1 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 /*
16 The cache has an interrupt that can be raised as soon as an access to a cached
17 region (flash, psram) is done without the cache being enabled. We use that here
18 to panic the CPU, which from a debugging perspective is better than grabbing bad
19 data from the bus.
20 */
21
22 #include <stdint.h>
23 #include <stdio.h>
24 #include <stdlib.h>
25 #include <stdbool.h>
26
27 #include "esp_err.h"
28 #include "esp_attr.h"
29
30 #include "esp_intr_alloc.h"
31 #include "soc/dport_reg.h"
32 #include "hal/cpu_hal.h"
33
34 #include "esp32/dport_access.h"
35 #include "esp32/rom/ets_sys.h" // for intr_matrix_set
36
37 #include "sdkconfig.h"
38
esp_cache_err_int_init(void)39 void esp_cache_err_int_init(void)
40 {
41 uint32_t core_id = cpu_hal_get_core_id();
42 ESP_INTR_DISABLE(ETS_MEMACCESS_ERR_INUM);
43
44 // We do not register a handler for the interrupt because it is interrupt
45 // level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
46 // a call to the panic handler for
47 // this interrupt.
48 intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_MEMACCESS_ERR_INUM);
49
50 // Enable invalid cache access interrupt when the cache is disabled.
51 // When the interrupt happens, we can not determine the CPU where the
52 // invalid cache access has occurred. We enable the interrupt to catch
53 // invalid access on both CPUs, but the interrupt is connected to the
54 // CPU which happens to call this function.
55 // For this reason, panic handler backtrace will not be correct if the
56 // interrupt is connected to PRO CPU and invalid access happens on the APP
57 // CPU.
58
59 if (core_id == PRO_CPU_NUM) {
60 DPORT_SET_PERI_REG_MASK(DPORT_CACHE_IA_INT_EN_REG,
61 DPORT_CACHE_IA_INT_PRO_OPPOSITE |
62 DPORT_CACHE_IA_INT_PRO_DRAM1 |
63 DPORT_CACHE_IA_INT_PRO_DROM0 |
64 DPORT_CACHE_IA_INT_PRO_IROM0 |
65 DPORT_CACHE_IA_INT_PRO_IRAM0 |
66 DPORT_CACHE_IA_INT_PRO_IRAM1);
67 } else {
68 DPORT_SET_PERI_REG_MASK(DPORT_CACHE_IA_INT_EN_REG,
69 DPORT_CACHE_IA_INT_APP_OPPOSITE |
70 DPORT_CACHE_IA_INT_APP_DRAM1 |
71 DPORT_CACHE_IA_INT_APP_DROM0 |
72 DPORT_CACHE_IA_INT_APP_IROM0 |
73 DPORT_CACHE_IA_INT_APP_IRAM0 |
74 DPORT_CACHE_IA_INT_APP_IRAM1);
75 }
76 ESP_INTR_ENABLE(ETS_MEMACCESS_ERR_INUM);
77 }
78
esp_cache_err_get_cpuid(void)79 int IRAM_ATTR esp_cache_err_get_cpuid(void)
80 {
81 const uint32_t pro_mask =
82 DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1 |
83 DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0 |
84 DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0 |
85 DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0 |
86 DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1 |
87 DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE;
88
89 if (DPORT_GET_PERI_REG_MASK(DPORT_PRO_DCACHE_DBUG3_REG, pro_mask)) {
90 return PRO_CPU_NUM;
91 }
92
93 const uint32_t app_mask =
94 DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1 |
95 DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0 |
96 DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0 |
97 DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0 |
98 DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1 |
99 DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE;
100
101 if (DPORT_GET_PERI_REG_MASK(DPORT_APP_DCACHE_DBUG3_REG, app_mask)) {
102 return APP_CPU_NUM;
103 }
104 return -1;
105 }
106
