1/*
2 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6/**
7 *                    ESP32-S3 Linker Script Memory Layout
8 * This file describes the memory layout (memory blocks) by virtual memory addresses.
9 * This linker script is passed through the C preprocessor to include configuration options.
10 * Please use preprocessor features sparingly!
11 * Restrict to simple macros with numeric values, and/or #if/#endif blocks.
12 */
13
14#include "sdkconfig.h"
15#include "ld.common"
16
17#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
18#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)
19#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP)
20#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)
21#else
22#define ESP_BOOTLOADER_RESERVE_RTC 0
23#endif
24
25/*
26 * 40370000 <- IRAM/Icache -> 40378000 <- D/IRAM (I) -> 403E0000
27 *                            3FC88000 <- D/IRAM (D) -> 3FCF0000 <- DRAM/DCache -> 3FD00000
28 *
29 * Startup code uses the IRAM from 0x403BA000 to 0x403E0000, which is not available for static
30 * memory, but can only be used after app starts.
31 *
32 * D cache use the memory from high address, so when it's configured to 16K/32K, the region
33 * 0x3FCF000 ~ (3FD00000 - DATA_CACHE_SIZE) should be available. This region is not used as
34 * static memory, leaving to the heap.
35 */
36
37#define SRAM_IRAM_START     0x40370000
38#define SRAM_DIRAM_I_START  0x40378000
39#define SRAM_IRAM_END       0x403BA000
40#define I_D_SRAM_OFFSET     (SRAM_DIRAM_I_START - SRAM_DRAM_START)
41
42#define SRAM_DRAM_START     0x3FC88000
43#define SRAM_DRAM_END       (SRAM_IRAM_END - I_D_SRAM_OFFSET)  /* 2nd stage bootloader iram_loader_seg start address */
44#define I_D_SRAM_SIZE       (SRAM_DRAM_END - SRAM_DRAM_START)
45
46
47#define ICACHE_SIZE         0x8000
48#define SRAM_IRAM_ORG       (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
49#define SRAM_IRAM_SIZE      (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
50
51#define DCACHE_SIZE         0x10000
52#define SRAM_DRAM_ORG       (SRAM_DRAM_START)
53
54#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
55ASSERT((CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), "Fixed static ram data does not fit.")
56#define DRAM0_0_SEG_LEN CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE
57#else
58#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
59#endif // CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
60
61MEMORY
62{
63  /**
64   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
65   *  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
66   *  are connected to the data port of the CPU and eg allow byte-wise access.
67   */
68
69  /* IRAM for PRO CPU. */
70  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE
71
72#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
73  /* Flash mapped instruction data */
74  iram0_2_seg (RX) :                 org = 0x42000020, len = 0x800000-0x20
75
76  /**
77   * (0x20 offset above is a convenience for the app binary image generation.
78   * Flash cache has 64KB pages. The .bin file which is flashed to the chip
79   * has a 0x18 byte file header, and each segment has a 0x08 byte segment
80   * header. Setting this offset makes it simple to meet the flash cache MMU's
81   * constraint that (paddr % 64KB == vaddr % 64KB).)
82   */
83#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
84
85  /**
86   * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
87   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
88   */
89  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
90
91#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
92  /* Flash mapped constant data */
93  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x800000-0x20
94
95  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
96#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
97
98  /**
99   * RTC fast memory (executable). Persists over deep sleep.
100   */
101  rtc_iram_seg(RWX) :                org = 0x600fe000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
102
103  /**
104   * RTC fast memory (same block as above), viewed from data bus
105   */
106  rtc_data_seg(RW) :                 org = 0x600fe000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
107
108  /**
109   * RTC slow memory (data accessible). Persists over deep sleep.
110   * Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
111   */
112  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM,
113                                     len = 0x2000 - CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM
114}
115
116#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
117/* static data ends at defined address */
118_static_data_end = 0x3FCA0000 + DRAM0_0_SEG_LEN;
119#else
120_static_data_end = _bss_end;
121#endif // CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
122
123/* Heap ends at top of dram0_0_seg */
124_heap_end = 0x40000000;
125
126_data_seg_org = ORIGIN(rtc_data_seg);
127
128#if CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
129REGION_ALIAS("rtc_data_location", rtc_data_seg );
130#else
131REGION_ALIAS("rtc_data_location", rtc_slow_seg );
132#endif // CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
133
134#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
135REGION_ALIAS("default_code_seg", iram0_2_seg);
136#else
137REGION_ALIAS("default_code_seg", iram0_0_seg);
138#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
139
140#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
141REGION_ALIAS("default_rodata_seg", drom0_0_seg);
142#else
143REGION_ALIAS("default_rodata_seg", dram0_0_seg);
144#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
145
146/**
147 *  If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
148 *  also be first in the segment.
149 */
150#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
151  ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
152         ".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
153#endif
154