1/*
2 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6/* ESP32S2 Linker Script Memory Layout
7
8   This file describes the memory layout (memory blocks) by virtual memory addresses.
9
10   This linker script is passed through the C preprocessor to include configuration options.
11
12   Please use preprocessor features sparingly!
13   Restrict to simple macros with numeric values, and/or #if/#endif blocks.
14*/
15#include "sdkconfig.h"
16#include "ld.common"
17
18#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
19#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)
20#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP)
21#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)
22#else
23#define ESP_BOOTLOADER_RESERVE_RTC 0
24#endif
25
26#ifdef CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
27#define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x2000
28#else
29#define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x4000
30#endif
31
32#ifdef CONFIG_ESP32S2_DATA_CACHE_0KB
33#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0
34#elif defined CONFIG_ESP32S2_DATA_CACHE_8KB
35#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x2000
36#else
37#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x4000
38#endif
39
40#define RAM_IRAM_START    0x40020000
41#define RAM_DRAM_START    0x3FFB0000
42
43#define DATA_RAM_END      0x3FFE0000  /* 2nd stage bootloader iram_loader_seg starts at SRAM block 14 (reclaimed after app boots) */
44
45#define IRAM_ORG    (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
46                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)
47
48#define DRAM_ORG    (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
49                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)
50
51#define I_D_RAM_SIZE   DATA_RAM_END - DRAM_ORG
52
53#if defined(CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE)
54
55ASSERT((CONFIG_ESP32S2_FIXED_STATIC_RAM_SIZE <= I_D_RAM_SIZE),
56          "Fixed static ram data does not fit.")
57
58#define STATIC_RAM_SIZE CONFIG_ESP32S2_FIXED_STATIC_RAM_SIZE
59
60#else
61#define STATIC_RAM_SIZE 0
62#endif
63
64MEMORY
65{
66  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
67  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
68  are connected to the data port of the CPU and eg allow bytewise access. */
69
70  /* IRAM for CPU.*/
71  iram0_0_seg (RX) :                 org = IRAM_ORG, len = I_D_RAM_SIZE
72
73#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
74  /* Even though the segment name is iram, it is actually mapped to flash
75  */
76  iram0_2_seg (RX) :                 org = 0x40080020, len = 0x780000-0x20
77
78  /*
79    (0x20 offset above is a convenience for the app binary image generation.
80    Flash cache has 64KB pages. The .bin file which is flashed to the chip
81    has a 0x18 byte file header, and each segment has a 0x08 byte segment
82    header. Setting this offset makes it simple to meet the flash cache MMU's
83    constraint that (paddr % 64KB == vaddr % 64KB).)
84  */
85#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
86
87
88  /* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack. */
89  dram0_0_seg (RW) :                 org = DRAM_ORG, len = I_D_RAM_SIZE - STATIC_RAM_SIZE
90
91#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
92  /* Flash mapped constant data */
93  drom0_0_seg (R) :                  org = 0x3F000020, len = 0x3f0000-0x20
94
95  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
96#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
97
98  /* RTC fast memory (executable). Persists over deep sleep.
99   */
100  rtc_iram_seg(RWX) :                org = 0x40070000, len = 0x2000
101
102  /* RTC slow memory (data accessible). Persists over deep sleep.
103
104     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
105  */
106  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM,
107                                     len = 0x2000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM
108
109  /* RTC fast memory (same block as above), viewed from data bus */
110  rtc_data_seg(RW) :                 org = 0x3ff9e000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
111
112  /* external memory, covers the dport, dram0, dram1 cacheable address space */
113  extern_ram_seg(RWX)  :             org = 0x3F500000,
114                                     len = 0xA80000
115}
116
117#if defined(CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE)
118/* static data ends at defined address */
119_static_data_end = DRAM_ORG + STATIC_RAM_SIZE;
120#else
121_static_data_end = _bss_end;
122#endif
123
124_heap_end = 0x40000000;
125
126_data_seg_org = ORIGIN(rtc_data_seg);
127
128/* The lines below define location alias for .rtc.data section based on Kconfig option.
129   When the option is not defined then use slow memory segment
130   else the data will be placed in fast memory segment
131   TODO: check whether the rtc_data_location is correct for esp32s2 - IDF-761 */
132#ifndef CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM
133REGION_ALIAS("rtc_data_location", rtc_slow_seg );
134#else
135REGION_ALIAS("rtc_data_location", rtc_data_seg );
136#endif
137
138#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
139  REGION_ALIAS("default_code_seg", iram0_2_seg);
140#else
141  REGION_ALIAS("default_code_seg", iram0_0_seg);
142#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
143
144#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
145  REGION_ALIAS("default_rodata_seg", drom0_0_seg);
146#else
147  REGION_ALIAS("default_rodata_seg", dram0_0_seg);
148#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
149
150
151/**
152 *  If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
153 *  also be first in the segment.
154 */
155#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
156  ASSERT(_rodata_reserved_start == ORIGIN(default_rodata_seg),
157         ".flash.appdesc section must be placed at the beginning of the rodata segment.")
158#endif
159