1/*
2 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/**
8 *                    ESP32-H2 Linker Script Memory Layout
9 * This file describes the memory layout (memory blocks) by virtual memory addresses.
10 * This linker script is passed through the C preprocessor to include configuration options.
11 * Please use preprocessor features sparingly!
12 * Restrict to simple macros with numeric values, and/or #if/#endif blocks.
13 */
14
15#include "sdkconfig.h"
16#include "ld.common"
17
18#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
19#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)
20#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP)
21#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)
22#else
23#define ESP_BOOTLOADER_RESERVE_RTC 0
24#endif
25
26#define SRAM_IRAM_START     0x4037C000
27#define SRAM_DRAM_START     0x3FC7C000
28#define ICACHE_SIZE         0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */
29#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)
30#define SRAM_DRAM_END       0x403D0000 - I_D_SRAM_OFFSET  /* 2nd stage bootloader iram_loader_seg start address */
31
32#define SRAM_IRAM_ORG       (SRAM_IRAM_START + ICACHE_SIZE)
33#define SRAM_DRAM_ORG       (SRAM_DRAM_START + ICACHE_SIZE)
34
35#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG
36
37#if CONFIG_ESP32H2_USE_FIXED_STATIC_RAM_SIZE
38ASSERT((CONFIG_ESP32H2_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), "Fixed static ram data does not fit.")
39#define DRAM0_0_SEG_LEN CONFIG_ESP3C3_FIXED_STATIC_RAM_SIZE
40#else
41#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
42#endif // CONFIG_ESP32H2_USE_FIXED_STATIC_RAM_SIZE
43MEMORY
44{
45  /**
46   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
47   *  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
48   *  are connected to the data port of the CPU and eg allow byte-wise access.
49   */
50
51  /* IRAM for PRO CPU. */
52  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
53
54#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
55  /* Flash mapped instruction data */
56  iram0_2_seg (RX) :                 org = 0x42000020, len = 0x800000-0x20
57
58  /**
59   * (0x20 offset above is a convenience for the app binary image generation.
60   * Flash cache has 64KB pages. The .bin file which is flashed to the chip
61   * has a 0x18 byte file header, and each segment has a 0x08 byte segment
62   * header. Setting this offset makes it simple to meet the flash cache MMU's
63   * constraint that (paddr % 64KB == vaddr % 64KB).)
64   */
65#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
66
67  /**
68   * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
69   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
70   */
71  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
72
73#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
74  /* Flash mapped constant data */
75  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x800000-0x20
76
77  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
78#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
79
80  /**
81   * RTC fast memory (executable). Persists over deep sleep.
82   */
83  rtc_iram_seg(RWX) :                org = 0x50000000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
84}
85
86#if CONFIG_ESP32H2_USE_FIXED_STATIC_RAM_SIZE
87/* static data ends at defined address */
88_static_data_end = 0x3FCA0000 + DRAM0_0_SEG_LEN;
89#else
90_static_data_end = _bss_end;
91#endif // CONFIG_ESP32H2_USE_FIXED_STATIC_RAM_SIZE
92
93/* Heap ends at top of dram0_0_seg */
94_heap_end = 0x40000000;
95
96_data_seg_org = ORIGIN(rtc_data_seg);
97
98/**
99 *  The lines below define location alias for .rtc.data section
100 *  As C3 only has RTC fast memory, this is not configurable like on other targets
101 */
102REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
103REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
104REGION_ALIAS("rtc_data_location", rtc_iram_seg );
105
106#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
107  REGION_ALIAS("default_code_seg", iram0_2_seg);
108#else
109  REGION_ALIAS("default_code_seg", iram0_0_seg);
110#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
111
112#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
113  REGION_ALIAS("default_rodata_seg", drom0_0_seg);
114#else
115  REGION_ALIAS("default_rodata_seg", dram0_0_seg);
116#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
117
118/**
119 *  If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
120 *  also be first in the segment.
121 */
122#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
123  ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
124         ".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
125#endif
126
127#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
128    ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!");
129    ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!");
130#endif
131