1/*
2 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6/* ESP32 Linker Script Memory Layout
7
8   This file describes the memory layout (memory blocks) as virtual
9   memory addresses.
10
11   esp32.project.ld contains output sections to link compiler output
12   into these memory blocks.
13
14   ***
15
16   This linker script is passed through the C preprocessor to include
17   configuration options.
18
19   Please use preprocessor features sparingly! Restrict
20   to simple macros with numeric values, and/or #if/#endif blocks.
21*/
22#include "sdkconfig.h"
23#include "ld.common"
24
25/* If BT is not built at all */
26#ifndef CONFIG_BTDM_RESERVE_DRAM
27#define CONFIG_BTDM_RESERVE_DRAM 0
28#endif
29
30#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
31#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)
32#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP)
33#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)
34#else
35#define ESP_BOOTLOADER_RESERVE_RTC 0
36#endif
37
38#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE)
39
40ASSERT((CONFIG_ESP32_FIXED_STATIC_RAM_SIZE <= 0x2c200),
41          "Fixed static ram data does not fit.")
42
43#define DRAM0_0_SEG_LEN CONFIG_ESP32_FIXED_STATIC_RAM_SIZE
44
45#else
46#define DRAM0_0_SEG_LEN 0x2c200
47#endif
48
49MEMORY
50{
51  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
52  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
53  are connected to the data port of the CPU and eg allow bytewise access. */
54
55  /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
56  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000
57
58#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
59  /* Even though the segment name is iram, it is actually mapped to flash
60  */
61  iram0_2_seg (RX) :                 org = 0x400D0020, len = 0x330000-0x20
62
63  /*
64    (0x20 offset above is a convenience for the app binary image generation.
65    Flash cache has 64KB pages. The .bin file which is flashed to the chip
66    has a 0x18 byte file header, and each segment has a 0x08 byte segment
67    header. Setting this offset makes it simple to meet the flash cache MMU's
68    constraint that (paddr % 64KB == vaddr % 64KB).)
69  */
70#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
71
72
73  /* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
74
75     Enabling Bluetooth & Trace Memory features in menuconfig will decrease
76     the amount of RAM available.
77
78     Note: Length of this section *should* be 0x50000, and this extra DRAM is available
79     in heap at runtime. However due to static ROM memory usage at this 176KB mark, the
80     additional static memory temporarily cannot be used.
81  */
82  dram0_0_seg (RW) :                 org = 0x3FFB0000 + CONFIG_BTDM_RESERVE_DRAM,
83                                     len = DRAM0_0_SEG_LEN - CONFIG_BTDM_RESERVE_DRAM
84
85#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
86  /* Flash mapped constant data */
87  drom0_0_seg (R) :                  org = 0x3F400020, len = 0x400000-0x20
88
89  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
90#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
91
92  /* RTC fast memory (executable). Persists over deep sleep.
93   */
94  rtc_iram_seg(RWX) :                org = 0x400C0000, len = 0x2000
95
96  /* RTC fast memory (same block as above), viewed from data bus */
97  rtc_data_seg(RW) :                 org = 0x3ff80000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
98
99  /* RTC slow memory (data accessible). Persists over deep sleep.
100
101     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
102  */
103  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32_ULP_COPROC_RESERVE_MEM,
104                                     len = 0x2000 - CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
105
106  /* external memory */
107  extern_ram_seg(RWX)  :             org = 0x3F800000,
108                                     len = 0x400000
109}
110
111#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE)
112/* static data ends at defined address */
113_static_data_end = 0x3FFB0000 + DRAM0_0_SEG_LEN;
114#else
115_static_data_end = _bss_end;
116#endif
117
118/* Heap ends at top of dram0_0_seg */
119_heap_end = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM;
120
121_data_seg_org = ORIGIN(rtc_data_seg);
122
123/* The lines below define location alias for .rtc.data section based on Kconfig option.
124   When the option is not defined then use slow memory segment
125   else the data will be placed in fast memory segment */
126#ifndef CONFIG_ESP32_RTCDATA_IN_FAST_MEM
127REGION_ALIAS("rtc_data_location", rtc_slow_seg );
128#else
129REGION_ALIAS("rtc_data_location", rtc_data_seg );
130#endif
131
132#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
133  REGION_ALIAS("default_code_seg", iram0_2_seg);
134#else
135  REGION_ALIAS("default_code_seg", iram0_0_seg);
136#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
137
138#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
139  REGION_ALIAS("default_rodata_seg", drom0_0_seg);
140#else
141  REGION_ALIAS("default_rodata_seg", dram0_0_seg);
142#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
143
144/**
145 *  If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
146 *  also be first in the segment.
147 */
148#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
149  ASSERT(_rodata_start == ORIGIN(default_rodata_seg),
150         ".flash.appdesc section must be placed at the beginning of the rodata segment.")
151#endif
152