1 // Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 #include <stdint.h> 17 #include <stdbool.h> 18 #include "esp_attr.h" 19 20 #ifdef __cplusplus 21 extern "C" { 22 #endif 23 24 /** \defgroup spi_flash_apis, spi flash operation related apis 25 * @brief spi_flash apis 26 */ 27 28 /** @addtogroup spi_flash_apis 29 * @{ 30 */ 31 32 /************************************************************* 33 * Note 34 ************************************************************* 35 * 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is 36 * used as an SPI master to access Flash and ext-SRAM by 37 * Cache module. It will support Decryto read for Flash, 38 * read/write for ext-SRAM. And SPI1 is also used as an 39 * SPI master for Flash read/write and ext-SRAM read/write. 40 * It will support Encrypto write for Flash. 41 * 2. As an SPI master, SPI support Highest clock to 80M, 42 * however, Flash with 80M Clock should be configured 43 * for different Flash chips. If you want to use 80M 44 * clock We should use the SPI that is certified by 45 * Espressif. However, the certification is not started 46 * at the time, so please use 40M clock at the moment. 47 * 3. SPI Flash can use 2 lines or 4 lines mode. If you 48 * use 2 lines mode, you can save two pad SPIHD and 49 * SPIWP for gpio. ESP32 support configured SPI pad for 50 * Flash, the configuration is stored in efuse and flash. 51 * However, the configurations of pads should be certified 52 * by Espressif. If you use this function, please use 40M 53 * clock at the moment. 54 * 4. ESP32 support to use Common SPI command to configure 55 * Flash to QIO mode, if you failed to configure with fix 56 * command. With Common SPI Command, ESP32 can also provide 57 * a way to use same Common SPI command groups on different 58 * Flash chips. 59 * 5. This functions are not protected by packeting, Please use the 60 ************************************************************* 61 */ 62 63 #define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1) 64 #define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1) 65 #define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1) 66 #define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1) 67 #define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1) 68 #define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1) 69 #define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1) 70 #define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1) 71 #define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1) 72 #define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1) 73 #define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1) 74 #define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1) 75 #define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1) 76 #define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1) 77 #define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1) 78 #define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) 79 #define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) 80 81 #define SPI0_R_QIO_DUMMY_CYCLELEN 5 82 #define SPI0_R_QIO_ADDR_BITSLEN 23 83 #define SPI0_R_FAST_DUMMY_CYCLELEN 7 84 #define SPI0_R_DIO_DUMMY_CYCLELEN 3 85 #define SPI0_R_FAST_ADDR_BITSLEN 23 86 #define SPI0_R_SIO_ADDR_BITSLEN 23 87 88 #define SPI1_R_QIO_DUMMY_CYCLELEN 5 89 #define SPI1_R_QIO_ADDR_BITSLEN 23 90 #define SPI1_R_FAST_DUMMY_CYCLELEN 7 91 #define SPI1_R_DIO_DUMMY_CYCLELEN 3 92 #define SPI1_R_DIO_ADDR_BITSLEN 23 93 #define SPI1_R_FAST_ADDR_BITSLEN 23 94 #define SPI1_R_SIO_ADDR_BITSLEN 23 95 96 #define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 97 98 #define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B 99 100 //SPI address register 101 #define ESP_ROM_SPIFLASH_BYTES_LEN 24 102 #define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 103 #define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16 104 #define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf 105 106 //SPI status register 107 #define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 108 #define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 109 #define ESP_ROM_SPIFLASH_BP0 BIT2 110 #define ESP_ROM_SPIFLASH_BP1 BIT3 111 #define ESP_ROM_SPIFLASH_BP2 BIT4 112 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) 113 #define ESP_ROM_SPIFLASH_QE BIT9 114 115 #define FLASH_ID_GD25LQ32C 0xC86016 116 117 typedef enum { 118 ESP_ROM_SPIFLASH_QIO_MODE = 0, 119 ESP_ROM_SPIFLASH_QOUT_MODE, 120 ESP_ROM_SPIFLASH_DIO_MODE, 121 ESP_ROM_SPIFLASH_DOUT_MODE, 122 ESP_ROM_SPIFLASH_FASTRD_MODE, 123 ESP_ROM_SPIFLASH_SLOWRD_MODE, 124 ESP_ROM_SPIFLASH_OPI_STR_MODE, 125 ESP_ROM_SPIFLASH_OPI_DTR_MODE, 126 ESP_ROM_SPIFLASH_OOUT_MODE, 127 ESP_ROM_SPIFLASH_OIO_STR_MODE, 128 ESP_ROM_SPIFLASH_OIO_DTR_MODE, 129 } esp_rom_spiflash_read_mode_t; 130 131 typedef enum { 132 ESP_ROM_SPIFLASH_RESULT_OK, 133 ESP_ROM_SPIFLASH_RESULT_ERR, 134 ESP_ROM_SPIFLASH_RESULT_TIMEOUT 135 } esp_rom_spiflash_result_t; 136 137 typedef struct { 138 uint32_t device_id; 139 uint32_t chip_size; // chip size in bytes 140 uint32_t block_size; 141 uint32_t sector_size; 142 uint32_t page_size; 143 uint32_t status_mask; 144 } esp_rom_spiflash_chip_t; 145 146 typedef struct { 147 uint8_t data_length; 148 uint8_t read_cmd0; 149 uint8_t read_cmd1; 150 uint8_t write_cmd; 151 uint16_t data_mask; 152 uint16_t data; 153 } esp_rom_spiflash_common_cmd_t; 154 155 typedef void (*spi_flash_func_t)(void); 156 typedef esp_rom_spiflash_result_t (*spi_flash_op_t)(void); 157 typedef esp_rom_spiflash_result_t (*spi_flash_erase_t)(uint32_t); 158 typedef esp_rom_spiflash_result_t (*spi_flash_rd_t)(uint32_t, void*, int); 159 typedef esp_rom_spiflash_result_t (*spi_flash_wr_t)(uint32_t, const uint32_t*, int); 160 typedef esp_rom_spiflash_result_t (*spi_flash_ewr_t)(uint32_t, const void*, uint32_t); 161 typedef esp_rom_spiflash_result_t (*spi_flash_wren_t)(void*); 162 typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t); 163 164 typedef struct { 165 uint8_t pp_addr_bit_len; 166 uint8_t se_addr_bit_len; 167 uint8_t be_addr_bit_len; 168 uint8_t rd_addr_bit_len; 169 uint32_t read_sub_len; 170 uint32_t write_sub_len; 171 spi_flash_op_t unlock; 172 spi_flash_erase_t erase_sector; 173 spi_flash_erase_t erase_block; 174 spi_flash_rd_t read; 175 spi_flash_wr_t write; 176 spi_flash_ewr_t encrypt_write; 177 spi_flash_func_t check_sus; 178 spi_flash_wren_t wren; 179 spi_flash_op_t wait_idle; 180 spi_flash_erase_area_t erase_area; 181 } spiflash_legacy_funcs_t; 182 183 184 /** 185 * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. 186 * Please do not call this function in SDK. 187 * 188 * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). 189 * 190 * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. 191 * 192 * @return None 193 */ 194 void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); 195 196 /** 197 * @brief Select SPI Flash to QIO mode when WP pad is read from Flash. 198 * Please do not call this function in SDK. 199 * 200 * @param uint8_t wp_gpio_num: WP gpio number. 201 * 202 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 203 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 204 * 205 * @return None 206 */ 207 void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi); 208 209 /** 210 * @brief Set SPI Flash pad drivers. 211 * Please do not call this function in SDK. 212 * 213 * @param uint8_t wp_gpio_num: WP gpio number. 214 * 215 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 216 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 217 * 218 * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid 219 * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. 220 * Values usually read from falsh by rom code, function usually callde by rom code. 221 * if value with bit(3) set, the value is valid, bit[2:0] is the real value. 222 * 223 * @return None 224 */ 225 void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); 226 227 /** 228 * @brief Select SPI Flash function for pads. 229 * Please do not call this function in SDK. 230 * 231 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 232 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 233 * 234 * @return None 235 */ 236 void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); 237 238 /** 239 * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode. 240 * Please do not call this function in SDK. 241 * 242 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 243 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 244 * 245 * @param uint8_t legacy: In legacy mode, more SPI command is used in line. 246 * 247 * @return None 248 */ 249 void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); 250 251 /** 252 * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). 253 * Please do not call this function in SDK. 254 * 255 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 256 * 257 * @param uint32_t *status : The pointer to which to return the Flash status value. 258 * 259 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 260 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 261 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 262 */ 263 esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); 264 265 /** 266 * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). 267 * Please do not call this function in SDK. 268 * 269 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 270 * 271 * @param uint32_t *status : The pointer to which to return the Flash status value. 272 * 273 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 274 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 275 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 276 */ 277 esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); 278 279 /** 280 * @brief Write status to Falsh status register. 281 * Please do not call this function in SDK. 282 * 283 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 284 * 285 * @param uint32_t status_value : Value to . 286 * 287 * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. 288 * ESP_ROM_SPIFLASH_RESULT_ERR : write error. 289 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. 290 */ 291 esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); 292 293 /** 294 * @brief Use a command to Read Flash status register. 295 * Please do not call this function in SDK. 296 * 297 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 298 * 299 * @param uint32_t*status : The pointer to which to return the Flash status value. 300 * 301 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 302 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 303 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 304 */ 305 esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); 306 307 /** 308 * @brief Config SPI Flash read mode when init. 309 * Please do not call this function in SDK. 310 * 311 * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. 312 * 313 * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. 314 * 315 * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. 316 * ESP_ROM_SPIFLASH_RESULT_ERR : config error. 317 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. 318 */ 319 esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); 320 321 /** 322 * @brief Config SPI Flash clock divisor. 323 * Please do not call this function in SDK. 324 * 325 * @param uint8_t freqdiv: clock divisor. 326 * 327 * @param uint8_t spi: 0 for SPI0, 1 for SPI1. 328 * 329 * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. 330 * ESP_ROM_SPIFLASH_RESULT_ERR : config error. 331 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. 332 */ 333 esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); 334 335 /** 336 * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. 337 * Please do not call this function in SDK. 338 * 339 * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. 340 * 341 * @return uint16_t 0 : do not send command any more. 342 * 1 : go to the next command. 343 * n > 1 : skip (n - 1) commands. 344 */ 345 uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); 346 347 /** 348 * @brief Unlock SPI write protect. 349 * Please do not call this function in SDK. 350 * 351 * @param None. 352 * 353 * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. 354 * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. 355 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. 356 */ 357 esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); 358 359 /** 360 * @brief SPI write protect. 361 * Please do not call this function in SDK. 362 * 363 * @param None. 364 * 365 * @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK. 366 * ESP_ROM_SPIFLASH_RESULT_ERR : Lock error. 367 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout. 368 */ 369 esp_rom_spiflash_result_t esp_rom_spiflash_lock(void); 370 371 /** 372 * @brief Update SPI Flash parameter. 373 * Please do not call this function in SDK. 374 * 375 * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. 376 * 377 * @param uint32_t chip_size : The Flash size. 378 * 379 * @param uint32_t block_size : The Flash block size. 380 * 381 * @param uint32_t sector_size : The Flash sector size. 382 * 383 * @param uint32_t page_size : The Flash page size. 384 * 385 * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). 386 * 387 * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. 388 * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. 389 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. 390 */ 391 esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, 392 uint32_t sector_size, uint32_t page_size, uint32_t status_mask); 393 394 /** 395 * @brief Erase whole flash chip. 396 * Please do not call this function in SDK. 397 * 398 * @param None 399 * 400 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 401 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 402 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 403 */ 404 esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); 405 406 /** 407 * @brief Erase a 64KB block of flash 408 * Uses SPI flash command D8H. 409 * Please do not call this function in SDK. 410 * 411 * @param uint32_t block_num : Which block to erase. 412 * 413 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 414 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 415 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 416 */ 417 esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); 418 419 /** 420 * @brief Erase a sector of flash. 421 * Uses SPI flash command 20H. 422 * Please do not call this function in SDK. 423 * 424 * @param uint32_t sector_num : Which sector to erase. 425 * 426 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 427 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 428 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 429 */ 430 esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); 431 432 /** 433 * @brief Erase some sectors. 434 * Please do not call this function in SDK. 435 * 436 * @param uint32_t start_addr : Start addr to erase, should be sector aligned. 437 * 438 * @param uint32_t area_len : Length to erase, should be sector aligned. 439 * 440 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 441 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 442 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 443 */ 444 esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); 445 446 /** 447 * @brief Write Data to Flash, you should Erase it yourself if need. 448 * Please do not call this function in SDK. 449 * 450 * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. 451 * 452 * @param const uint32_t *src : The pointer to data which is to write. 453 * 454 * @param uint32_t len : Length to write, should be 4 bytes aligned. 455 * 456 * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. 457 * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. 458 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. 459 */ 460 esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); 461 462 /** 463 * @brief Read Data from Flash, you should Erase it yourself if need. 464 * Please do not call this function in SDK. 465 * 466 * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. 467 * 468 * @param uint32_t *dest : The buf to read the data. 469 * 470 * @param uint32_t len : Length to read, should be 4 bytes aligned. 471 * 472 * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. 473 * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. 474 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. 475 */ 476 esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); 477 478 /** 479 * @brief SPI1 go into encrypto mode. 480 * Please do not call this function in SDK. 481 * 482 * @param None 483 * 484 * @return None 485 */ 486 void esp_rom_spiflash_write_encrypted_enable(void); 487 488 /** 489 * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. 490 * Please do not call this function in SDK. 491 * 492 * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. 493 * 494 * @param uint32_t *data : The pointer to data which is to write. 495 * 496 * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. 497 * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. 498 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. 499 */ 500 esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); 501 502 /** 503 * @brief SPI1 go out of encrypto mode. 504 * Please do not call this function in SDK. 505 * 506 * @param None 507 * 508 * @return None 509 */ 510 void esp_rom_spiflash_write_encrypted_disable(void); 511 512 /** 513 * @brief Write data to flash with transparent encryption. 514 * @note Sectors to be written should already be erased. 515 * 516 * @note Please do not call this function in SDK. 517 * 518 * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. 519 * 520 * @param uint32_t *data : The pointer to data to write. Note, this pointer must 521 * be 32 bit aligned and the content of the data will be 522 * modified by the encryption function. 523 * 524 * @param uint32_t len : Length to write, should be 32 bytes aligned. 525 * 526 * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. 527 * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. 528 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. 529 */ 530 esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); 531 532 533 /* TODO: figure out how to map these to their new names */ 534 typedef enum { 535 SPI_ENCRYPT_DESTINATION_FLASH, 536 SPI_ENCRYPT_DESTINATION_PSRAM, 537 } SpiEncryptDest; 538 539 typedef esp_rom_spiflash_result_t SpiFlashOpResult; 540 541 SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void *data, uint32_t len); 542 SpiFlashOpResult SPI_Encrypt_Write_Dest(SpiEncryptDest dest, uint32_t flash_addr, const void *data, uint32_t len); 543 void SPI_Write_Encrypt_Enable(void); 544 void SPI_Write_Encrypt_Disable(void); 545 546 /** @brief Wait until SPI flash write operation is complete 547 * 548 * @note Please do not call this function in SDK. 549 * 550 * Reads the Write In Progress bit of the SPI flash status register, 551 * repeats until this bit is zero (indicating write complete). 552 * 553 * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete 554 * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. 555 */ 556 esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); 557 558 559 /** @brief Enable Quad I/O pin functions 560 * 561 * @note Please do not call this function in SDK. 562 * 563 * Sets the HD & WP pin functions for Quad I/O modes, based on the 564 * efuse SPI pin configuration. 565 * 566 * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. 567 * 568 * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). 569 * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. 570 * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. 571 * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used 572 * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). 573 * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. 574 */ 575 void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig); 576 577 /** 578 * @brief Clear WEL bit unconditionally. 579 * 580 * @return always ESP_ROM_SPIFLASH_RESULT_OK 581 */ 582 esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void); 583 typedef struct { 584 esp_rom_spiflash_chip_t chip; 585 uint8_t dummy_len_plus[3]; 586 uint8_t sig_matrix; 587 } spiflash_legacy_data_t; 588 589 extern spiflash_legacy_data_t *rom_spiflash_legacy_data; 590 591 #define g_rom_flashchip (rom_spiflash_legacy_data->chip) 592 #define g_rom_spiflash_dummy_len_plus (rom_spiflash_legacy_data->dummy_len_plus) 593 594 #ifdef __cplusplus 595 } 596 #endif 597
