1 // Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef _ROM_SPI_FLASH_H_ 16 #define _ROM_SPI_FLASH_H_ 17 18 #ifndef CONFIG_IDF_TARGET_ESP32S2 19 #error This file should only be included for ESP32-S2 target 20 #endif 21 22 #include <stdint.h> 23 #include <stdbool.h> 24 25 #include "esp_attr.h" 26 #include "soc/spi_mem_reg.h" 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /** \defgroup spi_flash_apis, spi flash operation related apis 33 * @brief spi_flash apis 34 */ 35 36 /** @addtogroup spi_flash_apis 37 * @{ 38 */ 39 40 /************************************************************* 41 * Note 42 ************************************************************* 43 * 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is 44 * used as an SPI master to access Flash and ext-SRAM by 45 * Cache module. It will support Decryto read for Flash, 46 * read/write for ext-SRAM. And SPI1 is also used as an 47 * SPI master for Flash read/write and ext-SRAM read/write. 48 * It will support Encrypto write for Flash. 49 * 2. As an SPI master, SPI support Highest clock to 80M, 50 * however, Flash with 80M Clock should be configured 51 * for different Flash chips. If you want to use 80M 52 * clock We should use the SPI that is certified by 53 * Espressif. However, the certification is not started 54 * at the time, so please use 40M clock at the moment. 55 * 3. SPI Flash can use 2 lines or 4 lines mode. If you 56 * use 2 lines mode, you can save two pad SPIHD and 57 * SPIWP for gpio. ESP32 support configured SPI pad for 58 * Flash, the configuration is stored in efuse and flash. 59 * However, the configurations of pads should be certified 60 * by Espressif. If you use this function, please use 40M 61 * clock at the moment. 62 * 4. ESP32 support to use Common SPI command to configure 63 * Flash to QIO mode, if you failed to configure with fix 64 * command. With Common SPI Command, ESP32 can also provide 65 * a way to use same Common SPI command groups on different 66 * Flash chips. 67 * 5. This functions are not protected by packeting, Please use the 68 ************************************************************* 69 */ 70 71 #define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1) 72 #define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1) 73 #define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1) 74 #define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1) 75 #define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1) 76 #define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1) 77 #define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1) 78 #define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1) 79 #define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1) 80 #define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1) 81 #define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1) 82 #define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1) 83 #define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1) 84 #define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1) 85 #define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1) 86 #define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) 87 #define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) 88 89 #define SPI0_R_QIO_DUMMY_CYCLELEN 5 90 #define SPI0_R_QIO_ADDR_BITSLEN 23 91 #define SPI0_R_FAST_DUMMY_CYCLELEN 7 92 #define SPI0_R_DIO_DUMMY_CYCLELEN 3 93 #define SPI0_R_FAST_ADDR_BITSLEN 23 94 #define SPI0_R_SIO_ADDR_BITSLEN 23 95 96 #define SPI1_R_QIO_DUMMY_CYCLELEN 5 97 #define SPI1_R_QIO_ADDR_BITSLEN 23 98 #define SPI1_R_FAST_DUMMY_CYCLELEN 7 99 #define SPI1_R_DIO_DUMMY_CYCLELEN 3 100 #define SPI1_R_DIO_ADDR_BITSLEN 23 101 #define SPI1_R_FAST_ADDR_BITSLEN 23 102 #define SPI1_R_SIO_ADDR_BITSLEN 23 103 104 #define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 105 106 #define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B 107 108 //SPI address register 109 #define ESP_ROM_SPIFLASH_BYTES_LEN 24 110 #define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 111 #define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16 112 #define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf 113 114 //SPI status register 115 #define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 116 #define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 117 #define ESP_ROM_SPIFLASH_BP0 BIT2 118 #define ESP_ROM_SPIFLASH_BP1 BIT3 119 #define ESP_ROM_SPIFLASH_BP2 BIT4 120 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) 121 #define ESP_ROM_SPIFLASH_QE BIT9 122 123 #define FLASH_ID_GD25LQ32C 0xC86016 124 125 typedef enum { 126 ESP_ROM_SPIFLASH_QIO_MODE = 0, 127 ESP_ROM_SPIFLASH_QOUT_MODE, 128 ESP_ROM_SPIFLASH_DIO_MODE, 129 ESP_ROM_SPIFLASH_DOUT_MODE, 130 ESP_ROM_SPIFLASH_FASTRD_MODE, 131 ESP_ROM_SPIFLASH_SLOWRD_MODE, 132 ESP_ROM_SPIFLASH_OPI_STR_MODE, 133 ESP_ROM_SPIFLASH_OPI_DTR_MODE, 134 ESP_ROM_SPIFLASH_OOUT_MODE, 135 ESP_ROM_SPIFLASH_OIO_STR_MODE, 136 ESP_ROM_SPIFLASH_OIO_DTR_MODE, 137 } esp_rom_spiflash_read_mode_t; 138 139 typedef enum { 140 ESP_ROM_SPIFLASH_RESULT_OK, 141 ESP_ROM_SPIFLASH_RESULT_ERR, 142 ESP_ROM_SPIFLASH_RESULT_TIMEOUT 143 } esp_rom_spiflash_result_t; 144 145 typedef struct { 146 uint32_t device_id; 147 uint32_t chip_size; // chip size in bytes 148 uint32_t block_size; 149 uint32_t sector_size; 150 uint32_t page_size; 151 uint32_t status_mask; 152 } esp_rom_spiflash_chip_t; 153 154 typedef struct { 155 uint8_t data_length; 156 uint8_t read_cmd0; 157 uint8_t read_cmd1; 158 uint8_t write_cmd; 159 uint16_t data_mask; 160 uint16_t data; 161 } esp_rom_spiflash_common_cmd_t; 162 163 /** 164 * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. 165 * Please do not call this function in SDK. 166 * 167 * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). 168 * 169 * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. 170 * 171 * @return None 172 */ 173 void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); 174 175 /** 176 * @brief Select SPI Flash to QIO mode when WP pad is read from Flash. 177 * Please do not call this function in SDK. 178 * 179 * @param uint8_t wp_gpio_num: WP gpio number. 180 * 181 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 182 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 183 * 184 * @return None 185 */ 186 void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi); 187 188 /** 189 * @brief Set SPI Flash pad drivers. 190 * Please do not call this function in SDK. 191 * 192 * @param uint8_t wp_gpio_num: WP gpio number. 193 * 194 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 195 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 196 * 197 * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid 198 * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. 199 * Values usually read from falsh by rom code, function usually callde by rom code. 200 * if value with bit(3) set, the value is valid, bit[2:0] is the real value. 201 * 202 * @return None 203 */ 204 void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); 205 206 /** 207 * @brief Select SPI Flash function for pads. 208 * Please do not call this function in SDK. 209 * 210 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 211 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 212 * 213 * @return None 214 */ 215 void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); 216 217 /** 218 * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode. 219 * Please do not call this function in SDK. 220 * 221 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 222 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 223 * 224 * @param uint8_t legacy: In legacy mode, more SPI command is used in line. 225 * 226 * @return None 227 */ 228 void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); 229 230 /** 231 * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). 232 * Please do not call this function in SDK. 233 * 234 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 235 * 236 * @param uint32_t *status : The pointer to which to return the Flash status value. 237 * 238 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 239 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 240 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 241 */ 242 esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); 243 244 /** 245 * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). 246 * Please do not call this function in SDK. 247 * 248 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 249 * 250 * @param uint32_t *status : The pointer to which to return the Flash status value. 251 * 252 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 253 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 254 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 255 */ 256 esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); 257 258 /** 259 * @brief Write status to Falsh status register. 260 * Please do not call this function in SDK. 261 * 262 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 263 * 264 * @param uint32_t status_value : Value to . 265 * 266 * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. 267 * ESP_ROM_SPIFLASH_RESULT_ERR : write error. 268 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. 269 */ 270 esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); 271 272 /** 273 * @brief Use a command to Read Flash status register. 274 * Please do not call this function in SDK. 275 * 276 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 277 * 278 * @param uint32_t*status : The pointer to which to return the Flash status value. 279 * 280 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 281 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 282 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 283 */ 284 esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); 285 286 /** 287 * @brief Config SPI Flash read mode when init. 288 * Please do not call this function in SDK. 289 * 290 * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. 291 * 292 * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. 293 * 294 * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. 295 * ESP_ROM_SPIFLASH_RESULT_ERR : config error. 296 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. 297 */ 298 esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); 299 300 /** 301 * @brief Config SPI Flash clock divisor. 302 * Please do not call this function in SDK. 303 * 304 * @param uint8_t freqdiv: clock divisor. 305 * 306 * @param uint8_t spi: 0 for SPI0, 1 for SPI1. 307 * 308 * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. 309 * ESP_ROM_SPIFLASH_RESULT_ERR : config error. 310 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. 311 */ 312 esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); 313 314 /** 315 * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. 316 * Please do not call this function in SDK. 317 * 318 * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. 319 * 320 * @return uint16_t 0 : do not send command any more. 321 * 1 : go to the next command. 322 * n > 1 : skip (n - 1) commands. 323 */ 324 uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); 325 326 /** 327 * @brief Unlock SPI write protect. 328 * Please do not call this function in SDK. 329 * 330 * @param None. 331 * 332 * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. 333 * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. 334 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. 335 */ 336 esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); 337 338 /** 339 * @brief SPI write protect. 340 * Please do not call this function in SDK. 341 * 342 * @param None. 343 * 344 * @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK. 345 * ESP_ROM_SPIFLASH_RESULT_ERR : Lock error. 346 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout. 347 */ 348 esp_rom_spiflash_result_t esp_rom_spiflash_lock(void); 349 350 /** 351 * @brief Update SPI Flash parameter. 352 * Please do not call this function in SDK. 353 * 354 * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. 355 * 356 * @param uint32_t chip_size : The Flash size. 357 * 358 * @param uint32_t block_size : The Flash block size. 359 * 360 * @param uint32_t sector_size : The Flash sector size. 361 * 362 * @param uint32_t page_size : The Flash page size. 363 * 364 * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). 365 * 366 * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. 367 * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. 368 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. 369 */ 370 esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, 371 uint32_t sector_size, uint32_t page_size, uint32_t status_mask); 372 373 /** 374 * @brief Erase whole flash chip. 375 * Please do not call this function in SDK. 376 * 377 * @param None 378 * 379 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 380 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 381 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 382 */ 383 esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); 384 385 /** 386 * @brief Erase a 64KB block of flash 387 * Uses SPI flash command D8H. 388 * Please do not call this function in SDK. 389 * 390 * @param uint32_t block_num : Which block to erase. 391 * 392 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 393 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 394 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 395 */ 396 esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); 397 398 /** 399 * @brief Erase a sector of flash. 400 * Uses SPI flash command 20H. 401 * Please do not call this function in SDK. 402 * 403 * @param uint32_t sector_num : Which sector to erase. 404 * 405 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 406 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 407 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 408 */ 409 esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); 410 411 /** 412 * @brief Erase some sectors. 413 * Please do not call this function in SDK. 414 * 415 * @param uint32_t start_addr : Start addr to erase, should be sector aligned. 416 * 417 * @param uint32_t area_len : Length to erase, should be sector aligned. 418 * 419 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 420 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 421 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 422 */ 423 esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); 424 425 /** 426 * @brief Write Data to Flash, you should Erase it yourself if need. 427 * Please do not call this function in SDK. 428 * 429 * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. 430 * 431 * @param const uint32_t *src : The pointer to data which is to write. 432 * 433 * @param uint32_t len : Length to write, should be 4 bytes aligned. 434 * 435 * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. 436 * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. 437 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. 438 */ 439 esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); 440 441 /** 442 * @brief Read Data from Flash, you should Erase it yourself if need. 443 * Please do not call this function in SDK. 444 * 445 * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. 446 * 447 * @param uint32_t *dest : The buf to read the data. 448 * 449 * @param uint32_t len : Length to read, should be 4 bytes aligned. 450 * 451 * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. 452 * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. 453 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. 454 */ 455 esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); 456 457 /** 458 * @brief SPI1 go into encrypto mode. 459 * Please do not call this function in SDK. 460 * 461 * @param None 462 * 463 * @return None 464 */ 465 void esp_rom_spiflash_write_encrypted_enable(void); 466 467 /** 468 * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. 469 * Please do not call this function in SDK. 470 * 471 * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. 472 * 473 * @param uint32_t *data : The pointer to data which is to write. 474 * 475 * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. 476 * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. 477 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. 478 */ 479 esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); 480 481 /** 482 * @brief SPI1 go out of encrypto mode. 483 * Please do not call this function in SDK. 484 * 485 * @param None 486 * 487 * @return None 488 */ 489 void esp_rom_spiflash_write_encrypted_disable(void); 490 491 /** 492 * @brief Write data to flash with transparent encryption. 493 * @note Sectors to be written should already be erased. 494 * 495 * @note Please do not call this function in SDK. 496 * 497 * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. 498 * 499 * @param uint32_t *data : The pointer to data to write. Note, this pointer must 500 * be 32 bit aligned and the content of the data will be 501 * modified by the encryption function. 502 * 503 * @param uint32_t len : Length to write, should be 32 bytes aligned. 504 * 505 * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. 506 * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. 507 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. 508 */ 509 esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); 510 511 512 /* TODO: figure out how to map these to their new names */ 513 typedef enum { 514 SPI_ENCRYPT_DESTINATION_FLASH, 515 SPI_ENCRYPT_DESTINATION_PSRAM, 516 } SpiEncryptDest; 517 518 typedef esp_rom_spiflash_result_t SpiFlashOpResult; 519 520 SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void* data, uint32_t len); 521 SpiFlashOpResult SPI_Encrypt_Write_Dest(SpiEncryptDest dest, uint32_t flash_addr, const void* data, uint32_t len); 522 void SPI_Write_Encrypt_Enable(void); 523 void SPI_Write_Encrypt_Disable(void); 524 525 /** @brief Wait until SPI flash write operation is complete 526 * 527 * @note Please do not call this function in SDK. 528 * 529 * Reads the Write In Progress bit of the SPI flash status register, 530 * repeats until this bit is zero (indicating write complete). 531 * 532 * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete 533 * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. 534 */ 535 esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); 536 537 538 /** @brief Enable Quad I/O pin functions 539 * 540 * @note Please do not call this function in SDK. 541 * 542 * Sets the HD & WP pin functions for Quad I/O modes, based on the 543 * efuse SPI pin configuration. 544 * 545 * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. 546 * 547 * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). 548 * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. 549 * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. 550 * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used 551 * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). 552 * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. 553 */ 554 void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig); 555 556 /** 557 * @brief Clear WEL bit unconditionally. 558 * 559 * @return always ESP_ROM_SPIFLASH_RESULT_OK 560 */ 561 esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void); 562 563 /** @brief Global esp_rom_spiflash_chip_t structure used by ROM functions 564 * 565 */ 566 extern esp_rom_spiflash_chip_t g_rom_flashchip; 567 568 extern uint8_t g_rom_spiflash_dummy_len_plus[]; 569 570 /** 571 * @} 572 */ 573 574 #ifdef __cplusplus 575 } 576 #endif 577 578 #endif /* _ROM_SPI_FLASH_H_ */ 579
