1 /*
2 * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include "sdkconfig.h"
9 #include "soc/soc.h"
10 #include "soc/rtc.h"
11 #include "soc/rtc_cntl_reg.h"
12 #include "soc/efuse_periph.h"
13 #include "soc/gpio_reg.h"
14 #include "soc/spi_mem_reg.h"
15 #include "soc/extmem_reg.h"
16 #include "soc/system_reg.h"
17 #include "regi2c_ctrl.h"
18 #include "soc_log.h"
19 #include "esp_efuse.h"
20 #include "esp_efuse_table.h"
21
22 static const char *TAG = "rtc_init";
23
24 static void set_ocode_by_efuse(int calib_version);
25 static void calibrate_ocode(void);
26 static void set_rtc_dig_dbias(void);
27
rtc_init(rtc_config_t cfg)28 void rtc_init(rtc_config_t cfg)
29 {
30 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
31 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
32
33 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
34 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
35 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
36 REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN);
37
38 // set default powerup & wait time
39 rtc_init_config_t rtc_init_cfg = RTC_INIT_CONFIG_DEFAULT();
40 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles);
41 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles);
42 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, rtc_init_cfg.bt_powerup_cycles);
43 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, rtc_init_cfg.bt_wait_cycles);
44 REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_POWERUP_TIMER, rtc_init_cfg.cpu_top_powerup_cycles);
45 REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_WAIT_TIMER, rtc_init_cfg.cpu_top_wait_cycles);
46 REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, rtc_init_cfg.dg_wrap_powerup_cycles);
47 REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, rtc_init_cfg.dg_wrap_wait_cycles);
48 REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles);
49 REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles);
50
51 if (cfg.cali_ocode) {
52 uint32_t rtc_calib_version = 0;
53 esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3);
54 if (err != ESP_OK) {
55 rtc_calib_version = 0;
56 SOC_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version);
57 }
58 if (rtc_calib_version == 1) {
59 set_ocode_by_efuse(rtc_calib_version);
60 } else {
61 calibrate_ocode();
62 }
63 }
64
65 set_rtc_dig_dbias();
66
67 if (cfg.clkctl_init) {
68 //clear CMMU clock force on
69 CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON);
70 //clear tag clock force on
71 CLEAR_PERI_REG_MASK(EXTMEM_ICACHE_TAG_POWER_CTRL_REG, EXTMEM_ICACHE_TAG_MEM_FORCE_ON);
72 //clear register clock force on
73 CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN);
74 CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN);
75 }
76
77 if (cfg.pwrctl_init) {
78 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
79 //cancel xtal force pu if no need to force power up
80 //cannot cancel xtal force pu if pll is force power on
81 if (!(cfg.xtal_fpu | cfg.bbpll_fpu)) {
82 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
83 } else {
84 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
85 }
86 // force pd APLL
87 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
88 SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
89
90 //open sar_i2c protect function to avoid sar_i2c reset when rtc_ldo is low.
91 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);
92
93 //cancel bbpll force pu if setting no force power up
94 if (!cfg.bbpll_fpu) {
95 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
96 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
97 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
98 } else {
99 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
100 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
101 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
102 }
103
104 CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
105 CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
106
107 if (cfg.rtc_dboost_fpd) {
108 SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
109 } else {
110 CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
111 }
112
113 //clear i2c_reset_protect pd force, need tested in low temperature.
114 //CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_I2C_RESET_POR_FORCE_PD);
115
116 /* If this mask is enabled, all soc memories cannot enter power down mode */
117 /* We should control soc memory power down mode from RTC, so we will not touch this register any more */
118 CLEAR_PERI_REG_MASK(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK);
119
120 /* If this pd_cfg is set to 1, all memory won't enter low power mode during light sleep */
121 /* If this pd_cfg is set to 0, all memory will enter low power mode during light sleep */
122 rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(0);
123 rtc_sleep_pu(pu_cfg);
124
125 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
126 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
127 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU);
128 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU);
129 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU);
130
131 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO);
132 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
133 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO);
134 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO);
135 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO);
136 //cancel digital PADS force no iso
137 if (cfg.cpu_waiti_clk_gate) {
138 CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
139 } else {
140 SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
141 }
142 /*if SYSTEM_CPU_WAIT_MODE_FORCE_ON == 0 , the cpu clk will be closed when cpu enter WAITI mode*/
143 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
144 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
145 }
146 /* force power down wifi and bt power domain */
147 SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
148 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
149 /* force power down bt power domain */
150 SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_ISO);
151 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PD);
152
153 REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
154 REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
155 }
156
rtc_vddsdio_get_config(void)157 rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
158 {
159 rtc_vddsdio_config_t result;
160 uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG);
161 result.drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) >> RTC_CNTL_DREFH_SDIO_S;
162 result.drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) >> RTC_CNTL_DREFM_SDIO_S;
163 result.drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) >> RTC_CNTL_DREFL_SDIO_S;
164 if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) {
165 // Get configuration from RTC
166 result.force = 1;
167 result.enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) >> RTC_CNTL_XPD_SDIO_REG_S;
168 result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
169 return result;
170 } else {
171 result.force = 0;
172 }
173
174 // Otherwise, VDD_SDIO is controlled by bootstrapping pin
175 uint32_t strap_reg = REG_READ(GPIO_STRAP_REG);
176 result.force = 0;
177 result.tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V : RTC_VDDSDIO_TIEH_3_3V;
178 result.enable = 1;
179 return result;
180 }
181
rtc_vddsdio_set_config(rtc_vddsdio_config_t config)182 void rtc_vddsdio_set_config(rtc_vddsdio_config_t config)
183 {
184 uint32_t val = 0;
185 val |= (config.force << RTC_CNTL_SDIO_FORCE_S);
186 val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S);
187 val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S);
188 val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S);
189 val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S);
190 val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S);
191 val |= RTC_CNTL_SDIO_PD_EN;
192 REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val);
193 }
194
set_ocode_by_efuse(int calib_version)195 static void set_ocode_by_efuse(int calib_version)
196 {
197 assert(calib_version == 1);
198 // use efuse ocode.
199 uint32_t ocode;
200 esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, 8);
201 assert(err == ESP_OK);
202 (void) err;
203 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode);
204 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1);
205 }
206
calibrate_ocode(void)207 static void calibrate_ocode(void)
208 {
209 /*
210 Bandgap output voltage is not precise when calibrate o-code by hardware sometimes, so need software o-code calibration (must turn off PLL).
211 Method:
212 1. read current cpu config, save in old_config;
213 2. switch cpu to xtal because PLL will be closed when o-code calibration;
214 3. begin o-code calibration;
215 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout;
216 5. set cpu to old-config.
217 */
218 rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
219 rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL;
220 rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256;
221 rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
222 if (slow_clk_freq == (rtc_slow_freq_x32k)) {
223 cal_clk = RTC_CAL_32K_XTAL;
224 } else if (slow_clk_freq == rtc_slow_freq_8MD256) {
225 cal_clk = RTC_CAL_8MD256;
226 }
227
228 uint64_t max_delay_time_us = 10000;
229 uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100);
230 uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period);
231 uint64_t cycle0 = rtc_time_get();
232 uint64_t timeout_cycle = cycle0 + max_delay_cycle;
233 uint64_t cycle1 = 0;
234
235 rtc_cpu_freq_config_t old_config;
236 rtc_clk_cpu_freq_get_config(&old_config);
237 rtc_clk_cpu_freq_set_xtal();
238
239 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0);
240 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1);
241 bool odone_flag = 0;
242 bool bg_odone_flag = 0;
243 while (1) {
244 odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG);
245 bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG);
246 cycle1 = rtc_time_get();
247 if (odone_flag && bg_odone_flag) {
248 break;
249 }
250 if (cycle1 >= timeout_cycle) {
251 SOC_LOGW(TAG, "o_code calibration fail\n");
252 break;
253 }
254 }
255 rtc_clk_cpu_freq_set_config(&old_config);
256 }
257
get_dig_dbias_by_efuse(uint8_t chip_version)258 static uint32_t get_dig_dbias_by_efuse(uint8_t chip_version)
259 {
260 assert(chip_version >= 3);
261 uint32_t dig_dbias = 28;
262 esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, 5);
263 if (err != ESP_OK) {
264 dig_dbias = 28;
265 SOC_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias);
266 }
267 return dig_dbias;
268 }
269
get_rtc_dbias_by_efuse(uint8_t chip_version,uint32_t dig_dbias)270 uint32_t get_rtc_dbias_by_efuse(uint8_t chip_version, uint32_t dig_dbias)
271 {
272 assert(chip_version >= 3);
273 uint32_t rtc_dbias = 0;
274 signed int k_rtc_ldo = 0, k_dig_ldo = 0, v_rtc_bias20 = 0, v_dig_bias20 = 0;
275 esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_RTC_LDO, &k_rtc_ldo, 7);
276 esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, 7);
277 esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_V_RTC_DBIAS20, &v_rtc_bias20, 8);
278 esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, 8);
279 if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK)) {
280 k_rtc_ldo = 0;
281 k_dig_ldo = 0;
282 v_rtc_bias20 = 0;
283 v_dig_bias20 = 0;
284 SOC_LOGW(TAG, "efuse read fail, k_rtc_ldo: %d, k_dig_ldo: %d, v_rtc_bias20: %d, v_dig_bias20: %d\n", k_rtc_ldo, k_dig_ldo, v_rtc_bias20, v_dig_bias20);
285 }
286
287 k_rtc_ldo = ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): k_rtc_ldo;
288 k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo;
289 v_rtc_bias20 = ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20;
290 v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20;
291
292 uint32_t v_rtc_dbias20_real_mul10000 = V_RTC_MID_MUL10000 + v_rtc_bias20 * 10000 / 500;
293 uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500;
294 signed int k_rtc_ldo_real_mul10000 = K_RTC_MID_MUL10000 + k_rtc_ldo;
295 signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo;
296 uint32_t v_dig_nearest_1v15_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20);
297 uint32_t v_rtc_nearest_1v15_mul10000 = 0;
298 for (rtc_dbias = 15; rtc_dbias < 31; rtc_dbias++) {
299 v_rtc_nearest_1v15_mul10000 = v_rtc_dbias20_real_mul10000 + k_rtc_ldo_real_mul10000 * (rtc_dbias - 20);
300 if (v_rtc_nearest_1v15_mul10000 >= v_dig_nearest_1v15_mul10000 - 250)
301 break;
302 }
303 return rtc_dbias;
304 }
305
set_rtc_dig_dbias()306 static void set_rtc_dig_dbias()
307 {
308 /*
309 1. a reasonable dig_dbias which by scaning pvt to make 160 CPU run successful stored in efuse;
310 2. also we store some value in efuse, include:
311 k_rtc_ldo (slope of rtc voltage & rtc_dbias);
312 k_dig_ldo (slope of digital voltage & digital_dbias);
313 v_rtc_bias20 (rtc voltage when rtc dbais is 20);
314 v_dig_bias20 (digital voltage when digital dbais is 20).
315 3. a reasonable rtc_dbias can be calculated by a certion formula.
316 */
317 uint32_t rtc_dbias = 28, dig_dbias = 28;
318 uint8_t chip_version = esp_efuse_get_chip_ver();
319 if (chip_version >= 3) {
320 dig_dbias = get_dig_dbias_by_efuse(chip_version);
321 if (dig_dbias != 0) {
322 if (dig_dbias + 4 > 28) {
323 dig_dbias = 28;
324 } else {
325 dig_dbias += 4;
326 }
327 rtc_dbias = get_rtc_dbias_by_efuse(chip_version, dig_dbias); // already burn dig_dbias in efuse
328 } else {
329 dig_dbias = 28;
330 SOC_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value in chip version: 0%d\n", chip_version);
331 }
332 }
333 else {
334 SOC_LOGD(TAG, "chip_version is less than 3, not burn core voltage in efuse\n");
335 }
336 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, rtc_dbias);
337 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dig_dbias);
338 }
339
