1 /*
2 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: CC0-1.0
5 */
6
7 /**
8 * I2S test environment UT_T1_I2S:
9 * We use internal signals instead of external wiring, but please keep the following IO connections, or connect nothing to prevent the signal from being disturbed.
10 * connect GPIO15 and GPIO19, GPIO25(ESP32)/GPIO17(ESP32-S2) and GPIO26, GPIO21 and GPIO22(ESP32)/GPIO20(ESP32-S2)
11 * Please do not connect GPIO32(ESP32) any pull-up resistors externally, it will be used to test i2s adc function.
12 */
13
14 #include <stdio.h>
15 #include <string.h>
16 #include "freertos/FreeRTOS.h"
17 #include "freertos/task.h"
18 #include "freertos/queue.h"
19 #include "driver/i2s.h"
20 #include "driver/gpio.h"
21 #include "hal/gpio_hal.h"
22 #include "unity.h"
23 #include "math.h"
24 #include "esp_rom_gpio.h"
25
26 #define SAMPLE_RATE (36000)
27 #define SAMPLE_BITS (16)
28
29 #if CONFIG_IDF_TARGET_ESP32
30 #define MASTER_BCK_IO 15
31 #define MASTER_WS_IO 25
32 #define SLAVE_BCK_IO 19
33 #define SLAVE_WS_IO 26
34 #define DATA_IN_IO 21
35 #define DATA_OUT_IO 22
36 #define ADC1_CHANNEL_4_IO 32
37 #define I2S0_DATA_OUT_IDX I2S0O_DATA_OUT23_IDX
38 #define I2S0_DATA_IN_IDX I2S0I_DATA_IN15_IDX
39 #define I2S1_DATA_OUT_IDX I2S1O_DATA_OUT23_IDX
40 #define I2S1_DATA_IN_IDX I2S1I_DATA_IN15_IDX
41 #elif CONFIG_IDF_TARGET_ESP32S2
42 #define MASTER_BCK_IO 15
43 #define MASTER_WS_IO 28
44 #define SLAVE_BCK_IO 19
45 #define SLAVE_WS_IO 26
46 #define DATA_IN_IO 21
47 #define DATA_OUT_IO 20
48 #define I2S0_DATA_OUT_IDX I2S0O_DATA_OUT23_IDX
49 #define I2S0_DATA_IN_IDX I2S0I_DATA_IN15_IDX
50 #elif CONFIG_IDF_TARGET_ESP32C3
51 // TODO: change pins
52 #define MASTER_BCK_IO 4
53 #define MASTER_WS_IO 5
54 #define SLAVE_BCK_IO 14
55 #define SLAVE_WS_IO 15
56 #define DATA_IN_IO 19
57 #define DATA_OUT_IO 18
58 #define I2S0_DATA_OUT_IDX I2SO_SD_OUT_IDX
59 #define I2S0_DATA_IN_IDX I2SI_SD_IN_IDX
60 #elif CONFIG_IDF_TARGET_ESP32S3
61 #define MASTER_BCK_IO 4
62 #define MASTER_WS_IO 5
63 #define SLAVE_BCK_IO 14
64 #define SLAVE_WS_IO 15
65 #define DATA_IN_IO 19
66 #define DATA_OUT_IO 18
67 #define I2S0_DATA_OUT_IDX I2S0O_SD_OUT_IDX
68 #define I2S0_DATA_IN_IDX I2S0I_SD_IN_IDX
69 #define I2S1_DATA_OUT_IDX I2S1O_SD_OUT_IDX
70 #define I2S1_DATA_IN_IDX I2S1I_SD_IN_IDX
71 #endif
72
73 #define PERCENT_DIFF 0.0001
74
75 #define I2S_TEST_MODE_SLAVE_TO_MAXTER 0
76 #define I2S_TEST_MODE_MASTER_TO_SLAVE 1
77 #define I2S_TEST_MODE_LOOPBACK 2
78
79 // mode: 0, master rx, slave tx. mode: 1, master tx, slave rx. mode: 2, master tx rx loopback
80 // Since ESP32-S2 has only one I2S, only loop back test can be tested.
i2s_test_io_config(int mode)81 static void i2s_test_io_config(int mode)
82 {
83 // Connect internal signals using IO matrix.
84 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[MASTER_BCK_IO], PIN_FUNC_GPIO);
85 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[MASTER_WS_IO], PIN_FUNC_GPIO);
86 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[DATA_OUT_IO], PIN_FUNC_GPIO);
87
88 gpio_set_direction(MASTER_BCK_IO, GPIO_MODE_INPUT_OUTPUT);
89 gpio_set_direction(MASTER_WS_IO, GPIO_MODE_INPUT_OUTPUT);
90 gpio_set_direction(DATA_OUT_IO, GPIO_MODE_INPUT_OUTPUT);
91
92 switch (mode) {
93 #if SOC_I2S_NUM > 1
94 case I2S_TEST_MODE_SLAVE_TO_MAXTER: {
95 esp_rom_gpio_connect_out_signal(MASTER_BCK_IO, I2S0I_BCK_OUT_IDX, 0, 0);
96 esp_rom_gpio_connect_in_signal(MASTER_BCK_IO, I2S1O_BCK_IN_IDX, 0);
97
98 esp_rom_gpio_connect_out_signal(MASTER_WS_IO, I2S0I_WS_OUT_IDX, 0, 0);
99 esp_rom_gpio_connect_in_signal(MASTER_WS_IO, I2S1O_WS_IN_IDX, 0);
100
101 esp_rom_gpio_connect_out_signal(DATA_OUT_IO, I2S1_DATA_OUT_IDX, 0, 0);
102 esp_rom_gpio_connect_in_signal(DATA_OUT_IO, I2S0_DATA_IN_IDX, 0);
103 }
104 break;
105
106 case I2S_TEST_MODE_MASTER_TO_SLAVE: {
107 esp_rom_gpio_connect_out_signal(MASTER_BCK_IO, I2S0O_BCK_OUT_IDX, 0, 0);
108 esp_rom_gpio_connect_in_signal(MASTER_BCK_IO, I2S1I_BCK_IN_IDX, 0);
109
110 esp_rom_gpio_connect_out_signal(MASTER_WS_IO, I2S0O_WS_OUT_IDX, 0, 0);
111 esp_rom_gpio_connect_in_signal(MASTER_WS_IO, I2S1I_WS_IN_IDX, 0);
112
113 esp_rom_gpio_connect_out_signal(DATA_OUT_IO, I2S0_DATA_OUT_IDX, 0, 0);
114 esp_rom_gpio_connect_in_signal(DATA_OUT_IO, I2S1_DATA_IN_IDX, 0);
115 }
116 break;
117 #endif
118 case I2S_TEST_MODE_LOOPBACK: {
119 esp_rom_gpio_connect_out_signal(DATA_OUT_IO, I2S0_DATA_OUT_IDX, 0, 0);
120 esp_rom_gpio_connect_in_signal(DATA_OUT_IO, I2S0_DATA_IN_IDX, 0);
121 }
122 break;
123
124 default: {
125 TEST_FAIL_MESSAGE("error: mode not supported");
126 }
127 break;
128 }
129 }
130
131
132 /**
133 * i2s initialize test
134 * 1. i2s_driver_install
135 * 2. i2s_set_pin
136 */
137 TEST_CASE("I2S basic driver install, uninstall, set pin test", "[i2s]")
138 {
139 // dac, adc i2s
140 i2s_config_t i2s_config = {
141 .mode = I2S_MODE_MASTER | I2S_MODE_TX,
142 .sample_rate = SAMPLE_RATE,
143 .bits_per_sample = SAMPLE_BITS,
144 .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
145 .communication_format = I2S_COMM_FORMAT_STAND_I2S,
146 .dma_buf_count = 6,
147 .dma_buf_len = 60,
148 .use_apll = 0,
149 .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
150 #if SOC_I2S_SUPPORTS_TDM
151 .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
152 .total_chan = 2,
153 .left_align = false,
154 .big_edin = false,
155 .bit_order_msb = false,
156 .skip_msk = false
157 #endif
158 };
159
160 // normal i2s
161 i2s_pin_config_t pin_config = {
162 .mck_io_num = -1,
163 .bck_io_num = MASTER_BCK_IO,
164 .ws_io_num = MASTER_WS_IO,
165 .data_out_num = DATA_OUT_IO,
166 .data_in_num = -1
167 };
168 QueueHandle_t evt_que;
169 TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 16, &evt_que));
170 TEST_ASSERT(evt_que);
171 TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
172 TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
173
174 //error param test
175 TEST_ASSERT(i2s_driver_install(I2S_NUM_MAX, &i2s_config, 0, NULL) == ESP_ERR_INVALID_ARG);
176 TEST_ASSERT(i2s_driver_install(I2S_NUM_0, NULL, 0, NULL) == ESP_ERR_INVALID_ARG);
177 i2s_config.dma_buf_count = 1;
178 TEST_ASSERT(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL) == ESP_ERR_INVALID_ARG);
179 i2s_config.dma_buf_count = 129;
180 TEST_ASSERT(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL) == ESP_ERR_INVALID_ARG);
181 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, i2s_driver_uninstall(I2S_NUM_0));
182 }
183
184 TEST_CASE("I2S Loopback test(master tx and rx)", "[i2s]")
185 {
186 // master driver installed and send data
187 i2s_config_t master_i2s_config = {
188 .mode = I2S_MODE_MASTER | I2S_MODE_TX | I2S_MODE_RX,
189 .sample_rate = SAMPLE_RATE,
190 .bits_per_sample = SAMPLE_BITS,
191 .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
192 .communication_format = I2S_COMM_FORMAT_STAND_I2S,
193 .dma_buf_count = 6,
194 .dma_buf_len = 100,
195 .use_apll = 0,
196 .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
197 #if SOC_I2S_SUPPORTS_TDM
198 .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
199 .total_chan = 2,
200 .left_align = false,
201 .big_edin = false,
202 .bit_order_msb = false,
203 .skip_msk = false
204 #endif
205 };
206 i2s_pin_config_t master_pin_config = {
207 .mck_io_num = -1,
208 .bck_io_num = MASTER_BCK_IO,
209 .ws_io_num = MASTER_WS_IO,
210 .data_out_num = DATA_OUT_IO,
211 .data_in_num = DATA_IN_IO
212 };
213 TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
214 TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
215 i2s_test_io_config(I2S_TEST_MODE_LOOPBACK);
216 printf("\r\nheap size: %d\n", esp_get_free_heap_size());
217
218 uint8_t *data_wr = (uint8_t *)malloc(sizeof(uint8_t) * 400);
219 size_t i2s_bytes_write = 0;
220 size_t bytes_read = 0;
221 int length = 0;
222 uint8_t *i2s_read_buff = (uint8_t *)malloc(sizeof(uint8_t) * 10000);
223
224 for (int i = 0; i < 100; i++) {
225 data_wr[i] = i + 1;
226 }
227 int flag = 0; // break loop flag
228 int end_position = 0;
229 // write data to slave
230 i2s_write(I2S_NUM_0, data_wr, sizeof(uint8_t) * 400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
231 while (!flag) {
232 if (length >= 10000 - 500) {
233 break;
234 }
235 i2s_read(I2S_NUM_0, i2s_read_buff + length, sizeof(uint8_t) * 500, &bytes_read, 1000 / portMAX_DELAY);
236 if (bytes_read > 0) {
237 for (int i = length; i < length + bytes_read; i++) {
238 if (i2s_read_buff[i] == 100) {
239 flag = 1;
240 end_position = i;
241 break;
242 }
243 }
244 }
245 length = length + bytes_read;
246 }
247 // test the read data right or not
248 for (int i = end_position - 99; i <= end_position; i++) {
249 TEST_ASSERT_EQUAL_UINT8((i - end_position + 100), *(i2s_read_buff + i));
250 }
251 free(data_wr);
252 free(i2s_read_buff);
253 i2s_driver_uninstall(I2S_NUM_0);
254 }
255
256 #if SOC_I2S_SUPPORTS_TDM
257 TEST_CASE("I2S TDM Loopback test(master tx and rx)", "[i2s]")
258 {
259 // master driver installed and send data
260 i2s_config_t master_i2s_config = {
261 .mode = I2S_MODE_MASTER | I2S_MODE_TX | I2S_MODE_RX,
262 .sample_rate = SAMPLE_RATE,
263 .bits_per_sample = SAMPLE_BITS,
264 .channel_format = I2S_CHANNEL_FMT_MULTIPLE,
265 .communication_format = I2S_COMM_FORMAT_STAND_I2S,
266 .total_chan = 4,
267 .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1 | I2S_TDM_ACTIVE_CH2 | I2S_TDM_ACTIVE_CH3,
268 .dma_buf_count = 6,
269 .dma_buf_len = 100,
270 .use_apll = 0,
271 .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
272 };
273 i2s_pin_config_t master_pin_config = {
274 .mck_io_num = -1,
275 .bck_io_num = MASTER_BCK_IO,
276 .ws_io_num = MASTER_WS_IO,
277 .data_out_num = DATA_OUT_IO,
278 .data_in_num = DATA_IN_IO
279 };
280 TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
281 TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
282 i2s_test_io_config(I2S_TEST_MODE_LOOPBACK);
283 printf("\r\nheap size: %d\n", esp_get_free_heap_size());
284
285 uint8_t *data_wr = (uint8_t *)malloc(sizeof(uint8_t) * 400);
286 size_t i2s_bytes_write = 0;
287 size_t bytes_read = 0;
288 int length = 0;
289 uint8_t *i2s_read_buff = (uint8_t *)malloc(sizeof(uint8_t) * 10000);
290
291 for (int i = 0; i < 100; i++) {
292 data_wr[i] = i + 1;
293 }
294 int flag = 0; // break loop flag
295 int end_position = 0;
296 // write data to slave
297 i2s_write(I2S_NUM_0, data_wr, sizeof(uint8_t) * 400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
298 while (!flag) {
299 if (length >= 10000 - 500) {
300 break;
301 }
302 i2s_read(I2S_NUM_0, i2s_read_buff + length, sizeof(uint8_t) * 500, &bytes_read, 1000 / portMAX_DELAY);
303 if (bytes_read > 0) {
304 for (int i = length; i < length + bytes_read; i++) {
305 if (i2s_read_buff[i] == 100) {
306 flag = 1;
307 end_position = i;
308 break;
309 }
310 }
311 }
312 length = length + bytes_read;
313 }
314 // test the read data right or not
315 for (int i = end_position - 99; i <= end_position; i++) {
316 TEST_ASSERT_EQUAL_UINT8((i - end_position + 100), *(i2s_read_buff + i));
317 }
318 free(data_wr);
319 free(i2s_read_buff);
320 i2s_driver_uninstall(I2S_NUM_0);
321 }
322 #endif
323
324 #if SOC_I2S_NUM > 1
325 /* ESP32S2 and ESP32C3 has only single I2S port and hence following test cases are not applicable */
326 TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s]")
327 {
328 // master driver installed and send data
329 i2s_config_t master_i2s_config = {
330 .mode = I2S_MODE_MASTER | I2S_MODE_TX,
331 .sample_rate = SAMPLE_RATE,
332 .bits_per_sample = SAMPLE_BITS,
333 .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
334 .communication_format = I2S_COMM_FORMAT_STAND_I2S,
335 .dma_buf_count = 6,
336 .dma_buf_len = 100,
337 .use_apll = 0,
338 .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
339 #if SOC_I2S_SUPPORTS_TDM
340 .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
341 .total_chan = 2,
342 .left_align = false,
343 .big_edin = false,
344 .bit_order_msb = false,
345 .skip_msk = false
346 #endif
347 };
348 i2s_pin_config_t master_pin_config = {
349 .mck_io_num = -1,
350 .bck_io_num = MASTER_BCK_IO,
351 .ws_io_num = MASTER_WS_IO,
352 .data_out_num = DATA_OUT_IO,
353 .data_in_num = -1
354 };
355 TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
356 TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
357 i2s_test_io_config(I2S_TEST_MODE_MASTER_TO_SLAVE);
358 printf("\r\nheap size: %d\n", esp_get_free_heap_size());
359
360 i2s_config_t slave_i2s_config = {
361 .mode = I2S_MODE_SLAVE | I2S_MODE_RX,
362 .sample_rate = SAMPLE_RATE,
363 .bits_per_sample = SAMPLE_BITS,
364 .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
365 .communication_format = I2S_COMM_FORMAT_STAND_I2S,
366 .dma_buf_count = 6,
367 .dma_buf_len = 100,
368 .use_apll = 0,
369 .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
370 #if SOC_I2S_SUPPORTS_TDM
371 .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
372 .total_chan = 2,
373 .left_align = false,
374 .big_edin = false,
375 .bit_order_msb = false,
376 .skip_msk = false
377 #endif
378 };
379 i2s_pin_config_t slave_pin_config = {
380 .mck_io_num = -1,
381 .bck_io_num = SLAVE_BCK_IO,
382 .ws_io_num = SLAVE_WS_IO,
383 .data_out_num = -1,
384 .data_in_num = DATA_IN_IO,
385 };
386 // slave driver installed and receive data
387 TEST_ESP_OK(i2s_driver_install(I2S_NUM_1, &slave_i2s_config, 0, NULL));
388 TEST_ESP_OK(i2s_set_pin(I2S_NUM_1, &slave_pin_config));
389 i2s_test_io_config(I2S_TEST_MODE_MASTER_TO_SLAVE);
390 printf("\r\nheap size: %d\n", esp_get_free_heap_size());
391
392 uint8_t *data_wr = (uint8_t *)malloc(sizeof(uint8_t) * 400);
393 size_t i2s_bytes_write = 0;
394 size_t bytes_read = 0;
395 int length = 0;
396 uint8_t *i2s_read_buff = (uint8_t *)malloc(sizeof(uint8_t) * 10000);
397
398 for (int i = 0; i < 100; i++) {
399 data_wr[i] = i + 1;
400 }
401 int flag = 0; // break loop flag
402 int end_position = 0;
403 // write data to slave
404 i2s_write(I2S_NUM_0, data_wr, sizeof(uint8_t) * 400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
405 printf("write data size: %d\n", i2s_bytes_write);
406 while (!flag) {
407 i2s_read(I2S_NUM_1, i2s_read_buff + length, sizeof(uint8_t) * 500, &bytes_read, 1000 / portTICK_PERIOD_MS);
408 if (bytes_read > 0) {
409 printf("read data size: %d\n", bytes_read);
410 for (int i = length; i < length + bytes_read; i++) {
411 if (i2s_read_buff[i] == 100) {
412 flag = 1;
413 end_position = i;
414 break;
415 }
416 }
417 }
418 length = length + bytes_read;
419 }
420 // test the readed data right or not
421 for (int i = end_position - 99; i <= end_position; i++) {
422 TEST_ASSERT_EQUAL_UINT8((i - end_position + 100), *(i2s_read_buff + i));
423 }
424 free(data_wr);
425 free(i2s_read_buff);
426 i2s_driver_uninstall(I2S_NUM_0);
427 i2s_driver_uninstall(I2S_NUM_1);
428 }
429
430 TEST_CASE("I2S write and read test(master rx and slave tx)", "[i2s]")
431 {
432 // master driver installed and send data
433 i2s_config_t master_i2s_config = {
434 .mode = I2S_MODE_MASTER | I2S_MODE_RX,
435 .sample_rate = SAMPLE_RATE,
436 .bits_per_sample = SAMPLE_BITS,
437 .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
438 .communication_format = I2S_COMM_FORMAT_STAND_I2S,
439 .dma_buf_count = 6,
440 .dma_buf_len = 100,
441 .use_apll = 1,
442 .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
443 #if SOC_I2S_SUPPORTS_TDM
444 .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
445 .total_chan = 2,
446 .left_align = false,
447 .big_edin = false,
448 .bit_order_msb = false,
449 .skip_msk = false
450 #endif
451 };
452 i2s_pin_config_t master_pin_config = {
453 .mck_io_num = -1,
454 .bck_io_num = MASTER_BCK_IO,
455 .ws_io_num = MASTER_WS_IO,
456 .data_out_num = -1,
457 .data_in_num = DATA_IN_IO,
458 };
459 TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
460 TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
461 i2s_test_io_config(I2S_TEST_MODE_SLAVE_TO_MAXTER);
462 printf("\r\nheap size: %d\n", esp_get_free_heap_size());
463
464 i2s_config_t slave_i2s_config = {
465 .mode = I2S_MODE_SLAVE | I2S_MODE_TX, // Only RX
466 .sample_rate = SAMPLE_RATE,
467 .bits_per_sample = SAMPLE_BITS,
468 .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, //2-channels
469 .communication_format = I2S_COMM_FORMAT_STAND_I2S,
470 .dma_buf_count = 6,
471 .dma_buf_len = 100,
472 .use_apll = 1,
473 .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
474 #if SOC_I2S_SUPPORTS_TDM
475 .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
476 .total_chan = 2,
477 .left_align = false,
478 .big_edin = false,
479 .bit_order_msb = false,
480 .skip_msk = false
481 #endif
482 };
483 i2s_pin_config_t slave_pin_config = {
484 .mck_io_num = -1,
485 .bck_io_num = SLAVE_BCK_IO,
486 .ws_io_num = SLAVE_WS_IO,
487 .data_out_num = DATA_OUT_IO,
488 .data_in_num = -1
489 };
490 // slave driver installed and receive data
491 TEST_ESP_OK(i2s_driver_install(I2S_NUM_1, &slave_i2s_config, 0, NULL));
492 TEST_ESP_OK(i2s_set_pin(I2S_NUM_1, &slave_pin_config));
493 i2s_test_io_config(I2S_TEST_MODE_SLAVE_TO_MAXTER);
494 printf("\r\nheap size: %d\n", esp_get_free_heap_size());
495
496 uint8_t *data_wr = (uint8_t *)malloc(sizeof(uint8_t) * 400);
497 size_t i2s_bytes_write = 0;
498 size_t bytes_read = 0;
499 int length = 0;
500 uint8_t *i2s_read_buff = (uint8_t *)malloc(sizeof(uint8_t) * 10000);
501
502 for (int i = 0; i < 100; i++) {
503 data_wr[i] = i + 1;
504 }
505 // slave write data to master
506 i2s_write(I2S_NUM_1, data_wr, sizeof(uint8_t) * 400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
507 printf("write data size: %d\n", i2s_bytes_write);
508 int flag = 0; // break loop flag
509 volatile int end_position = 0;
510 // write data to slave
511 while (!flag) {
512 TEST_ESP_OK(i2s_read(I2S_NUM_0, i2s_read_buff + length, 10000 - length, &bytes_read, 1000 / portTICK_PERIOD_MS));
513 if (bytes_read > 0) {
514 printf("read data size: %d\n", bytes_read);
515 for (int i = length; i < length + bytes_read; i++) {
516 if (i2s_read_buff[i] == 100) {
517 flag = 1;
518 end_position = i;
519 break;
520 }
521 }
522 }
523 length = length + bytes_read;
524 }
525 // test the readed data right or not
526 for (int i = end_position - 99; i <= end_position; i++) {
527 TEST_ASSERT_EQUAL_UINT8((i - end_position + 100), *(i2s_read_buff + i));
528 }
529 free(data_wr);
530 free(i2s_read_buff);
531 i2s_driver_uninstall(I2S_NUM_0);
532 i2s_driver_uninstall(I2S_NUM_1);
533 }
534 #endif
535
536 TEST_CASE("I2S memory leaking test", "[i2s]")
537 {
538 i2s_config_t master_i2s_config = {
539 .mode = I2S_MODE_MASTER | I2S_MODE_RX,
540 .sample_rate = SAMPLE_RATE,
541 .bits_per_sample = SAMPLE_BITS,
542 .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
543 .communication_format = I2S_COMM_FORMAT_STAND_I2S,
544 .dma_buf_count = 6,
545 .dma_buf_len = 100,
546 .use_apll = 0,
547 .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
548 #if SOC_I2S_SUPPORTS_TDM
549 .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
550 .total_chan = 2,
551 .left_align = false,
552 .big_edin = false,
553 .bit_order_msb = false,
554 .skip_msk = false
555 #endif
556 };
557 i2s_pin_config_t master_pin_config = {
558 .mck_io_num = -1,
559 .bck_io_num = MASTER_BCK_IO,
560 .ws_io_num = MASTER_WS_IO,
561 .data_out_num = -1,
562 .data_in_num = DATA_IN_IO
563 };
564
565 TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
566 TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
567 i2s_driver_uninstall(I2S_NUM_0);
568 int initial_size = esp_get_free_heap_size();
569
570 for (int i = 0; i < 100; i++) {
571 TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
572 TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
573 i2s_driver_uninstall(I2S_NUM_0);
574 TEST_ASSERT(initial_size == esp_get_free_heap_size());
575 }
576 vTaskDelay(100 / portTICK_PERIOD_MS);
577 TEST_ASSERT(initial_size == esp_get_free_heap_size());
578 }
579
580 #if SOC_I2S_SUPPORTS_APLL
581 /*
582 * The I2S APLL clock variation test used to test the difference between the different sample rates, different bits per sample
583 * and the APLL clock generate for it. The TEST_CASE passes PERCENT_DIFF variation from the provided sample rate in APLL generated clock
584 * The percentage difference calculated as (mod((obtained clock rate - desired clock rate)/(desired clock rate))) * 100.
585 */
586 TEST_CASE("I2S APLL clock variation test", "[i2s]")
587 {
588 i2s_pin_config_t pin_config = {
589 .mck_io_num = -1,
590 .bck_io_num = MASTER_BCK_IO,
591 .ws_io_num = MASTER_WS_IO,
592 .data_out_num = DATA_OUT_IO,
593 .data_in_num = -1
594 };
595
596 i2s_config_t i2s_config = {
597 .mode = I2S_MODE_MASTER | I2S_MODE_TX,
598 .sample_rate = SAMPLE_RATE,
599 .bits_per_sample = SAMPLE_BITS,
600 .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
601 .communication_format = I2S_COMM_FORMAT_STAND_I2S,
602 .dma_buf_count = 6,
603 .dma_buf_len = 60,
604 .use_apll = true,
605 .intr_alloc_flags = 0,
606 #if SOC_I2S_SUPPORTS_TDM
607 .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
608 .total_chan = 2,
609 .left_align = false,
610 .big_edin = false,
611 .bit_order_msb = false,
612 .skip_msk = false
613 #endif
614 };
615
616 TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
617 TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
618 TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
619 int initial_size = esp_get_free_heap_size();
620
621 uint32_t sample_rate_arr[8] = { 10675, 11025, 16000, 22050, 32000, 44100, 48000, 96000 };
622 int bits_per_sample_arr[3] = { 16, 24, 32 };
623
624 for (int i = 0; i < (sizeof(sample_rate_arr) / sizeof(sample_rate_arr[0])); i++) {
625 for (int j = 0; j < (sizeof(bits_per_sample_arr) / sizeof(bits_per_sample_arr[0])); j++) {
626 i2s_config.sample_rate = sample_rate_arr[i];
627 i2s_config.bits_per_sample = bits_per_sample_arr[j];
628
629 TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
630 TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
631 TEST_ASSERT((fabs((i2s_get_clk(I2S_NUM_0) - sample_rate_arr[i])) / (sample_rate_arr[i])) * 100 < PERCENT_DIFF);
632 TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
633 TEST_ASSERT(initial_size == esp_get_free_heap_size());
634 }
635 }
636
637 vTaskDelay(100 / portTICK_PERIOD_MS);
638 TEST_ASSERT(initial_size == esp_get_free_heap_size());
639 }
640 #endif
641
642 #if SOC_I2S_SUPPORTS_ADC
643 /* Only ESP32 need I2S adc/dac test */
644 TEST_CASE("I2S adc test", "[i2s]")
645 {
646 // init I2S ADC
647 i2s_config_t i2s_config = {
648 .mode = I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_ADC_BUILT_IN,
649 .sample_rate = SAMPLE_RATE,
650 .bits_per_sample = SAMPLE_BITS,
651 .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
652 .intr_alloc_flags = 0,
653 .dma_buf_count = 2,
654 .dma_buf_len = 1024,
655 .use_apll = 0,
656 };
657 // install and start I2S driver
658 i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL);
659 // init ADC pad
660 i2s_set_adc_mode(ADC_UNIT_1, ADC1_CHANNEL_4);
661 // enable adc sampling, ADC_WIDTH_BIT_12, ADC_ATTEN_DB_11 hard-coded in adc_i2s_mode_init
662 i2s_adc_enable(I2S_NUM_0);
663 // init read buffer
664 uint16_t *i2sReadBuffer = (uint16_t *)calloc(1024, sizeof(uint16_t));
665 size_t bytesRead;
666
667 for (int loop = 0; loop < 10; loop++) {
668 for (int level = 0; level <= 1; level++) {
669 if (level == 0) {
670 gpio_set_pull_mode(ADC1_CHANNEL_4_IO, GPIO_PULLDOWN_ONLY);
671 } else {
672 gpio_set_pull_mode(ADC1_CHANNEL_4_IO, GPIO_PULLUP_ONLY);
673 }
674 vTaskDelay(200 / portTICK_RATE_MS);
675 // read data from adc, will block until buffer is full
676 i2s_read(I2S_NUM_0, (void *)i2sReadBuffer, 1024 * sizeof(uint16_t), &bytesRead, portMAX_DELAY);
677
678 // calc average
679 int64_t adcSumValue = 0;
680 for (size_t i = 0; i < 1024; i++) {
681 adcSumValue += i2sReadBuffer[i] & 0xfff;
682 }
683 int adcAvgValue = adcSumValue / 1024;
684 printf("adc average val: %d\n", adcAvgValue);
685
686 if (level == 0) {
687 if (adcAvgValue > 100) {
688 i2s_adc_disable(I2S_NUM_0);
689 free(i2sReadBuffer);
690 i2s_driver_uninstall(I2S_NUM_0);
691 TEST_ASSERT_LESS_THAN(100, adcAvgValue);
692 }
693 } else {
694 if (adcAvgValue < 4000) {
695 i2s_adc_disable(I2S_NUM_0);
696 free(i2sReadBuffer);
697 i2s_driver_uninstall(I2S_NUM_0);
698 TEST_ASSERT_GREATER_THAN(4000, adcAvgValue);
699 }
700 }
701 }
702 }
703
704 i2s_adc_disable(I2S_NUM_0);
705 free(i2sReadBuffer);
706 i2s_driver_uninstall(I2S_NUM_0);
707 }
708 #endif
709
710 #if SOC_I2S_SUPPORTS_DAC
711 TEST_CASE("I2S dac test", "[i2s]")
712 {
713 // dac, adc i2s
714 i2s_config_t i2s_config = {
715 .mode = I2S_MODE_MASTER | I2S_MODE_TX,
716 .sample_rate = SAMPLE_RATE,
717 .bits_per_sample = SAMPLE_BITS,
718 .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
719 .communication_format = I2S_COMM_FORMAT_STAND_I2S,
720 .dma_buf_count = 6,
721 .dma_buf_len = 60,
722 .use_apll = 0,
723 .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
724 };
725
726 //install and start i2s driver
727 TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
728 //for internal DAC, this will enable both of the internal channels
729 TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, NULL));
730 //stop & destroy i2s driver
731 TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
732 }
733 #endif
734
