1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "sdkconfig.h"
8 #include "esp_flash.h"
9 #include "memspi_host_driver.h"
10 #include "esp_flash_spi_init.h"
11 #include "driver/gpio.h"
12 #include "esp_rom_gpio.h"
13 #include "esp_rom_efuse.h"
14 #include "esp_log.h"
15 #include "esp_heap_caps.h"
16 #include "hal/spi_types.h"
17 #include "driver/spi_common_internal.h"
18 #include "hal/spi_flash_hal.h"
19 #include "hal/gpio_hal.h"
20 #include "esp_flash_internal.h"
21 #include "esp_rom_gpio.h"
22 #include "esp_private/spi_flash_os.h"
23 #if CONFIG_IDF_TARGET_ESP32
24 #include "esp32/rom/spi_flash.h"
25 #elif CONFIG_IDF_TARGET_ESP32S2
26 #include "esp32s2/rom/spi_flash.h"
27 #elif CONFIG_IDF_TARGET_ESP32S3
28 #include "esp32s3/rom/spi_flash.h"
29 #elif CONFIG_IDF_TARGET_ESP32C3
30 #include "esp32c3/rom/spi_flash.h"
31 #elif CONFIG_IDF_TARGET_ESP32H2
32 #include "esp32h2/rom/spi_flash.h"
33 #endif
34
35 __attribute__((unused)) static const char TAG[] = "spi_flash";
36
37 /* This pointer is defined in ROM and extern-ed on targets where CONFIG_SPI_FLASH_ROM_IMPL = y*/
38 #if !CONFIG_SPI_FLASH_ROM_IMPL
39 esp_flash_t *esp_flash_default_chip = NULL;
40 #endif
41
42 #ifndef CONFIG_SPI_FLASH_USE_LEGACY_IMPL
43
44 #ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
45 #define DEFAULT_FLASH_SPEED ESP_FLASH_80MHZ
46 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_40M
47 #define DEFAULT_FLASH_SPEED ESP_FLASH_40MHZ
48 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_26M
49 #define DEFAULT_FLASH_SPEED ESP_FLASH_26MHZ
50 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_20M
51 #define DEFAULT_FLASH_SPEED ESP_FLASH_20MHZ
52 #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_120M
53 #define DEFAULT_FLASH_SPEED ESP_FLASH_120MHZ
54 #else
55 #error Flash frequency not defined! Check the ``CONFIG_ESPTOOLPY_FLASHFREQ_*`` options.
56 #endif
57
58 #if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO)
59 #define DEFAULT_FLASH_MODE SPI_FLASH_QIO
60 #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT)
61 #define DEFAULT_FLASH_MODE SPI_FLASH_QOUT
62 #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO)
63 #define DEFAULT_FLASH_MODE SPI_FLASH_DIO
64 #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT)
65 #define DEFAULT_FLASH_MODE SPI_FLASH_DOUT
66 #elif defined(CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR)
67 #define DEFAULT_FLASH_MODE SPI_FLASH_OPI_STR
68 #elif defined(CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR)
69 #define DEFAULT_FLASH_MODE SPI_FLASH_OPI_DTR
70 #else
71 #define DEFAULT_FLASH_MODE SPI_FLASH_FASTRD
72 #endif
73
74 //TODO: modify cs hold to meet requirements of all chips!!!
75 #if CONFIG_IDF_TARGET_ESP32
76 #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
77 .host_id = SPI1_HOST,\
78 .speed = DEFAULT_FLASH_SPEED, \
79 .cs_num = 0, \
80 .iomux = false, \
81 .input_delay_ns = 0,\
82 .cs_setup = 1,\
83 }
84 #elif CONFIG_IDF_TARGET_ESP32S2
85 #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
86 .host_id = SPI1_HOST,\
87 .speed = DEFAULT_FLASH_SPEED, \
88 .cs_num = 0, \
89 .iomux = true, \
90 .input_delay_ns = 0,\
91 .cs_setup = 1,\
92 }
93 #elif CONFIG_IDF_TARGET_ESP32S3
94 #include "esp32s3/rom/efuse.h"
95 #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
96 .host_id = SPI1_HOST,\
97 .speed = DEFAULT_FLASH_SPEED, \
98 .cs_num = 0, \
99 .iomux = true, \
100 .input_delay_ns = 0,\
101 .cs_setup = 1,\
102 }
103 #elif CONFIG_IDF_TARGET_ESP32C3
104 #include "esp32c3/rom/efuse.h"
105 #if !CONFIG_SPI_FLASH_AUTO_SUSPEND
106 #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
107 .host_id = SPI1_HOST,\
108 .speed = DEFAULT_FLASH_SPEED, \
109 .cs_num = 0, \
110 .iomux = true, \
111 .input_delay_ns = 0,\
112 .cs_setup = 1,\
113 }
114 #else
115 #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
116 .host_id = SPI1_HOST,\
117 .speed = DEFAULT_FLASH_SPEED, \
118 .cs_num = 0, \
119 .iomux = true, \
120 .input_delay_ns = 0,\
121 .auto_sus_en = true,\
122 .cs_setup = 1,\
123 }
124 #endif //!CONFIG_SPI_FLASH_AUTO_SUSPEND
125 #elif CONFIG_IDF_TARGET_ESP32H2
126 #include "esp32h2/rom/efuse.h"
127 #if !CONFIG_SPI_FLASH_AUTO_SUSPEND
128 #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
129 .host_id = SPI1_HOST,\
130 .speed = DEFAULT_FLASH_SPEED, \
131 .cs_num = 0, \
132 .iomux = true, \
133 .input_delay_ns = 0,\
134 }
135 #else
136 #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
137 .host_id = SPI1_HOST,\
138 .speed = DEFAULT_FLASH_SPEED, \
139 .cs_num = 0, \
140 .iomux = true, \
141 .input_delay_ns = 0,\
142 .auto_sus_en = true,\
143 }
144 #endif //!CONFIG_SPI_FLASH_AUTO_SUSPEND
145 #endif
146
147
cs_initialize(esp_flash_t * chip,const esp_flash_spi_device_config_t * config,bool use_iomux,int cs_id)148 static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_flash_spi_device_config_t *config, bool use_iomux, int cs_id)
149 {
150 //Not using spicommon_cs_initialize since we don't want to put the whole
151 //spi_periph_signal into the DRAM. Copy these data from flash before the
152 //cache disabling
153 int cs_io_num = config->cs_io_num;
154 int spics_in = spi_periph_signal[config->host_id].spics_in;
155 int spics_out = spi_periph_signal[config->host_id].spics_out[cs_id];
156 int spics_func = spi_periph_signal[config->host_id].func;
157 uint32_t iomux_reg = GPIO_PIN_MUX_REG[cs_io_num];
158
159 //To avoid the panic caused by flash data line conflicts during cs line
160 //initialization, disable the cache temporarily
161 chip->os_func->start(chip->os_func_data);
162 PIN_INPUT_ENABLE(iomux_reg);
163 if (use_iomux) {
164 gpio_hal_iomux_func_sel(iomux_reg, spics_func);
165 } else {
166 #if SOC_GPIO_PIN_COUNT <= 32
167 GPIO.enable_w1ts.val = (0x1 << cs_io_num);
168 #else
169 if (cs_io_num < 32) {
170 GPIO.enable_w1ts = (0x1 << cs_io_num);
171 } else {
172 GPIO.enable1_w1ts.data = (0x1 << (cs_io_num - 32));
173 }
174 #endif
175 GPIO.pin[cs_io_num].pad_driver = 0;
176 esp_rom_gpio_connect_out_signal(cs_io_num, spics_out, false, false);
177 if (cs_id == 0) {
178 esp_rom_gpio_connect_in_signal(cs_io_num, spics_in, false);
179 }
180 gpio_hal_iomux_func_sel(iomux_reg, PIN_FUNC_GPIO);
181 }
182 chip->os_func->end(chip->os_func_data);
183 }
184
spi_bus_add_flash_device(esp_flash_t ** out_chip,const esp_flash_spi_device_config_t * config)185 esp_err_t spi_bus_add_flash_device(esp_flash_t **out_chip, const esp_flash_spi_device_config_t *config)
186 {
187 if (out_chip == NULL) {
188 return ESP_ERR_INVALID_ARG;
189 }
190 if (!GPIO_IS_VALID_OUTPUT_GPIO(config->cs_io_num)) {
191 return ESP_ERR_INVALID_ARG;
192 }
193 esp_flash_t *chip = NULL;
194 memspi_host_inst_t *host = NULL;
195 esp_err_t ret = ESP_OK;
196
197 uint32_t caps = MALLOC_CAP_DEFAULT;
198 if (config->host_id == SPI1_HOST) caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT;
199
200 chip = (esp_flash_t*)heap_caps_malloc(sizeof(esp_flash_t), caps);
201 if (!chip) {
202 ret = ESP_ERR_NO_MEM;
203 goto fail;
204 }
205
206 host = (memspi_host_inst_t*)heap_caps_malloc(sizeof(memspi_host_inst_t), caps);
207 *chip = (esp_flash_t) {
208 .read_mode = config->io_mode,
209 .host = (spi_flash_host_inst_t*)host,
210 };
211 if (!host) {
212 ret = ESP_ERR_NO_MEM;
213 goto fail;
214 }
215
216 int dev_id = -1;
217 esp_err_t err = esp_flash_init_os_functions(chip, config->host_id, &dev_id);
218 if (err == ESP_ERR_NOT_SUPPORTED) {
219 ESP_LOGE(TAG, "Init os functions failed! No free CS.");
220 } else if (err == ESP_ERR_INVALID_ARG) {
221 ESP_LOGE(TAG, "Init os functions failed! Bus lock not initialized (check CONFIG_SPI_FLASH_SHARE_SPI1_BUS).");
222 }
223 if (err != ESP_OK) {
224 ret = err;
225 goto fail;
226 }
227 // When `CONFIG_SPI_FLASH_SHARE_SPI1_BUS` is not enabled on SPI1 bus, the
228 // `esp_flash_init_os_functions` will not be able to assign a new device ID. In this case, we
229 // use the `cs_id` in the config structure.
230 if (dev_id == -1 && config->host_id == SPI1_HOST) {
231 dev_id = config->cs_id;
232 }
233 assert(dev_id < SOC_SPI_PERIPH_CS_NUM(config->host_id) && dev_id >= 0);
234
235 bool use_iomux = spicommon_bus_using_iomux(config->host_id);
236 memspi_host_config_t host_cfg = {
237 .host_id = config->host_id,
238 .cs_num = dev_id,
239 .iomux = use_iomux,
240 .input_delay_ns = config->input_delay_ns,
241 .speed = config->speed,
242 };
243 err = memspi_host_init_pointers(host, &host_cfg);
244 if (err != ESP_OK) {
245 ret = err;
246 goto fail;
247 }
248
249 // The cs_id inside `config` is deprecated, use the `dev_id` provided by the bus lock instead.
250 cs_initialize(chip, config, use_iomux, dev_id);
251 *out_chip = chip;
252 return ret;
253 fail:
254 // The memory allocated are free'd in the `spi_bus_remove_flash_device`.
255 spi_bus_remove_flash_device(chip);
256 return ret;
257 }
258
spi_bus_remove_flash_device(esp_flash_t * chip)259 esp_err_t spi_bus_remove_flash_device(esp_flash_t *chip)
260 {
261 if (chip==NULL) {
262 return ESP_ERR_INVALID_ARG;
263 }
264 esp_flash_deinit_os_functions(chip);
265 free(chip->host);
266 free(chip);
267 return ESP_OK;
268 }
269
270 /* The default (ie initial boot) no-OS ROM esp_flash_os_functions_t */
271 extern const esp_flash_os_functions_t esp_flash_noos_functions;
272
273 static DRAM_ATTR memspi_host_inst_t esp_flash_default_host;
274
275 static DRAM_ATTR esp_flash_t default_chip = {
276 .read_mode = DEFAULT_FLASH_MODE,
277 .host = (spi_flash_host_inst_t*)&esp_flash_default_host,
278 .os_func = &esp_flash_noos_functions,
279 };
280
281 extern esp_err_t esp_flash_suspend_cmd_init(esp_flash_t* chip);
esp_flash_init_default_chip(void)282 esp_err_t esp_flash_init_default_chip(void)
283 {
284 const esp_rom_spiflash_chip_t *legacy_chip = &g_rom_flashchip;
285 memspi_host_config_t cfg = ESP_FLASH_HOST_CONFIG_DEFAULT();
286
287 #if !CONFIG_IDF_TARGET_ESP32
288 // For esp32s2 spi IOs are configured as from IO MUX by default
289 cfg.iomux = esp_rom_efuse_get_flash_gpio_info() == 0 ? true : false;
290 #endif
291
292 #if CONFIG_ESPTOOLPY_OCT_FLASH
293 cfg.octal_mode_en = 1;
294 cfg.default_io_mode = DEFAULT_FLASH_MODE;
295 #endif
296
297 // For chips need time tuning, get value directely from system here.
298 #if SOC_SPI_MEM_SUPPORT_TIME_TUNING
299 if (spi_timing_is_tuned()) {
300 cfg.using_timing_tuning = 1;
301 spi_timing_get_flash_timing_param(&cfg.timing_reg);
302 }
303 #endif // SOC_SPI_MEM_SUPPORT_TIME_TUNING
304
305 //the host is already initialized, only do init for the data and load it to the host
306 esp_err_t err = memspi_host_init_pointers(&esp_flash_default_host, &cfg);
307 if (err != ESP_OK) {
308 return err;
309 }
310
311 // ROM TODO: account for non-standard default pins in efuse
312 // ROM TODO: to account for chips which are slow to power on, maybe keep probing in a loop here
313 err = esp_flash_init_main(&default_chip);
314 if (err != ESP_OK) {
315 return err;
316 }
317 if (default_chip.size < legacy_chip->chip_size) {
318 ESP_EARLY_LOGE(TAG, "Detected size(%dk) smaller than the size in the binary image header(%dk). Probe failed.", default_chip.size/1024, legacy_chip->chip_size/1024);
319 return ESP_ERR_FLASH_SIZE_NOT_MATCH;
320 }
321
322 if (default_chip.size > legacy_chip->chip_size) {
323 ESP_EARLY_LOGW(TAG, "Detected size(%dk) larger than the size in the binary image header(%dk). Using the size in the binary image header.", default_chip.size/1024, legacy_chip->chip_size/1024);
324 }
325 default_chip.size = legacy_chip->chip_size;
326
327 esp_flash_default_chip = &default_chip;
328 #ifdef CONFIG_SPI_FLASH_AUTO_SUSPEND
329 err = esp_flash_suspend_cmd_init(&default_chip);
330 if (err != ESP_OK) {
331 return err;
332 }
333 #endif
334 return ESP_OK;
335 }
336
esp_flash_app_init(void)337 esp_err_t esp_flash_app_init(void)
338 {
339 esp_err_t err = ESP_OK;
340 #if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
341 err = esp_flash_init_main_bus_lock();
342 if (err != ESP_OK) return err;
343 #endif
344 err = esp_flash_app_enable_os_functions(&default_chip);
345 return err;
346 }
347
348 #endif //!CONFIG_SPI_FLASH_USE_LEGACY_IMPL
349
