1 // Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_WORLD_CONTROLLER_REG_H_ 15 #define _SOC_WORLD_CONTROLLER_REG_H_ 16 17 18 #include "soc.h" 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_1_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x0) 24 /* WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 25 /*description: Core_0 Entry 1 address from WORLD1 to WORLD0.*/ 26 #define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR 0xFFFFFFFF 27 #define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_S)) 28 #define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_V 0xFFFFFFFF 29 #define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_S 0 30 31 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_2_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4) 32 /* WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 33 /*description: Core_0 Entry 2 address from WORLD1 to WORLD0.*/ 34 #define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR 0xFFFFFFFF 35 #define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_S)) 36 #define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_V 0xFFFFFFFF 37 #define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_S 0 38 39 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_3_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x8) 40 /* WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 41 /*description: Core_0 Entry 3 address from WORLD1 to WORLD0.*/ 42 #define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR 0xFFFFFFFF 43 #define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_S)) 44 #define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_V 0xFFFFFFFF 45 #define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_S 0 46 47 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_4_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xC) 48 /* WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 49 /*description: Core_0 Entry 4 address from WORLD1 to WORLD0.*/ 50 #define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR 0xFFFFFFFF 51 #define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_S)) 52 #define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_V 0xFFFFFFFF 53 #define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_S 0 54 55 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_5_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x10) 56 /* WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 57 /*description: Core_0 Entry 5 address from WORLD1 to WORLD0.*/ 58 #define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR 0xFFFFFFFF 59 #define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_S)) 60 #define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_V 0xFFFFFFFF 61 #define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_S 0 62 63 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_6_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x14) 64 /* WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 65 /*description: Core_0 Entry 6 address from WORLD1 to WORLD0.*/ 66 #define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR 0xFFFFFFFF 67 #define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_S)) 68 #define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_V 0xFFFFFFFF 69 #define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_S 0 70 71 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_7_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x18) 72 /* WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 73 /*description: Core_0 Entry 7 address from WORLD1 to WORLD0.*/ 74 #define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR 0xFFFFFFFF 75 #define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_S)) 76 #define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_V 0xFFFFFFFF 77 #define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_S 0 78 79 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_8_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x1C) 80 /* WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 81 /*description: Core_0 Entry 8 address from WORLD1 to WORLD0.*/ 82 #define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR 0xFFFFFFFF 83 #define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_S)) 84 #define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_V 0xFFFFFFFF 85 #define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_S 0 86 87 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_9_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x20) 88 /* WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 89 /*description: Core_0 Entry 9 address from WORLD1 to WORLD0.*/ 90 #define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR 0xFFFFFFFF 91 #define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_S)) 92 #define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_V 0xFFFFFFFF 93 #define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_S 0 94 95 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_10_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x24) 96 /* WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 97 /*description: Core_0 Entry 10 address from WORLD1 to WORLD0.*/ 98 #define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR 0xFFFFFFFF 99 #define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_S)) 100 #define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_V 0xFFFFFFFF 101 #define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_S 0 102 103 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_11_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x28) 104 /* WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 105 /*description: Core_0 Entry 11 address from WORLD1 to WORLD0.*/ 106 #define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR 0xFFFFFFFF 107 #define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_S)) 108 #define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_V 0xFFFFFFFF 109 #define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_S 0 110 111 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_12_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x2C) 112 /* WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 113 /*description: Core_0 Entry 12 address from WORLD1 to WORLD0.*/ 114 #define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR 0xFFFFFFFF 115 #define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_S)) 116 #define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_V 0xFFFFFFFF 117 #define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_S 0 118 119 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_13_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x30) 120 /* WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 121 /*description: Core_0 Entry 13 address from WORLD1 to WORLD0.*/ 122 #define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR 0xFFFFFFFF 123 #define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_S)) 124 #define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_V 0xFFFFFFFF 125 #define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_S 0 126 127 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_CHECK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x7C) 128 /* WORLD_CONTROLLER_CORE_0_ENTRY_CHECK : R/W ;bitpos:[13:1] ;default: 1'b1 ; */ 129 /*description: This filed is used to enable entry address check .*/ 130 #define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK 0x00001FFF 131 #define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_M ((WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_S)) 132 #define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_V 0x1FFF 133 #define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_S 1 134 135 #define WORLD_CONTROLLER_WCL_CORE_0_MESSAGE_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x100) 136 /* WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 137 /*description: This field is used to set address that need to write when enter WORLD0.*/ 138 #define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR 0xFFFFFFFF 139 #define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_M ((WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_S)) 140 #define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_V 0xFFFFFFFF 141 #define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_S 0 142 143 #define WORLD_CONTROLLER_WCL_CORE_0_MESSAGE_MAX_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x104) 144 /* WORLD_CONTROLLER_CORE_0_MESSAGE_MAX : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ 145 /*description: This filed is used to set the max value of clear write_buffer.*/ 146 #define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX 0x0000000F 147 #define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_M ((WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_V)<<(WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_S)) 148 #define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_V 0xF 149 #define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_S 0 150 151 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE1_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x80) 152 /* WORLD_CONTROLLER_CORE_0_CURRENT_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 153 /*description: This bit is used to confirm whether the current state is in entry 1 .*/ 154 #define WORLD_CONTROLLER_CORE_0_CURRENT_1 (BIT(5)) 155 #define WORLD_CONTROLLER_CORE_0_CURRENT_1_M (BIT(5)) 156 #define WORLD_CONTROLLER_CORE_0_CURRENT_1_V 0x1 157 #define WORLD_CONTROLLER_CORE_0_CURRENT_1_S 5 158 /* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 159 /*description: This filed is used to confirm in which entry before enter entry 1.*/ 160 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1 0x0000000F 161 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_S)) 162 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_V 0xF 163 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_S 1 164 /* WORLD_CONTROLLER_CORE_0_FROM_WORLD_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 165 /*description: This bit is used to confirm world before enter entry 1 .*/ 166 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1 (BIT(0)) 167 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1_M (BIT(0)) 168 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1_V 0x1 169 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1_S 0 170 171 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE2_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x84) 172 /* WORLD_CONTROLLER_CORE_0_CURRENT_2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 173 /*description: This bit is used to confirm whether the current state is in entry 2 .*/ 174 #define WORLD_CONTROLLER_CORE_0_CURRENT_2 (BIT(5)) 175 #define WORLD_CONTROLLER_CORE_0_CURRENT_2_M (BIT(5)) 176 #define WORLD_CONTROLLER_CORE_0_CURRENT_2_V 0x1 177 #define WORLD_CONTROLLER_CORE_0_CURRENT_2_S 5 178 /* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 179 /*description: This filed is used to confirm in which entry before enter entry 2.*/ 180 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2 0x0000000F 181 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_S)) 182 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_V 0xF 183 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_S 1 184 /* WORLD_CONTROLLER_CORE_0_FROM_WORLD_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 185 /*description: This bit is used to confirm world before enter entry 2 .*/ 186 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2 (BIT(0)) 187 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2_M (BIT(0)) 188 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2_V 0x1 189 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2_S 0 190 191 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE3_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x88) 192 /* WORLD_CONTROLLER_CORE_0_CURRENT_3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 193 /*description: This bit is used to confirm whether the current state is in entry 3 .*/ 194 #define WORLD_CONTROLLER_CORE_0_CURRENT_3 (BIT(5)) 195 #define WORLD_CONTROLLER_CORE_0_CURRENT_3_M (BIT(5)) 196 #define WORLD_CONTROLLER_CORE_0_CURRENT_3_V 0x1 197 #define WORLD_CONTROLLER_CORE_0_CURRENT_3_S 5 198 /* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 199 /*description: This filed is used to confirm in which entry before enter entry 3.*/ 200 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3 0x0000000F 201 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_S)) 202 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_V 0xF 203 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_S 1 204 /* WORLD_CONTROLLER_CORE_0_FROM_WORLD_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 205 /*description: This bit is used to confirm world before enter entry 3 .*/ 206 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3 (BIT(0)) 207 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3_M (BIT(0)) 208 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3_V 0x1 209 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3_S 0 210 211 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE4_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x8C) 212 /* WORLD_CONTROLLER_CORE_0_CURRENT_4 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 213 /*description: This bit is used to confirm whether the current state is in entry 4 .*/ 214 #define WORLD_CONTROLLER_CORE_0_CURRENT_4 (BIT(5)) 215 #define WORLD_CONTROLLER_CORE_0_CURRENT_4_M (BIT(5)) 216 #define WORLD_CONTROLLER_CORE_0_CURRENT_4_V 0x1 217 #define WORLD_CONTROLLER_CORE_0_CURRENT_4_S 5 218 /* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 219 /*description: This filed is used to confirm in which entry before enter entry 4.*/ 220 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4 0x0000000F 221 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_S)) 222 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_V 0xF 223 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_S 1 224 /* WORLD_CONTROLLER_CORE_0_FROM_WORLD_4 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 225 /*description: This bit is used to confirm world before enter entry 4 .*/ 226 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4 (BIT(0)) 227 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4_M (BIT(0)) 228 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4_V 0x1 229 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4_S 0 230 231 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE5_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x90) 232 /* WORLD_CONTROLLER_CORE_0_CURRENT_5 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 233 /*description: This bit is used to confirm whether the current state is in entry 5 .*/ 234 #define WORLD_CONTROLLER_CORE_0_CURRENT_5 (BIT(5)) 235 #define WORLD_CONTROLLER_CORE_0_CURRENT_5_M (BIT(5)) 236 #define WORLD_CONTROLLER_CORE_0_CURRENT_5_V 0x1 237 #define WORLD_CONTROLLER_CORE_0_CURRENT_5_S 5 238 /* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 239 /*description: This filed is used to confirm in which entry before enter entry 5.*/ 240 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5 0x0000000F 241 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_S)) 242 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_V 0xF 243 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_S 1 244 /* WORLD_CONTROLLER_CORE_0_FROM_WORLD_5 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 245 /*description: This bit is used to confirm world before enter entry 5 .*/ 246 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5 (BIT(0)) 247 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5_M (BIT(0)) 248 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5_V 0x1 249 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5_S 0 250 251 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE6_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x94) 252 /* WORLD_CONTROLLER_CORE_0_CURRENT_6 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 253 /*description: This bit is used to confirm whether the current state is in entry 6 .*/ 254 #define WORLD_CONTROLLER_CORE_0_CURRENT_6 (BIT(5)) 255 #define WORLD_CONTROLLER_CORE_0_CURRENT_6_M (BIT(5)) 256 #define WORLD_CONTROLLER_CORE_0_CURRENT_6_V 0x1 257 #define WORLD_CONTROLLER_CORE_0_CURRENT_6_S 5 258 /* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 259 /*description: This filed is used to confirm in which entry before enter entry 6.*/ 260 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6 0x0000000F 261 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_S)) 262 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_V 0xF 263 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_S 1 264 /* WORLD_CONTROLLER_CORE_0_FROM_WORLD_6 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 265 /*description: This bit is used to confirm world before enter entry 6 .*/ 266 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6 (BIT(0)) 267 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6_M (BIT(0)) 268 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6_V 0x1 269 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6_S 0 270 271 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE7_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x98) 272 /* WORLD_CONTROLLER_CORE_0_CURRENT_7 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 273 /*description: This bit is used to confirm whether the current state is in entry 7 .*/ 274 #define WORLD_CONTROLLER_CORE_0_CURRENT_7 (BIT(5)) 275 #define WORLD_CONTROLLER_CORE_0_CURRENT_7_M (BIT(5)) 276 #define WORLD_CONTROLLER_CORE_0_CURRENT_7_V 0x1 277 #define WORLD_CONTROLLER_CORE_0_CURRENT_7_S 5 278 /* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 279 /*description: This filed is used to confirm in which entry before enter entry 7.*/ 280 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7 0x0000000F 281 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_S)) 282 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_V 0xF 283 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_S 1 284 /* WORLD_CONTROLLER_CORE_0_FROM_WORLD_7 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 285 /*description: This bit is used to confirm world before enter entry 7 .*/ 286 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7 (BIT(0)) 287 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7_M (BIT(0)) 288 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7_V 0x1 289 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7_S 0 290 291 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE8_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x9C) 292 /* WORLD_CONTROLLER_CORE_0_CURRENT_8 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 293 /*description: This bit is used to confirm whether the current state is in entry 8 .*/ 294 #define WORLD_CONTROLLER_CORE_0_CURRENT_8 (BIT(5)) 295 #define WORLD_CONTROLLER_CORE_0_CURRENT_8_M (BIT(5)) 296 #define WORLD_CONTROLLER_CORE_0_CURRENT_8_V 0x1 297 #define WORLD_CONTROLLER_CORE_0_CURRENT_8_S 5 298 /* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 299 /*description: This filed is used to confirm in which entry before enter entry 8.*/ 300 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8 0x0000000F 301 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_S)) 302 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_V 0xF 303 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_S 1 304 /* WORLD_CONTROLLER_CORE_0_FROM_WORLD_8 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 305 /*description: This bit is used to confirm world before enter entry 8 .*/ 306 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8 (BIT(0)) 307 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8_M (BIT(0)) 308 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8_V 0x1 309 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8_S 0 310 311 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE9_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xA0) 312 /* WORLD_CONTROLLER_CORE_0_CURRENT_9 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 313 /*description: This bit is used to confirm whether the current state is in entry 9 .*/ 314 #define WORLD_CONTROLLER_CORE_0_CURRENT_9 (BIT(5)) 315 #define WORLD_CONTROLLER_CORE_0_CURRENT_9_M (BIT(5)) 316 #define WORLD_CONTROLLER_CORE_0_CURRENT_9_V 0x1 317 #define WORLD_CONTROLLER_CORE_0_CURRENT_9_S 5 318 /* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 319 /*description: This filed is used to confirm in which entry before enter entry 9.*/ 320 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9 0x0000000F 321 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_S)) 322 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_V 0xF 323 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_S 1 324 /* WORLD_CONTROLLER_CORE_0_FROM_WORLD_9 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 325 /*description: This bit is used to confirm world before enter entry 9 .*/ 326 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9 (BIT(0)) 327 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9_M (BIT(0)) 328 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9_V 0x1 329 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9_S 0 330 331 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE10_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xA4) 332 /* WORLD_CONTROLLER_CORE_0_CURRENT_10 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 333 /*description: This bit is used to confirm whether the current state is in entry 10 .*/ 334 #define WORLD_CONTROLLER_CORE_0_CURRENT_10 (BIT(5)) 335 #define WORLD_CONTROLLER_CORE_0_CURRENT_10_M (BIT(5)) 336 #define WORLD_CONTROLLER_CORE_0_CURRENT_10_V 0x1 337 #define WORLD_CONTROLLER_CORE_0_CURRENT_10_S 5 338 /* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 339 /*description: This filed is used to confirm in which entry before enter entry 10.*/ 340 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10 0x0000000F 341 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_S)) 342 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_V 0xF 343 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_S 1 344 /* WORLD_CONTROLLER_CORE_0_FROM_WORLD_10 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 345 /*description: This bit is used to confirm world before enter entry 10 .*/ 346 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10 (BIT(0)) 347 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10_M (BIT(0)) 348 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10_V 0x1 349 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10_S 0 350 351 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE11_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xA8) 352 /* WORLD_CONTROLLER_CORE_0_CURRENT_11 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 353 /*description: This bit is used to confirm whether the current state is in entry 11 .*/ 354 #define WORLD_CONTROLLER_CORE_0_CURRENT_11 (BIT(5)) 355 #define WORLD_CONTROLLER_CORE_0_CURRENT_11_M (BIT(5)) 356 #define WORLD_CONTROLLER_CORE_0_CURRENT_11_V 0x1 357 #define WORLD_CONTROLLER_CORE_0_CURRENT_11_S 5 358 /* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 359 /*description: This filed is used to confirm in which entry before enter entry 11.*/ 360 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11 0x0000000F 361 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_S)) 362 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_V 0xF 363 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_S 1 364 /* WORLD_CONTROLLER_CORE_0_FROM_WORLD_11 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 365 /*description: This bit is used to confirm world before enter entry 11 .*/ 366 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11 (BIT(0)) 367 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11_M (BIT(0)) 368 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11_V 0x1 369 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11_S 0 370 371 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE12_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xAC) 372 /* WORLD_CONTROLLER_CORE_0_CURRENT_12 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 373 /*description: This bit is used to confirm whether the current state is in entry 12 .*/ 374 #define WORLD_CONTROLLER_CORE_0_CURRENT_12 (BIT(5)) 375 #define WORLD_CONTROLLER_CORE_0_CURRENT_12_M (BIT(5)) 376 #define WORLD_CONTROLLER_CORE_0_CURRENT_12_V 0x1 377 #define WORLD_CONTROLLER_CORE_0_CURRENT_12_S 5 378 /* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 379 /*description: This filed is used to confirm in which entry before enter entry 12.*/ 380 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12 0x0000000F 381 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_S)) 382 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_V 0xF 383 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_S 1 384 /* WORLD_CONTROLLER_CORE_0_FROM_WORLD_12 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 385 /*description: This bit is used to confirm world before enter entry 12 .*/ 386 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12 (BIT(0)) 387 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12_M (BIT(0)) 388 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12_V 0x1 389 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12_S 0 390 391 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE13_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xB0) 392 /* WORLD_CONTROLLER_CORE_0_CURRENT_13 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 393 /*description: This bit is used to confirm whether the current state is in entry 13 .*/ 394 #define WORLD_CONTROLLER_CORE_0_CURRENT_13 (BIT(5)) 395 #define WORLD_CONTROLLER_CORE_0_CURRENT_13_M (BIT(5)) 396 #define WORLD_CONTROLLER_CORE_0_CURRENT_13_V 0x1 397 #define WORLD_CONTROLLER_CORE_0_CURRENT_13_S 5 398 /* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 399 /*description: This filed is used to confirm in which entry before enter entry 13.*/ 400 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13 0x0000000F 401 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_S)) 402 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_V 0xF 403 #define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_S 1 404 /* WORLD_CONTROLLER_CORE_0_FROM_WORLD_13 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 405 /*description: This bit is used to confirm world before enter entry 13 .*/ 406 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13 (BIT(0)) 407 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13_M (BIT(0)) 408 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13_V 0x1 409 #define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13_S 0 410 411 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE_CURRENT_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xFC) 412 /* WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT : R/W ;bitpos:[13:1] ;default: 13'b0 ; */ 413 /*description: This field is used to quickly read and rewrite the current field of all STATUSTA 414 BLE registers.For example.*/ 415 #define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT 0x00001FFF 416 #define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_M ((WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_V)<<(WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_S)) 417 #define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_V 0x1FFF 418 #define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_S 1 419 420 #define WORLD_CONTROLLER_WCL_CORE_0_MESSAGE_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x108) 421 /* WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE : RO ;bitpos:[6] ;default: 1'b0 ; */ 422 /*description: If this bit is 1.*/ 423 #define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE (BIT(6)) 424 #define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_M (BIT(6)) 425 #define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_V 0x1 426 #define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_S 6 427 /* WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE : RO ;bitpos:[5] ;default: 1'b0 ; */ 428 /*description: If this bit is 1.*/ 429 #define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE (BIT(5)) 430 #define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE_M (BIT(5)) 431 #define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE_V 0x1 432 #define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE_S 5 433 /* WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT : RO ;bitpos:[4:1] ;default: 4'b0 ; */ 434 /*description: This field indicates the data to be written next time.*/ 435 #define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT 0x0000000F 436 #define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_M ((WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_V)<<(WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_S)) 437 #define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_V 0xF 438 #define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_S 1 439 /* WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH : RO ;bitpos:[0] ;default: 1'b0 ; */ 440 /*description: This bit indicates whether the check is successful.*/ 441 #define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH (BIT(0)) 442 #define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH_M (BIT(0)) 443 #define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH_V 0x1 444 #define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH_S 0 445 446 #define WORLD_CONTROLLER_WCL_CORE_0_WORLD_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x140) 447 /* WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR : RW ;bitpos:[31:0] ;default: 32'b0 ; */ 448 /*description: This field is used to configure the entry address from WORLD0 to WORLD1.*/ 449 #define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR 0xFFFFFFFF 450 #define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_S)) 451 #define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_V 0xFFFFFFFF 452 #define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_S 0 453 454 #define WORLD_CONTROLLER_WCL_CORE_0_WORLD_PREPARE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x144) 455 /* WORLD_CONTROLLER_CORE_0_WORLD_PREPARE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ 456 /*description: This field to used to set world to enter.*/ 457 #define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE 0x00000003 458 #define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_M ((WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_S)) 459 #define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_V 0x3 460 #define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_S 0 461 462 #define WORLD_CONTROLLER_WCL_CORE_0_WORLD_UPDATE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x148) 463 /* WORLD_CONTROLLER_CORE_0_UPDATE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ 464 /*description: This field is used to update configuration completed.*/ 465 #define WORLD_CONTROLLER_CORE_0_UPDATE 0xFFFFFFFF 466 #define WORLD_CONTROLLER_CORE_0_UPDATE_M ((WORLD_CONTROLLER_CORE_0_UPDATE_V)<<(WORLD_CONTROLLER_CORE_0_UPDATE_S)) 467 #define WORLD_CONTROLLER_CORE_0_UPDATE_V 0xFFFFFFFF 468 #define WORLD_CONTROLLER_CORE_0_UPDATE_S 0 469 470 #define WORLD_CONTROLLER_WCL_CORE_0_WORLD_CANCEL_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x14C) 471 /* WORLD_CONTROLLER_CORE_0_WORLD_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ 472 /*description: This field is used to cancel switch world configuration.*/ 473 #define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL 0xFFFFFFFF 474 #define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_M ((WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_S)) 475 #define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_V 0xFFFFFFFF 476 #define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_S 0 477 478 #define WORLD_CONTROLLER_WCL_CORE_0_WORLD_IRAM0_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x150) 479 /* WORLD_CONTROLLER_CORE_0_WORLD_IRAM0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ 480 /*description: this field is used to read current world of Iram0 bus.*/ 481 #define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0 0x00000003 482 #define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_M ((WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_S)) 483 #define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_V 0x3 484 #define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_S 0 485 486 #define WORLD_CONTROLLER_WCL_CORE_0_WORLD_DRAM0_PIF_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x154) 487 /* WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ 488 /*description: this field is used to read current world of Dram0 bus and PIF bus.*/ 489 #define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF 0x00000003 490 #define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_M ((WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_S)) 491 #define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_V 0x3 492 #define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_S 0 493 494 #define WORLD_CONTROLLER_WCL_CORE_0_WORLD_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x158) 495 /* WORLD_CONTROLLER_CORE_0_WORLD_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ 496 /*description: This bit indicates whether is preparing to switch to WORLD1.*/ 497 #define WORLD_CONTROLLER_CORE_0_WORLD_PHASE (BIT(0)) 498 #define WORLD_CONTROLLER_CORE_0_WORLD_PHASE_M (BIT(0)) 499 #define WORLD_CONTROLLER_CORE_0_WORLD_PHASE_V 0x1 500 #define WORLD_CONTROLLER_CORE_0_WORLD_PHASE_S 0 501 502 #define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_ENABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x180) 503 /* WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ 504 /*description: this field is used to set NMI mask.*/ 505 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE 0xFFFFFFFF 506 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_S)) 507 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_V 0xFFFFFFFF 508 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_S 0 509 510 #define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x184) 511 /* WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 512 /*description: this field to used to set trigger address.*/ 513 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR 0xFFFFFFFF 514 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_S)) 515 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_V 0xFFFFFFFF 516 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_S 0 517 518 #define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_DISABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x188) 519 /* WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ 520 /*description: this field is used to disable NMI mask.*/ 521 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE 0xFFFFFFFF 522 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_S)) 523 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_V 0xFFFFFFFF 524 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_S 0 525 526 #define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_CANCLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x18C) 527 /* WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ 528 /*description: this field is used to cancel NMI mask disable function..*/ 529 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL 0xFFFFFFFF 530 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_S)) 531 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_V 0xFFFFFFFF 532 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_S 0 533 534 #define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x190) 535 /* WORLD_CONTROLLER_CORE_0_NMI_MASK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 536 /*description: this bit is used to mask NMI interrupt.*/ 537 #define WORLD_CONTROLLER_CORE_0_NMI_MASK (BIT(0)) 538 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_M (BIT(0)) 539 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_V 0x1 540 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_S 0 541 542 #define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x194) 543 /* WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ 544 /*description: this bit is used to indicates whether the NMI interrupt is being masked.*/ 545 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE (BIT(0)) 546 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE_M (BIT(0)) 547 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE_V 0x1 548 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE_S 0 549 550 #define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_1_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x400) 551 /* WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 552 /*description: Core_1 Entry 1 address from WORLD1 to WORLD0.*/ 553 #define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR 0xFFFFFFFF 554 #define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_S)) 555 #define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_V 0xFFFFFFFF 556 #define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_S 0 557 558 #define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_2_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x404) 559 /* WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 560 /*description: Core_1 Entry 2 address from WORLD1 to WORLD0.*/ 561 #define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR 0xFFFFFFFF 562 #define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_S)) 563 #define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_V 0xFFFFFFFF 564 #define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_S 0 565 566 #define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_3_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x408) 567 /* WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 568 /*description: Core_1 Entry 3 address from WORLD1 to WORLD0.*/ 569 #define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR 0xFFFFFFFF 570 #define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_S)) 571 #define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_V 0xFFFFFFFF 572 #define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_S 0 573 574 #define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_4_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x40C) 575 /* WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 576 /*description: Core_1 Entry 4 address from WORLD1 to WORLD0.*/ 577 #define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR 0xFFFFFFFF 578 #define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_S)) 579 #define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_V 0xFFFFFFFF 580 #define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_S 0 581 582 #define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_5_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x410) 583 /* WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 584 /*description: Core_1 Entry 5 address from WORLD1 to WORLD0.*/ 585 #define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR 0xFFFFFFFF 586 #define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_S)) 587 #define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_V 0xFFFFFFFF 588 #define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_S 0 589 590 #define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_6_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x414) 591 /* WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 592 /*description: Core_1 Entry 6 address from WORLD1 to WORLD0.*/ 593 #define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR 0xFFFFFFFF 594 #define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_S)) 595 #define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_V 0xFFFFFFFF 596 #define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_S 0 597 598 #define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_7_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x418) 599 /* WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 600 /*description: Core_1 Entry 7 address from WORLD1 to WORLD0.*/ 601 #define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR 0xFFFFFFFF 602 #define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_S)) 603 #define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_V 0xFFFFFFFF 604 #define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_S 0 605 606 #define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_8_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x41C) 607 /* WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 608 /*description: Core_1 Entry 8 address from WORLD1 to WORLD0.*/ 609 #define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR 0xFFFFFFFF 610 #define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_S)) 611 #define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_V 0xFFFFFFFF 612 #define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_S 0 613 614 #define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_9_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x420) 615 /* WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 616 /*description: Core_1 Entry 9 address from WORLD1 to WORLD0.*/ 617 #define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR 0xFFFFFFFF 618 #define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_S)) 619 #define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_V 0xFFFFFFFF 620 #define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_S 0 621 622 #define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_10_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x424) 623 /* WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 624 /*description: Core_1 Entry 10 address from WORLD1 to WORLD0.*/ 625 #define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR 0xFFFFFFFF 626 #define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_S)) 627 #define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_V 0xFFFFFFFF 628 #define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_S 0 629 630 #define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_11_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x428) 631 /* WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 632 /*description: Core_1 Entry 11 address from WORLD1 to WORLD0.*/ 633 #define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR 0xFFFFFFFF 634 #define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_S)) 635 #define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_V 0xFFFFFFFF 636 #define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_S 0 637 638 #define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_12_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x42C) 639 /* WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 640 /*description: Core_1 Entry 12 address from WORLD1 to WORLD0.*/ 641 #define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR 0xFFFFFFFF 642 #define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_S)) 643 #define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_V 0xFFFFFFFF 644 #define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_S 0 645 646 #define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_13_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x430) 647 /* WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ 648 /*description: Core_1 Entry 13 address from WORLD1 to WORLD0.*/ 649 #define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR 0xFFFFFFFF 650 #define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_S)) 651 #define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_V 0xFFFFFFFF 652 #define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_S 0 653 654 #define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_CHECK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x47C) 655 /* WORLD_CONTROLLER_CORE_1_ENTRY_CHECK : R/W ;bitpos:[13:1] ;default: 1'b1 ; */ 656 /*description: This filed is used to enable entry address check .*/ 657 #define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK 0x00001FFF 658 #define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_M ((WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_S)) 659 #define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_V 0x1FFF 660 #define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_S 1 661 662 #define WORLD_CONTROLLER_WCL_CORE_1_MESSAGE_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x500) 663 /* WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 664 /*description: This field is used to set address that need to write when enter WORLD0.*/ 665 #define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR 0xFFFFFFFF 666 #define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_M ((WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_S)) 667 #define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_V 0xFFFFFFFF 668 #define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_S 0 669 670 #define WORLD_CONTROLLER_WCL_CORE_1_MESSAGE_MAX_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x504) 671 /* WORLD_CONTROLLER_CORE_1_MESSAGE_MAX : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ 672 /*description: This filed is used to set the max value of clear write_buffer.*/ 673 #define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX 0x0000000F 674 #define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_M ((WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_V)<<(WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_S)) 675 #define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_V 0xF 676 #define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_S 0 677 678 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE1_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x480) 679 /* WORLD_CONTROLLER_CORE_1_CURRENT_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 680 /*description: This bit is used to confirm whether the current state is in entry 1 .*/ 681 #define WORLD_CONTROLLER_CORE_1_CURRENT_1 (BIT(5)) 682 #define WORLD_CONTROLLER_CORE_1_CURRENT_1_M (BIT(5)) 683 #define WORLD_CONTROLLER_CORE_1_CURRENT_1_V 0x1 684 #define WORLD_CONTROLLER_CORE_1_CURRENT_1_S 5 685 /* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 686 /*description: This filed is used to confirm in which entry before enter entry 1.*/ 687 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1 0x0000000F 688 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_S)) 689 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_V 0xF 690 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_S 1 691 /* WORLD_CONTROLLER_CORE_1_FROM_WORLD_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 692 /*description: This bit is used to confirm world before enter entry 1 .*/ 693 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1 (BIT(0)) 694 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1_M (BIT(0)) 695 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1_V 0x1 696 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1_S 0 697 698 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE2_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x484) 699 /* WORLD_CONTROLLER_CORE_1_CURRENT_2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 700 /*description: This bit is used to confirm whether the current state is in entry 2 .*/ 701 #define WORLD_CONTROLLER_CORE_1_CURRENT_2 (BIT(5)) 702 #define WORLD_CONTROLLER_CORE_1_CURRENT_2_M (BIT(5)) 703 #define WORLD_CONTROLLER_CORE_1_CURRENT_2_V 0x1 704 #define WORLD_CONTROLLER_CORE_1_CURRENT_2_S 5 705 /* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 706 /*description: This filed is used to confirm in which entry before enter entry 2.*/ 707 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2 0x0000000F 708 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_S)) 709 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_V 0xF 710 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_S 1 711 /* WORLD_CONTROLLER_CORE_1_FROM_WORLD_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 712 /*description: This bit is used to confirm world before enter entry 2 .*/ 713 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2 (BIT(0)) 714 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2_M (BIT(0)) 715 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2_V 0x1 716 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2_S 0 717 718 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE3_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x488) 719 /* WORLD_CONTROLLER_CORE_1_CURRENT_3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 720 /*description: This bit is used to confirm whether the current state is in entry 3 .*/ 721 #define WORLD_CONTROLLER_CORE_1_CURRENT_3 (BIT(5)) 722 #define WORLD_CONTROLLER_CORE_1_CURRENT_3_M (BIT(5)) 723 #define WORLD_CONTROLLER_CORE_1_CURRENT_3_V 0x1 724 #define WORLD_CONTROLLER_CORE_1_CURRENT_3_S 5 725 /* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 726 /*description: This filed is used to confirm in which entry before enter entry 3.*/ 727 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3 0x0000000F 728 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_S)) 729 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_V 0xF 730 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_S 1 731 /* WORLD_CONTROLLER_CORE_1_FROM_WORLD_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 732 /*description: This bit is used to confirm world before enter entry 3 .*/ 733 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3 (BIT(0)) 734 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3_M (BIT(0)) 735 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3_V 0x1 736 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3_S 0 737 738 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE4_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x48C) 739 /* WORLD_CONTROLLER_CORE_1_CURRENT_4 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 740 /*description: This bit is used to confirm whether the current state is in entry 4 .*/ 741 #define WORLD_CONTROLLER_CORE_1_CURRENT_4 (BIT(5)) 742 #define WORLD_CONTROLLER_CORE_1_CURRENT_4_M (BIT(5)) 743 #define WORLD_CONTROLLER_CORE_1_CURRENT_4_V 0x1 744 #define WORLD_CONTROLLER_CORE_1_CURRENT_4_S 5 745 /* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 746 /*description: This filed is used to confirm in which entry before enter entry 4.*/ 747 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4 0x0000000F 748 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_S)) 749 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_V 0xF 750 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_S 1 751 /* WORLD_CONTROLLER_CORE_1_FROM_WORLD_4 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 752 /*description: This bit is used to confirm world before enter entry 4 .*/ 753 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4 (BIT(0)) 754 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4_M (BIT(0)) 755 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4_V 0x1 756 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4_S 0 757 758 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE5_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x490) 759 /* WORLD_CONTROLLER_CORE_1_CURRENT_5 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 760 /*description: This bit is used to confirm whether the current state is in entry 5 .*/ 761 #define WORLD_CONTROLLER_CORE_1_CURRENT_5 (BIT(5)) 762 #define WORLD_CONTROLLER_CORE_1_CURRENT_5_M (BIT(5)) 763 #define WORLD_CONTROLLER_CORE_1_CURRENT_5_V 0x1 764 #define WORLD_CONTROLLER_CORE_1_CURRENT_5_S 5 765 /* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 766 /*description: This filed is used to confirm in which entry before enter entry 5.*/ 767 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5 0x0000000F 768 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_S)) 769 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_V 0xF 770 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_S 1 771 /* WORLD_CONTROLLER_CORE_1_FROM_WORLD_5 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 772 /*description: This bit is used to confirm world before enter entry 5 .*/ 773 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5 (BIT(0)) 774 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5_M (BIT(0)) 775 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5_V 0x1 776 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5_S 0 777 778 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE6_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x494) 779 /* WORLD_CONTROLLER_CORE_1_CURRENT_6 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 780 /*description: This bit is used to confirm whether the current state is in entry 6 .*/ 781 #define WORLD_CONTROLLER_CORE_1_CURRENT_6 (BIT(5)) 782 #define WORLD_CONTROLLER_CORE_1_CURRENT_6_M (BIT(5)) 783 #define WORLD_CONTROLLER_CORE_1_CURRENT_6_V 0x1 784 #define WORLD_CONTROLLER_CORE_1_CURRENT_6_S 5 785 /* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 786 /*description: This filed is used to confirm in which entry before enter entry 6.*/ 787 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6 0x0000000F 788 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_S)) 789 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_V 0xF 790 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_S 1 791 /* WORLD_CONTROLLER_CORE_1_FROM_WORLD_6 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 792 /*description: This bit is used to confirm world before enter entry 6 .*/ 793 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6 (BIT(0)) 794 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6_M (BIT(0)) 795 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6_V 0x1 796 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6_S 0 797 798 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE7_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x498) 799 /* WORLD_CONTROLLER_CORE_1_CURRENT_7 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 800 /*description: This bit is used to confirm whether the current state is in entry 7 .*/ 801 #define WORLD_CONTROLLER_CORE_1_CURRENT_7 (BIT(5)) 802 #define WORLD_CONTROLLER_CORE_1_CURRENT_7_M (BIT(5)) 803 #define WORLD_CONTROLLER_CORE_1_CURRENT_7_V 0x1 804 #define WORLD_CONTROLLER_CORE_1_CURRENT_7_S 5 805 /* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 806 /*description: This filed is used to confirm in which entry before enter entry 7.*/ 807 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7 0x0000000F 808 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_S)) 809 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_V 0xF 810 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_S 1 811 /* WORLD_CONTROLLER_CORE_1_FROM_WORLD_7 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 812 /*description: This bit is used to confirm world before enter entry 7 .*/ 813 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7 (BIT(0)) 814 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7_M (BIT(0)) 815 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7_V 0x1 816 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7_S 0 817 818 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE8_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x49C) 819 /* WORLD_CONTROLLER_CORE_1_CURRENT_8 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 820 /*description: This bit is used to confirm whether the current state is in entry 8 .*/ 821 #define WORLD_CONTROLLER_CORE_1_CURRENT_8 (BIT(5)) 822 #define WORLD_CONTROLLER_CORE_1_CURRENT_8_M (BIT(5)) 823 #define WORLD_CONTROLLER_CORE_1_CURRENT_8_V 0x1 824 #define WORLD_CONTROLLER_CORE_1_CURRENT_8_S 5 825 /* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 826 /*description: This filed is used to confirm in which entry before enter entry 8.*/ 827 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8 0x0000000F 828 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_S)) 829 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_V 0xF 830 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_S 1 831 /* WORLD_CONTROLLER_CORE_1_FROM_WORLD_8 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 832 /*description: This bit is used to confirm world before enter entry 8 .*/ 833 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8 (BIT(0)) 834 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8_M (BIT(0)) 835 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8_V 0x1 836 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8_S 0 837 838 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE9_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4A0) 839 /* WORLD_CONTROLLER_CORE_1_CURRENT_9 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 840 /*description: This bit is used to confirm whether the current state is in entry 9 .*/ 841 #define WORLD_CONTROLLER_CORE_1_CURRENT_9 (BIT(5)) 842 #define WORLD_CONTROLLER_CORE_1_CURRENT_9_M (BIT(5)) 843 #define WORLD_CONTROLLER_CORE_1_CURRENT_9_V 0x1 844 #define WORLD_CONTROLLER_CORE_1_CURRENT_9_S 5 845 /* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 846 /*description: This filed is used to confirm in which entry before enter entry 9.*/ 847 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9 0x0000000F 848 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_S)) 849 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_V 0xF 850 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_S 1 851 /* WORLD_CONTROLLER_CORE_1_FROM_WORLD_9 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 852 /*description: This bit is used to confirm world before enter entry 9 .*/ 853 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9 (BIT(0)) 854 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9_M (BIT(0)) 855 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9_V 0x1 856 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9_S 0 857 858 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE10_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4A4) 859 /* WORLD_CONTROLLER_CORE_1_CURRENT_10 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 860 /*description: This bit is used to confirm whether the current state is in entry 10 .*/ 861 #define WORLD_CONTROLLER_CORE_1_CURRENT_10 (BIT(5)) 862 #define WORLD_CONTROLLER_CORE_1_CURRENT_10_M (BIT(5)) 863 #define WORLD_CONTROLLER_CORE_1_CURRENT_10_V 0x1 864 #define WORLD_CONTROLLER_CORE_1_CURRENT_10_S 5 865 /* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 866 /*description: This filed is used to confirm in which entry before enter entry 10.*/ 867 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10 0x0000000F 868 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_S)) 869 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_V 0xF 870 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_S 1 871 /* WORLD_CONTROLLER_CORE_1_FROM_WORLD_10 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 872 /*description: This bit is used to confirm world before enter entry 10 .*/ 873 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10 (BIT(0)) 874 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10_M (BIT(0)) 875 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10_V 0x1 876 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10_S 0 877 878 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE11_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4A8) 879 /* WORLD_CONTROLLER_CORE_1_CURRENT_11 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 880 /*description: This bit is used to confirm whether the current state is in entry 11 .*/ 881 #define WORLD_CONTROLLER_CORE_1_CURRENT_11 (BIT(5)) 882 #define WORLD_CONTROLLER_CORE_1_CURRENT_11_M (BIT(5)) 883 #define WORLD_CONTROLLER_CORE_1_CURRENT_11_V 0x1 884 #define WORLD_CONTROLLER_CORE_1_CURRENT_11_S 5 885 /* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 886 /*description: This filed is used to confirm in which entry before enter entry 11.*/ 887 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11 0x0000000F 888 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_S)) 889 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_V 0xF 890 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_S 1 891 /* WORLD_CONTROLLER_CORE_1_FROM_WORLD_11 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 892 /*description: This bit is used to confirm world before enter entry 11 .*/ 893 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11 (BIT(0)) 894 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11_M (BIT(0)) 895 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11_V 0x1 896 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11_S 0 897 898 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE12_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4AC) 899 /* WORLD_CONTROLLER_CORE_1_CURRENT_12 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 900 /*description: This bit is used to confirm whether the current state is in entry 12 .*/ 901 #define WORLD_CONTROLLER_CORE_1_CURRENT_12 (BIT(5)) 902 #define WORLD_CONTROLLER_CORE_1_CURRENT_12_M (BIT(5)) 903 #define WORLD_CONTROLLER_CORE_1_CURRENT_12_V 0x1 904 #define WORLD_CONTROLLER_CORE_1_CURRENT_12_S 5 905 /* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 906 /*description: This filed is used to confirm in which entry before enter entry 12.*/ 907 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12 0x0000000F 908 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_S)) 909 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_V 0xF 910 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_S 1 911 /* WORLD_CONTROLLER_CORE_1_FROM_WORLD_12 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 912 /*description: This bit is used to confirm world before enter entry 12 .*/ 913 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12 (BIT(0)) 914 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12_M (BIT(0)) 915 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12_V 0x1 916 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12_S 0 917 918 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE13_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4B0) 919 /* WORLD_CONTROLLER_CORE_1_CURRENT_13 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 920 /*description: This bit is used to confirm whether the current state is in entry 13 .*/ 921 #define WORLD_CONTROLLER_CORE_1_CURRENT_13 (BIT(5)) 922 #define WORLD_CONTROLLER_CORE_1_CURRENT_13_M (BIT(5)) 923 #define WORLD_CONTROLLER_CORE_1_CURRENT_13_V 0x1 924 #define WORLD_CONTROLLER_CORE_1_CURRENT_13_S 5 925 /* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ 926 /*description: This filed is used to confirm in which entry before enter entry 13.*/ 927 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13 0x0000000F 928 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_S)) 929 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_V 0xF 930 #define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_S 1 931 /* WORLD_CONTROLLER_CORE_1_FROM_WORLD_13 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 932 /*description: This bit is used to confirm world before enter entry 13 .*/ 933 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13 (BIT(0)) 934 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13_M (BIT(0)) 935 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13_V 0x1 936 #define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13_S 0 937 938 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE_CURRENT_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4FC) 939 /* WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT : R/W ;bitpos:[13:1] ;default: 13'b0 ; */ 940 /*description: This field is used to quickly read and rewrite the current field of all STATUSTA 941 BLE registers.For example.*/ 942 #define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT 0x00001FFF 943 #define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_M ((WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_V)<<(WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_S)) 944 #define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_V 0x1FFF 945 #define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_S 1 946 947 #define WORLD_CONTROLLER_WCL_CORE_1_MESSAGE_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x508) 948 /* WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE : RO ;bitpos:[6] ;default: 1'b0 ; */ 949 /*description: If this bit is 1.*/ 950 #define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE (BIT(6)) 951 #define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_M (BIT(6)) 952 #define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_V 0x1 953 #define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_S 6 954 /* WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE : RO ;bitpos:[5] ;default: 1'b0 ; */ 955 /*description: If this bit is 1.*/ 956 #define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE (BIT(5)) 957 #define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE_M (BIT(5)) 958 #define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE_V 0x1 959 #define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE_S 5 960 /* WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT : RO ;bitpos:[4:1] ;default: 4'b0 ; */ 961 /*description: This field indicates the data to be written next time.*/ 962 #define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT 0x0000000F 963 #define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_M ((WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_V)<<(WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_S)) 964 #define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_V 0xF 965 #define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_S 1 966 /* WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH : RO ;bitpos:[0] ;default: 1'b0 ; */ 967 /*description: This bit indicates whether the check is successful.*/ 968 #define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH (BIT(0)) 969 #define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH_M (BIT(0)) 970 #define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH_V 0x1 971 #define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH_S 0 972 973 #define WORLD_CONTROLLER_WCL_CORE_1_WORLD_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x540) 974 /* WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR : RW ;bitpos:[31:0] ;default: 32'b0 ; */ 975 /*description: This field is used to configure the entry address from WORLD0 to WORLD1.*/ 976 #define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR 0xFFFFFFFF 977 #define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_S)) 978 #define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_V 0xFFFFFFFF 979 #define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_S 0 980 981 #define WORLD_CONTROLLER_WCL_CORE_1_WORLD_PREPARE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x544) 982 /* WORLD_CONTROLLER_CORE_1_WORLD_PREPARE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ 983 /*description: This field to used to set world to enter.*/ 984 #define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE 0x00000003 985 #define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_M ((WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_S)) 986 #define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_V 0x3 987 #define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_S 0 988 989 #define WORLD_CONTROLLER_WCL_CORE_1_WORLD_UPDATE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x548) 990 /* WORLD_CONTROLLER_CORE_1_UPDATE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ 991 /*description: This field is used to update configuration completed.*/ 992 #define WORLD_CONTROLLER_CORE_1_UPDATE 0xFFFFFFFF 993 #define WORLD_CONTROLLER_CORE_1_UPDATE_M ((WORLD_CONTROLLER_CORE_1_UPDATE_V)<<(WORLD_CONTROLLER_CORE_1_UPDATE_S)) 994 #define WORLD_CONTROLLER_CORE_1_UPDATE_V 0xFFFFFFFF 995 #define WORLD_CONTROLLER_CORE_1_UPDATE_S 0 996 997 #define WORLD_CONTROLLER_WCL_CORE_1_WORLD_CANCEL_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x54C) 998 /* WORLD_CONTROLLER_CORE_1_WORLD_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ 999 /*description: This field is used to cancel switch world configuration.*/ 1000 #define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL 0xFFFFFFFF 1001 #define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_M ((WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_S)) 1002 #define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_V 0xFFFFFFFF 1003 #define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_S 0 1004 1005 #define WORLD_CONTROLLER_WCL_CORE_1_WORLD_IRAM0_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x550) 1006 /* WORLD_CONTROLLER_CORE_1_WORLD_IRAM0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ 1007 /*description: this field is used to read current world of Iram0 bus.*/ 1008 #define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0 0x00000003 1009 #define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_M ((WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_S)) 1010 #define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_V 0x3 1011 #define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_S 0 1012 1013 #define WORLD_CONTROLLER_WCL_CORE_1_WORLD_DRAM0_PIF_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x554) 1014 /* WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ 1015 /*description: this field is used to read current world of Dram0 bus and PIF bus.*/ 1016 #define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF 0x00000003 1017 #define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_M ((WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_S)) 1018 #define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_V 0x3 1019 #define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_S 0 1020 1021 #define WORLD_CONTROLLER_WCL_CORE_1_WORLD_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x558) 1022 /* WORLD_CONTROLLER_CORE_1_WORLD_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ 1023 /*description: This bit indicates whether is preparing to switch to WORLD1.*/ 1024 #define WORLD_CONTROLLER_CORE_1_WORLD_PHASE (BIT(0)) 1025 #define WORLD_CONTROLLER_CORE_1_WORLD_PHASE_M (BIT(0)) 1026 #define WORLD_CONTROLLER_CORE_1_WORLD_PHASE_V 0x1 1027 #define WORLD_CONTROLLER_CORE_1_WORLD_PHASE_S 0 1028 1029 #define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_ENABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x580) 1030 /* WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ 1031 /*description: this field is used to set NMI mask.*/ 1032 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE 0xFFFFFFFF 1033 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_S)) 1034 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_V 0xFFFFFFFF 1035 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_S 0 1036 1037 #define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x584) 1038 /* WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1039 /*description: this field to used to set trigger address.*/ 1040 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR 0xFFFFFFFF 1041 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_S)) 1042 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_V 0xFFFFFFFF 1043 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_S 0 1044 1045 #define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_DISABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x588) 1046 /* WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ 1047 /*description: this field is used to disable NMI mask.*/ 1048 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE 0xFFFFFFFF 1049 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_S)) 1050 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_V 0xFFFFFFFF 1051 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_S 0 1052 1053 #define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_CANCLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x58C) 1054 /* WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ 1055 /*description: this field is used to cancel NMI mask disable function..*/ 1056 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL 0xFFFFFFFF 1057 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_S)) 1058 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_V 0xFFFFFFFF 1059 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_S 0 1060 1061 #define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x590) 1062 /* WORLD_CONTROLLER_CORE_1_NMI_MASK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1063 /*description: this bit is used to mask NMI interrupt.*/ 1064 #define WORLD_CONTROLLER_CORE_1_NMI_MASK (BIT(0)) 1065 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_M (BIT(0)) 1066 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_V 0x1 1067 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_S 0 1068 1069 #define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x594) 1070 /* WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ 1071 /*description: this bit is used to indicates whether the NMI interrupt is being masked.*/ 1072 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE (BIT(0)) 1073 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_M (BIT(0)) 1074 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_V 0x1 1075 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_S 0 1076 1077 1078 #ifdef __cplusplus 1079 } 1080 #endif 1081 1082 1083 1084 #endif /*_SOC_WORLD_CONTROLLER_REG_H_ */ 1085
