1 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "soc/soc_caps.h"
16 #if SOC_SDMMC_HOST_SUPPORTED
17
18 #include <stdio.h>
19 #include <stdlib.h>
20 #include <string.h>
21 #include "esp_log.h"
22 #include "esp_heap_caps.h"
23 #include "freertos/FreeRTOS.h"
24 #include "freertos/task.h"
25 #include "driver/gpio.h"
26 #include "driver/sdmmc_host.h"
27 #include "driver/sdmmc_defs.h"
28 #include "sdmmc_cmd.h"
29 #include "unity.h"
30
31 /* Second ESP32 board attached as follows:
32 * Master Slave
33 * IO18 EN
34 * IO19 IO0
35 * IO14 SD_CLK
36 * IO15 SD_CMD
37 * IO2 SD_D0
38 * IO4 SD_D1
39 * IO12 SD_D2
40 * IO13 SD_D3
41 */
42
43
44 /* TODO: add SDIO slave header files, remove these definitions */
45
46 #define DR_REG_SLC_MASK 0xfffffc00
47
48 #define SLCCONF1 (DR_REG_SLC_BASE + 0x60)
49 #define SLC_SLC0_RX_STITCH_EN (BIT(6))
50 #define SLC_SLC0_TX_STITCH_EN (BIT(5))
51
52 #define SLC0TX_LINK (DR_REG_SLC_BASE + 0x40)
53 #define SLC_SLC0_TXLINK_PARK (BIT(31))
54 #define SLC_SLC0_TXLINK_RESTART (BIT(30))
55 #define SLC_SLC0_TXLINK_START (BIT(29))
56
57 #define DR_REG_SLCHOST_MASK 0xfffffc00
58 #define SLCHOST_STATE_W0 (DR_REG_SLCHOST_BASE + 0x64)
59 #define SLCHOST_CONF_W0 (DR_REG_SLCHOST_BASE + 0x6C)
60 #define SLCHOST_CONF_W5 (DR_REG_SLCHOST_BASE + 0x80)
61 #define SLCHOST_WIN_CMD (DR_REG_SLCHOST_BASE + 0x84)
62
63 #define SLC_WIN_CMD_READ 0x80
64 #define SLC_WIN_CMD_WRITE 0xC0
65 #define SLC_WIN_CMD_S 8
66
67 #define SLC_THRESHOLD_ADDR 0x1f800
68
69 static const char* TAG = "sdio_test";
70
slave_slchost_reg_read(sdmmc_card_t * card,uint32_t addr,uint32_t * out_val)71 static esp_err_t slave_slchost_reg_read(sdmmc_card_t* card, uint32_t addr, uint32_t* out_val)
72 {
73 if ((addr & DR_REG_SLCHOST_MASK) != DR_REG_SLCHOST_BASE) {
74 ESP_LOGW(TAG, "%s: invalid addr 0x%08x\n", __func__, addr);
75 return ESP_ERR_INVALID_ARG;
76 }
77 return sdmmc_io_read_bytes(card, 1, addr & (~DR_REG_SLCHOST_MASK), out_val, sizeof(*out_val));
78 }
79
slave_slchost_reg_write(sdmmc_card_t * card,uint32_t addr,uint32_t val)80 static esp_err_t slave_slchost_reg_write(sdmmc_card_t* card, uint32_t addr, uint32_t val)
81 {
82 if ((addr & DR_REG_SLCHOST_MASK) != DR_REG_SLCHOST_BASE) {
83 ESP_LOGW(TAG, "%s: invalid addr 0x%08x\n", __func__, addr);
84 return ESP_ERR_INVALID_ARG;
85 }
86 return sdmmc_io_write_bytes(card, 1, addr & (~DR_REG_SLCHOST_MASK), &val, sizeof(val));
87 }
88
slave_slc_reg_read(sdmmc_card_t * card,uint32_t addr,uint32_t * val)89 static esp_err_t slave_slc_reg_read(sdmmc_card_t* card, uint32_t addr, uint32_t* val)
90 {
91 if ((addr & DR_REG_SLC_MASK) != DR_REG_SLC_BASE) {
92 ESP_LOGW(TAG, "%s: invalid addr 0x%08x\n", __func__, addr);
93 return ESP_ERR_INVALID_ARG;
94 }
95 uint32_t word = (addr - DR_REG_SLC_BASE) / 4;
96 if (word > INT8_MAX) {
97 return ESP_ERR_INVALID_ARG;
98 }
99
100 uint32_t window_command = word | (SLC_WIN_CMD_READ << SLC_WIN_CMD_S);
101 esp_err_t err = slave_slchost_reg_write(card, SLCHOST_WIN_CMD, window_command);
102 if (err != ESP_OK) {
103 return err;
104 }
105
106 return slave_slchost_reg_read(card, SLCHOST_STATE_W0, val);
107 }
108
slave_slc_reg_write(sdmmc_card_t * card,uint32_t addr,uint32_t val)109 static esp_err_t slave_slc_reg_write(sdmmc_card_t* card, uint32_t addr, uint32_t val)
110 {
111 if ((addr & DR_REG_SLC_MASK) != DR_REG_SLC_BASE) {
112 ESP_LOGW(TAG, "%s: invalid addr 0x%08x\n", __func__, addr);
113 return ESP_ERR_INVALID_ARG;
114 }
115 uint32_t word = (addr - DR_REG_SLC_BASE) / 4;
116 if (word > INT8_MAX) {
117 return ESP_ERR_INVALID_ARG;
118 }
119
120 esp_err_t err = slave_slchost_reg_write(card, SLCHOST_CONF_W5, val);
121 if (err != ESP_OK) {
122 return err;
123 }
124
125 uint32_t window_command = word | (SLC_WIN_CMD_WRITE << SLC_WIN_CMD_S);
126 return slave_slchost_reg_write(card, SLCHOST_WIN_CMD, window_command);
127 }
128
129 /** Reset and put slave into download mode */
reset_slave(void)130 static void reset_slave(void)
131 {
132 const int pin_en = 18;
133 const int pin_io0 = 19;
134 gpio_config_t gpio_cfg = {
135 .pin_bit_mask = BIT64(pin_en) | BIT64(pin_io0),
136 .mode = GPIO_MODE_OUTPUT_OD,
137 };
138 TEST_ESP_OK(gpio_config(&gpio_cfg));
139 gpio_set_level(pin_en, 0);
140 gpio_set_level(pin_io0, 0);
141 vTaskDelay(10 / portTICK_PERIOD_MS);
142 gpio_set_level(pin_en, 1);
143 vTaskDelay(10 / portTICK_PERIOD_MS);
144 gpio_set_level(pin_io0, 1);
145 }
146
sdio_slave_common_init(sdmmc_card_t * card)147 static void sdio_slave_common_init(sdmmc_card_t* card)
148 {
149 uint8_t card_cap;
150 esp_err_t err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_CARD_CAP, &card_cap);
151 TEST_ESP_OK(err);
152 printf("CAP: 0x%02x\n", card_cap);
153
154 uint8_t hs;
155 err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_HIGHSPEED, &hs);
156 TEST_ESP_OK(err);
157 printf("HS: 0x%02x\n", hs);
158
159
160 #define FUNC1_EN_MASK (BIT(1))
161
162 uint8_t ioe;
163 err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_ENABLE, &ioe);
164 TEST_ESP_OK(err);
165 printf("IOE: 0x%02x\n", ioe);
166
167 uint8_t ior = 0;
168 err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_READY, &ior);
169 TEST_ESP_OK(err);
170 printf("IOR: 0x%02x\n", ior);
171
172 // enable function 1
173 ioe |= FUNC1_EN_MASK;
174 err = sdmmc_io_write_byte(card, 0, SD_IO_CCCR_FN_ENABLE, ioe, NULL);
175 TEST_ESP_OK(err);
176
177 err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_ENABLE, &ioe);
178 TEST_ESP_OK(err);
179 printf("IOE: 0x%02x\n", ioe);
180
181 // wait for the card to become ready
182 while ( (ior & FUNC1_EN_MASK) == 0 ) {
183 err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_READY, &ior);
184 TEST_ESP_OK(err);
185 printf("IOR: 0x%02x\n", ior);
186 }
187
188 // get interrupt status
189 uint8_t ie;
190 err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_INT_ENABLE, &ie);
191 TEST_ESP_OK(err);
192 printf("IE: 0x%02x\n", ie);
193
194 // enable interrupts for function 1&2 and master enable
195 ie |= BIT(0) | FUNC1_EN_MASK;
196 err = sdmmc_io_write_byte(card, 0, SD_IO_CCCR_INT_ENABLE, ie, NULL);
197 TEST_ESP_OK(err);
198
199 err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_INT_ENABLE, &ie);
200 TEST_ESP_OK(err);
201 printf("IE: 0x%02x\n", ie);
202 }
203
204 /** Common for all SDIO devices, set block size for specific function */
sdio_slave_set_blocksize(sdmmc_card_t * card,int function,uint16_t bs)205 static void sdio_slave_set_blocksize(sdmmc_card_t* card, int function, uint16_t bs)
206 {
207 const uint8_t* bs_u8 = (const uint8_t*) &bs;
208 uint16_t bs_read = 0;
209 uint8_t* bs_read_u8 = (uint8_t*) &bs_read;
210 uint32_t offset = SD_IO_FBR_START * function;
211 TEST_ESP_OK( sdmmc_io_write_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEL, bs_u8[0], NULL));
212 TEST_ESP_OK( sdmmc_io_write_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEH, bs_u8[1], NULL));
213 TEST_ESP_OK( sdmmc_io_read_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEL, &bs_read_u8[0]));
214 TEST_ESP_OK( sdmmc_io_read_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEH, &bs_read_u8[1]));
215 TEST_ASSERT_EQUAL_HEX16(bs, bs_read);
216 }
217
218 /**
219 * ESP32 ROM code does not set some SDIO slave registers to the defaults
220 * we need, this function clears/sets some bits.
221 */
esp32_slave_init_extra(sdmmc_card_t * card)222 static void esp32_slave_init_extra(sdmmc_card_t* card)
223 {
224 printf("Initialize some ESP32 SDIO slave registers\n");
225
226 uint32_t reg_val;
227 TEST_ESP_OK( slave_slc_reg_read(card, SLCCONF1, ®_val) );
228 reg_val &= ~(SLC_SLC0_RX_STITCH_EN | SLC_SLC0_TX_STITCH_EN);
229 TEST_ESP_OK( slave_slc_reg_write(card, SLCCONF1, reg_val) );
230
231 TEST_ESP_OK( slave_slc_reg_read(card, SLC0TX_LINK, ®_val) );
232 reg_val |= SLC_SLC0_TXLINK_START;
233 TEST_ESP_OK( slave_slc_reg_write(card, SLC0TX_LINK, reg_val) );
234 }
235
236 /**
237 * ESP32 bootloader implements "SIP" protocol which can be used to exchange
238 * some commands, events, and data packets between the host and the slave.
239 * This function sends a SIP command, testing CMD53 block writes along the way.
240 */
esp32_send_sip_command(sdmmc_card_t * card)241 static void esp32_send_sip_command(sdmmc_card_t* card)
242 {
243 printf("Test block write using CMD53\n");
244 const size_t block_size = 512;
245 uint8_t* data = heap_caps_calloc(1, block_size, MALLOC_CAP_DMA);
246 struct sip_cmd_bootup {
247 uint32_t boot_addr;
248 uint32_t discard_link;
249 };
250 struct sip_cmd_write_reg {
251 uint32_t addr;
252 uint32_t val;
253 };
254 struct sip_hdr {
255 uint8_t fc[2];
256 uint16_t len;
257 uint32_t cmdid;
258 uint32_t seq;
259 };
260
261 struct sip_hdr* hdr = (struct sip_hdr*) data;
262 size_t len;
263
264 #define SEND_WRITE_REG_CMD
265
266 #ifdef SEND_WRITE_REG_CMD
267 struct sip_cmd_write_reg *write_reg = (struct sip_cmd_write_reg*) (data + sizeof(*hdr));
268 len = sizeof(*hdr) + sizeof(*write_reg);
269 hdr->cmdid = 3; /* SIP_CMD_WRITE_REG */
270 write_reg->addr = GPIO_ENABLE_W1TS_REG;
271 write_reg->val = BIT(0) | BIT(2) | BIT(4); /* Turn of RGB LEDs on WROVER-KIT */
272 #else
273 struct sip_cmd_bootup *bootup = (struct sip_cmd_bootup*) (data + sizeof(*hdr));
274 len = sizeof(*hdr) + sizeof(*bootup);
275 hdr->cmdid = 5; /* SIP_CMD_BOOTUP */
276 bootup->boot_addr = 0x4005a980; /* start_tb_console function in ROM */
277 bootup->discard_link = 1;
278 #endif
279 hdr->len = len;
280
281 TEST_ESP_OK( sdmmc_io_write_blocks(card, 1, SLC_THRESHOLD_ADDR - len, data, block_size) );
282 free(data);
283 }
284
test_cmd52_read_write_single_byte(sdmmc_card_t * card)285 static void test_cmd52_read_write_single_byte(sdmmc_card_t* card)
286 {
287 esp_err_t err;
288 printf("Write bytes to slave's W0_REG using CMD52\n");
289 const size_t scratch_area_reg = SLCHOST_CONF_W0 - DR_REG_SLCHOST_BASE;
290
291 const uint8_t test_byte_1 = 0xa5;
292 const uint8_t test_byte_2 = 0xb6;
293 // used to check Read-After-Write
294 uint8_t test_byte_1_raw;
295 uint8_t test_byte_2_raw;
296 uint8_t val = 0;
297 err = sdmmc_io_write_byte(card, 1, scratch_area_reg, test_byte_1, &test_byte_1_raw);
298 TEST_ESP_OK(err);
299 TEST_ASSERT_EQUAL_UINT8(test_byte_1, test_byte_1_raw);
300 err = sdmmc_io_write_byte(card, 1, scratch_area_reg + 1, test_byte_2, &test_byte_2_raw);
301 TEST_ESP_OK(err);
302 TEST_ASSERT_EQUAL_UINT8(test_byte_2, test_byte_2_raw);
303
304 printf("Read back bytes using CMD52\n");
305 TEST_ESP_OK(sdmmc_io_read_byte(card, 1, scratch_area_reg, &val));
306 TEST_ASSERT_EQUAL_UINT8(test_byte_1, val);
307
308 TEST_ESP_OK(sdmmc_io_read_byte(card, 1, scratch_area_reg + 1, &val));
309 TEST_ASSERT_EQUAL_UINT8(test_byte_2, val);
310 }
311
test_cmd53_read_write_multiple_bytes(sdmmc_card_t * card,size_t n_bytes)312 static void test_cmd53_read_write_multiple_bytes(sdmmc_card_t* card, size_t n_bytes)
313 {
314 printf("Write multiple bytes using CMD53\n");
315 const size_t scratch_area_reg = SLCHOST_CONF_W0 - DR_REG_SLCHOST_BASE;
316
317 uint8_t* src = heap_caps_malloc(512, MALLOC_CAP_DMA);
318 uint32_t* src_32 = (uint32_t*) src;
319
320 for (size_t i = 0; i < (n_bytes + 3) / 4; ++i) {
321 src_32[i] = rand();
322 }
323
324 TEST_ESP_OK(sdmmc_io_write_bytes(card, 1, scratch_area_reg, src, n_bytes));
325 ESP_LOG_BUFFER_HEX(TAG, src, n_bytes);
326
327 printf("Read back using CMD52\n");
328 uint8_t* dst = heap_caps_malloc(512, MALLOC_CAP_DMA);
329 for (size_t i = 0; i < n_bytes; ++i) {
330 TEST_ESP_OK(sdmmc_io_read_byte(card, 1, scratch_area_reg + i, &dst[i]));
331 }
332 ESP_LOG_BUFFER_HEX(TAG, dst, n_bytes);
333 TEST_ASSERT_EQUAL_UINT8_ARRAY(src, dst, n_bytes);
334
335 printf("Read back using CMD53\n");
336 TEST_ESP_OK(sdmmc_io_read_bytes(card, 1, scratch_area_reg, dst, n_bytes));
337 ESP_LOG_BUFFER_HEX(TAG, dst, n_bytes);
338 TEST_ASSERT_EQUAL_UINT8_ARRAY(src, dst, n_bytes);
339
340 free(src);
341 free(dst);
342 }
343
344
345 TEST_CASE("can probe and talk to ESP32 SDIO slave", "[sdio][ignore]")
346 {
347 reset_slave();
348
349 /* Probe */
350 sdmmc_host_t config = SDMMC_HOST_DEFAULT();
351 config.flags = SDMMC_HOST_FLAG_1BIT;
352 config.max_freq_khz = SDMMC_FREQ_PROBING;
353
354 sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT();
355 (sdmmc_host_init());
356 (sdmmc_host_init_slot(SDMMC_HOST_SLOT_1, &slot_config));
357 sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t));
358 TEST_ASSERT_NOT_NULL(card);
359 TEST_ESP_OK(sdmmc_card_init(&config, card));
360 sdmmc_card_print_info(stdout, card);
361
362 /* Set up standard SDIO registers */
363 sdio_slave_common_init(card);
364
365 srand(0);
366 for (int repeat = 0; repeat < 4; ++repeat) {
367 test_cmd52_read_write_single_byte(card);
368 test_cmd53_read_write_multiple_bytes(card, 1);
369 test_cmd53_read_write_multiple_bytes(card, 2);
370 test_cmd53_read_write_multiple_bytes(card, 3);
371 test_cmd53_read_write_multiple_bytes(card, 4);
372 test_cmd53_read_write_multiple_bytes(card, 5);
373 test_cmd53_read_write_multiple_bytes(card, 23);
374 test_cmd53_read_write_multiple_bytes(card, 24);
375 }
376
377 sdio_slave_set_blocksize(card, 0, 512);
378 sdio_slave_set_blocksize(card, 1, 512);
379
380 esp32_slave_init_extra(card);
381
382 esp32_send_sip_command(card);
383
384 TEST_ESP_OK(sdmmc_host_deinit());
385 free(card);
386 }
387
388 #endif //SOC_SDMMC_HOST_SUPPORTED
389
