1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdbool.h>
8 #include <stdint.h>
9 #include <stddef.h>
10 #include <assert.h>
11 #include <stdlib.h>
12 #include "sdkconfig.h"
13 #include "esp32s3/rom/ets_sys.h"
14 #include "esp32s3/rom/rtc.h"
15 #include "soc/rtc.h"
16 #include "soc/rtc_cntl_reg.h"
17 #include "soc/rtc_io_reg.h"
18 #include "soc/sens_reg.h"
19 #include "soc/dport_reg.h"
20 #include "soc/efuse_reg.h"
21 #include "soc/syscon_reg.h"
22 #include "soc/system_reg.h"
23 #include "esp_rom_sys.h"
24 #include "regi2c_ctrl.h"
25 #include "soc_log.h"
26 #include "rtc_clk_common.h"
27 #include "hal/usb_serial_jtag_ll.h"
28 #include "sdkconfig.h"
29
30 static const char *TAG = "rtc_clk";
31
32 #define RTC_PLL_FREQ_320M 320
33 #define RTC_PLL_FREQ_480M 480
34 #define DELAY_RTC_CLK_SWITCH 5
35
36 // Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
37 static uint32_t s_cur_pll_freq;
38
39 static uint32_t s_apb_freq;
40
41 static void rtc_clk_cpu_freq_to_8m(void);
42 static bool rtc_clk_set_bbpll_always_on(void);
43
rtc_clk_32k_enable_internal(x32k_config_t cfg)44 void rtc_clk_32k_enable_internal(x32k_config_t cfg)
45 {
46 REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DAC_XTAL_32K, cfg.dac);
47 REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DRES_XTAL_32K, cfg.dres);
48 REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DGM_XTAL_32K, cfg.dgm);
49 REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DBUF_XTAL_32K, cfg.dbuf);
50 SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K);
51 }
52
rtc_clk_32k_enable(bool enable)53 void rtc_clk_32k_enable(bool enable)
54 {
55 if (enable) {
56 SET_PERI_REG_MASK(RTC_IO_XTAL_32P_PAD_REG, RTC_IO_X32P_MUX_SEL);
57 SET_PERI_REG_MASK(RTC_IO_XTAL_32N_PAD_REG, RTC_IO_X32N_MUX_SEL);
58 x32k_config_t cfg = X32K_CONFIG_DEFAULT();
59 rtc_clk_32k_enable_internal(cfg);
60 } else {
61 SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE);
62 CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K);
63 }
64 }
65
rtc_clk_32k_enable_external(void)66 void rtc_clk_32k_enable_external(void)
67 {
68 SET_PERI_REG_MASK(RTC_IO_XTAL_32P_PAD_REG, RTC_IO_X32P_MUX_SEL);
69 SET_PERI_REG_MASK(RTC_IO_XTAL_32N_PAD_REG, RTC_IO_X32N_MUX_SEL);
70 /* TODO: external 32k source may need different settings */
71 x32k_config_t cfg = X32K_CONFIG_DEFAULT();
72 rtc_clk_32k_enable_internal(cfg);
73 }
74
rtc_clk_32k_bootstrap(uint32_t cycle)75 void rtc_clk_32k_bootstrap(uint32_t cycle)
76 {
77 /* No special bootstrapping needed for ESP32-S3, 'cycle' argument is to keep the signature
78 * same as for the ESP32. Just enable the XTAL here.
79 */
80 (void) cycle;
81 rtc_clk_32k_enable(true);
82 }
83
rtc_clk_32k_enabled(void)84 bool rtc_clk_32k_enabled(void)
85 {
86 uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG);
87 /* If xtal xpd is controlled by software */
88 bool xtal_xpd_sw = (xtal_conf & RTC_CNTL_XTAL32K_XPD_FORCE) >> RTC_CNTL_XTAL32K_XPD_FORCE_S;
89 /* If xtal xpd software control is on */
90 bool xtal_xpd_st = (xtal_conf & RTC_CNTL_XPD_XTAL_32K) >> RTC_CNTL_XPD_XTAL_32K_S;
91 bool disabled = xtal_xpd_sw && !xtal_xpd_st;
92 return !disabled;
93 }
94
rtc_clk_8m_enable(bool clk_8m_en,bool d256_en)95 void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
96 {
97 if (clk_8m_en) {
98 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
99 /* no need to wait once enabled by software */
100 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
101 esp_rom_delay_us(DELAY_8M_ENABLE);
102 } else {
103 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
104 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
105 }
106 /* d256 should be independent configured with 8M
107 * Maybe we can split this function into 8m and dmd256
108 */
109 if (d256_en) {
110 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
111 } else {
112 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
113 }
114 }
115
rtc_clk_8m_enabled(void)116 bool rtc_clk_8m_enabled(void)
117 {
118 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
119 }
120
rtc_clk_8md256_enabled(void)121 bool rtc_clk_8md256_enabled(void)
122 {
123 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
124 }
125
wait_dig_dbias_valid(uint64_t rtc_cycles)126 static void wait_dig_dbias_valid(uint64_t rtc_cycles)
127 {
128 rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
129 rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
130 if (slow_clk_freq == RTC_SLOW_FREQ_32K_XTAL) {
131 cal_clk = RTC_CAL_32K_XTAL;
132 } else if (slow_clk_freq == RTC_SLOW_FREQ_8MD256) {
133 cal_clk = RTC_CAL_8MD256;
134 }
135 rtc_clk_cal(cal_clk, rtc_cycles);
136 }
137
rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)138 void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
139 {
140 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
141
142 /* Why we need to connect this clock to digital?
143 * Or maybe this clock should be connected to digital when xtal 32k clock is enabled instead?
144 */
145 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
146 (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
147
148 /* The clk_8m_d256 will be closed when rtc_state in SLEEP,
149 so if the slow_clk is 8md256, clk_8m must be force power on
150 */
151 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0);
152 esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH);
153 }
154
rtc_clk_slow_freq_get(void)155 rtc_slow_freq_t rtc_clk_slow_freq_get(void)
156 {
157 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
158 }
159
rtc_clk_slow_freq_get_hz(void)160 uint32_t rtc_clk_slow_freq_get_hz(void)
161 {
162 switch (rtc_clk_slow_freq_get()) {
163 case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
164 case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K;
165 case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256;
166 }
167 return 0;
168 }
169
rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)170 void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)
171 {
172 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq);
173 esp_rom_delay_us(DELAY_FAST_CLK_SWITCH);
174 }
175
rtc_clk_fast_freq_get(void)176 rtc_fast_freq_t rtc_clk_fast_freq_get(void)
177 {
178 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
179 }
180
rtc_clk_bbpll_disable(void)181 static void rtc_clk_bbpll_disable(void)
182 {
183 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD |
184 RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
185 s_cur_pll_freq = 0;
186 }
187
rtc_clk_bbpll_enable(void)188 static void rtc_clk_bbpll_enable(void)
189 {
190 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD |
191 RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
192 }
193
rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq,int pll_freq)194 void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
195 {
196 uint8_t div_ref;
197 uint8_t div7_0;
198 uint8_t dr1;
199 uint8_t dr3;
200 uint8_t dchgp;
201 uint8_t dcur;
202 uint8_t dbias;
203
204 CLEAR_PERI_REG_MASK(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
205 SET_PERI_REG_MASK(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
206
207 if (pll_freq == RTC_PLL_FREQ_480M) {
208 /* Set this register to let the digital part know 480M PLL is used */
209 SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);
210 /* Configure 480M PLL */
211 switch (xtal_freq) {
212 case RTC_XTAL_FREQ_40M:
213 div_ref = 0;
214 div7_0 = 8;
215 dr1 = 0;
216 dr3 = 0;
217 dchgp = 5;
218 dcur = 3;
219 dbias = 2;
220 break;
221 case RTC_XTAL_FREQ_32M:
222 div_ref = 1;
223 div7_0 = 26;
224 dr1 = 1;
225 dr3 = 1;
226 dchgp = 4;
227 dcur = 0;
228 dbias = 2;
229 break;
230 default:
231 div_ref = 0;
232 div7_0 = 8;
233 dr1 = 0;
234 dr3 = 0;
235 dchgp = 5;
236 dcur = 3;
237 dbias = 2;
238 break;
239 }
240 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
241 } else {
242 /* Clear this register to let the digital part know 320M PLL is used */
243 CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);
244 /* Configure 320M PLL */
245 switch (xtal_freq) {
246 case RTC_XTAL_FREQ_40M:
247 div_ref = 0;
248 div7_0 = 4;
249 dr1 = 0;
250 dr3 = 0;
251 dchgp = 5;
252 dcur = 3;
253 dbias = 2;
254 break;
255 case RTC_XTAL_FREQ_32M:
256 div_ref = 1;
257 div7_0 = 6;
258 dr1 = 0;
259 dr3 = 0;
260 dchgp = 5;
261 dcur = 3;
262 dbias = 2;
263 break;
264 default:
265 div_ref = 0;
266 div7_0 = 4;
267 dr1 = 0;
268 dr3 = 0;
269 dchgp = 5;
270 dcur = 3;
271 dbias = 2;
272 break;
273 }
274 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
275 }
276 uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
277 uint8_t i2c_bbpll_div_7_0 = div7_0;
278 uint8_t i2c_bbpll_dcur = (1 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (2 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
279 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
280 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
281 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
282 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
283 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
284 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
285 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 2);
286 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1);
287 s_cur_pll_freq = pll_freq;
288 }
289
290 /**
291 * Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL.
292 * PLL must already be enabled.
293 * @param cpu_freq new CPU frequency
294 */
rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)295 static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
296 {
297 int dbias = DIG_DBIAS_80M_160M;
298 int per_conf = DPORT_CPUPERIOD_SEL_80;
299 if (cpu_freq_mhz == 80) {
300 /* nothing to do */
301 } else if (cpu_freq_mhz == 160) {
302 per_conf = DPORT_CPUPERIOD_SEL_160;
303 } else if (cpu_freq_mhz == 240) {
304 dbias = DIG_DBIAS_240M;
305 per_conf = DPORT_CPUPERIOD_SEL_240;
306 } else {
307 SOC_LOGE(TAG, "invalid frequency");
308 }
309 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dbias);
310 wait_dig_dbias_valid(2);
311 REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, per_conf);
312 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
313 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL);
314 rtc_clk_apb_freq_update(80 * MHZ);
315 ets_update_cpu_frequency(cpu_freq_mhz);
316 }
317
rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz,rtc_cpu_freq_config_t * out_config)318 bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
319 {
320 uint32_t source_freq_mhz;
321 rtc_cpu_freq_src_t source;
322 uint32_t divider;
323 uint32_t real_freq_mhz;
324
325 uint32_t xtal_freq = (uint32_t) rtc_clk_xtal_freq_get();
326 if (freq_mhz <= xtal_freq) {
327 divider = xtal_freq / freq_mhz;
328 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */
329 if (real_freq_mhz != freq_mhz) {
330 // no suitable divider
331 return false;
332 }
333
334 source_freq_mhz = xtal_freq;
335 source = RTC_CPU_FREQ_SRC_XTAL;
336 } else if (freq_mhz == 80) {
337 real_freq_mhz = freq_mhz;
338 source = RTC_CPU_FREQ_SRC_PLL;
339 source_freq_mhz = RTC_PLL_FREQ_480M;
340 divider = 6;
341 } else if (freq_mhz == 160) {
342 real_freq_mhz = freq_mhz;
343 source = RTC_CPU_FREQ_SRC_PLL;
344 source_freq_mhz = RTC_PLL_FREQ_480M;
345 divider = 3;
346 } else if (freq_mhz == 240) {
347 real_freq_mhz = freq_mhz;
348 source = RTC_CPU_FREQ_SRC_PLL;
349 source_freq_mhz = RTC_PLL_FREQ_480M;
350 divider = 2;
351 } else {
352 // unsupported frequency
353 return false;
354 }
355 *out_config = (rtc_cpu_freq_config_t) {
356 .source = source,
357 .div = divider,
358 .source_freq_mhz = source_freq_mhz,
359 .freq_mhz = real_freq_mhz
360 };
361 return true;
362 }
363
rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t * config)364 void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
365 {
366 uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
367 if (config->source == RTC_CPU_FREQ_SRC_XTAL) {
368 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
369 if ((soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) && !rtc_clk_set_bbpll_always_on()) {
370 // We don't turn off the bbpll if some consumers only depends on bbpll
371 rtc_clk_bbpll_disable();
372 }
373 } else if (config->source == RTC_CPU_FREQ_SRC_PLL) {
374 if (soc_clk_sel != DPORT_SOC_CLK_SEL_PLL) {
375 rtc_clk_bbpll_enable();
376 rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
377 }
378 rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
379 } else if (config->source == RTC_CPU_FREQ_SRC_8M) {
380 rtc_clk_cpu_freq_to_8m();
381 if ((soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) && !rtc_clk_set_bbpll_always_on()) {
382 // We don't turn off the bbpll if some consumers only depends on bbpll
383 rtc_clk_bbpll_disable();
384 }
385 }
386 }
387
rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t * out_config)388 void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
389 {
390 rtc_cpu_freq_src_t source;
391 uint32_t source_freq_mhz;
392 uint32_t div;
393 uint32_t freq_mhz;
394 uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
395 switch (soc_clk_sel) {
396 case DPORT_SOC_CLK_SEL_XTAL: {
397 source = RTC_CPU_FREQ_SRC_XTAL;
398 div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1;
399 source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get();
400 freq_mhz = source_freq_mhz / div;
401 }
402 break;
403 case DPORT_SOC_CLK_SEL_PLL: {
404 source = RTC_CPU_FREQ_SRC_PLL;
405 uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL);
406 uint32_t pllfreq_sel = DPORT_REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);
407 source_freq_mhz = (pllfreq_sel) ? RTC_PLL_FREQ_480M : RTC_PLL_FREQ_320M;
408 if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
409 div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 6 : 4;
410 freq_mhz = 80;
411 } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
412 div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 3 : 2;
413 div = 3;
414 freq_mhz = 160;
415 } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) {
416 div = 2;
417 freq_mhz = 240;
418 } else {
419 SOC_LOGE(TAG, "unsupported frequency configuration");
420 return;
421 }
422 break;
423 }
424 case DPORT_SOC_CLK_SEL_8M:
425 source = RTC_CPU_FREQ_SRC_8M;
426 source_freq_mhz = 8;
427 div = 1;
428 freq_mhz = source_freq_mhz;
429 break;
430 default:
431 SOC_LOGE(TAG, "unsupported frequency configuration");
432 return;
433 }
434 *out_config = (rtc_cpu_freq_config_t) {
435 .source = source,
436 .source_freq_mhz = source_freq_mhz,
437 .div = div,
438 .freq_mhz = freq_mhz
439 };
440 }
441
rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t * config)442 void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
443 {
444 if (config->source == RTC_CPU_FREQ_SRC_XTAL) {
445 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
446 } else if (config->source == RTC_CPU_FREQ_SRC_PLL &&
447 s_cur_pll_freq == config->source_freq_mhz) {
448 rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
449 } else {
450 /* fallback */
451 rtc_clk_cpu_freq_set_config(config);
452 }
453 }
454
rtc_clk_cpu_freq_set_xtal(void)455 void rtc_clk_cpu_freq_set_xtal(void)
456 {
457 int freq_mhz = (int) rtc_clk_xtal_freq_get();
458
459 rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
460
461 // We don't turn off the bbpll if some consumers only depends on bbpll
462 if (!rtc_clk_set_bbpll_always_on()) {
463 rtc_clk_bbpll_disable();
464 }
465 }
466
467 /**
468 * Switch to XTAL frequency. Does not disable the PLL.
469 */
rtc_clk_cpu_freq_to_xtal(int freq,int div)470 void rtc_clk_cpu_freq_to_xtal(int freq, int div)
471 {
472 ets_update_cpu_frequency(freq);
473 /* set digital voltage for different cpu freq from xtal */
474 if (freq <= 2) {
475 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_2M);
476 } else {
477 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL);
478 }
479 wait_dig_dbias_valid(2);
480 /* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
481 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
482 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, div - 1);
483 /* no need to adjust the REF_TICK */
484 /* switch clock source */
485 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_XTAL);
486 rtc_clk_apb_freq_update(freq * MHZ);
487 }
488
rtc_clk_cpu_freq_to_8m(void)489 static void rtc_clk_cpu_freq_to_8m(void)
490 {
491 ets_update_cpu_frequency(8);
492 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL);
493 wait_dig_dbias_valid(2);
494 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
495 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M);
496 rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);
497 }
498
rtc_clk_xtal_freq_get(void)499 rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
500 {
501 uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
502 if (!clk_val_is_valid(xtal_freq_reg)) {
503 SOC_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value: 0x%08x", xtal_freq_reg);
504 return RTC_XTAL_FREQ_40M;
505 }
506 return reg_val_to_clk_val(xtal_freq_reg);
507 }
508
rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)509 void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
510 {
511 WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
512 }
513
rtc_clk_apb_freq_update(uint32_t apb_freq)514 void rtc_clk_apb_freq_update(uint32_t apb_freq)
515 {
516 s_apb_freq = apb_freq;
517 }
518
rtc_clk_apb_freq_get(void)519 uint32_t rtc_clk_apb_freq_get(void)
520 {
521 return s_apb_freq;
522 }
523
rtc_clk_divider_set(uint32_t div)524 void rtc_clk_divider_set(uint32_t div)
525 {
526 CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
527 REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, div);
528 SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
529 }
530
rtc_clk_8m_divider_set(uint32_t div)531 void rtc_clk_8m_divider_set(uint32_t div)
532 {
533 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
534 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, div);
535 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
536 }
537
rtc_dig_clk8m_enable(void)538 void rtc_dig_clk8m_enable(void)
539 {
540 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
541 esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
542 }
543
rtc_dig_clk8m_disable(void)544 void rtc_dig_clk8m_disable(void)
545 {
546 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
547 esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
548 }
549
rtc_clk_set_bbpll_always_on(void)550 static bool rtc_clk_set_bbpll_always_on(void)
551 {
552 /* We just keep the rtc bbpll clock on just under the case that
553 user selects the `RTC_CLOCK_BBPLL_POWER_ON_WITH_USB` as well as
554 the USB_SERIAL_JTAG is connected with PC.
555 */
556 bool is_bbpll_on = false;
557 #if CONFIG_RTC_CLOCK_BBPLL_POWER_ON_WITH_USB
558 if (usb_serial_jtag_ll_txfifo_writable() == 1) {
559 is_bbpll_on = true;
560 }
561 #endif
562 return is_bbpll_on;
563 }
564
565 /* Name used in libphy.a:phy_chip_v7.o
566 * TODO: update the library to use rtc_clk_xtal_freq_get
567 */
568 rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get")));
569
