1 /*
2 * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "esp_attr.h"
8 #include "soc/cpu.h"
9 #include "soc/soc.h"
10 #include "soc/rtc_periph.h"
11 #include "sdkconfig.h"
12
13 #include "hal/cpu_hal.h"
14 #include "hal/cpu_types.h"
15 #include "hal/mpu_hal.h"
16
17 #include "esp_cpu.h"
18
19 #include "hal/soc_hal.h"
20 #include "soc/soc_caps.h"
21
22 #include "sdkconfig.h"
23
esp_cpu_stall(int cpu_id)24 void IRAM_ATTR esp_cpu_stall(int cpu_id)
25 {
26 #if SOC_CPU_CORES_NUM > 1
27 soc_hal_stall_core(cpu_id);
28 #endif
29 }
30
esp_cpu_unstall(int cpu_id)31 void IRAM_ATTR esp_cpu_unstall(int cpu_id)
32 {
33 #if SOC_CPU_CORES_NUM > 1
34 soc_hal_unstall_core(cpu_id);
35 #endif
36 }
37
esp_cpu_reset(int cpu_id)38 void IRAM_ATTR esp_cpu_reset(int cpu_id)
39 {
40 soc_hal_reset_core(cpu_id);
41 }
42
esp_cpu_set_watchpoint(int no,void * adr,int size,int flags)43 esp_err_t IRAM_ATTR esp_cpu_set_watchpoint(int no, void *adr, int size, int flags)
44 {
45 watchpoint_trigger_t trigger;
46
47 switch (flags)
48 {
49 case ESP_WATCHPOINT_LOAD:
50 trigger = WATCHPOINT_TRIGGER_ON_RO;
51 break;
52 case ESP_WATCHPOINT_STORE:
53 trigger = WATCHPOINT_TRIGGER_ON_WO;
54 break;
55 case ESP_WATCHPOINT_ACCESS:
56 trigger = WATCHPOINT_TRIGGER_ON_RW;
57 break;
58 default:
59 return ESP_ERR_INVALID_ARG;
60 }
61
62 cpu_hal_set_watchpoint(no, adr, size, trigger);
63 return ESP_OK;
64 }
65
esp_cpu_clear_watchpoint(int no)66 void IRAM_ATTR esp_cpu_clear_watchpoint(int no)
67 {
68 cpu_hal_clear_watchpoint(no);
69 }
70
esp_cpu_in_ocd_debug_mode(void)71 bool IRAM_ATTR esp_cpu_in_ocd_debug_mode(void)
72 {
73 #if CONFIG_ESP32_DEBUG_OCDAWARE || \
74 CONFIG_ESP32S2_DEBUG_OCDAWARE || \
75 CONFIG_ESP32S3_DEBUG_OCDAWARE || \
76 CONFIG_ESP32C3_DEBUG_OCDAWARE || \
77 CONFIG_ESP32H2_DEBUG_OCDAWARE
78 return cpu_ll_is_debugger_attached();
79 #else
80 return false; // Always return false if "OCD aware" is disabled
81 #endif
82 }
83
84 #if __XTENSA__
85
esp_cpu_configure_region_protection(void)86 void esp_cpu_configure_region_protection(void)
87 {
88 /* Note: currently this is configured the same on all Xtensa targets
89 *
90 * Both chips have the address space divided into 8 regions, 512MB each.
91 */
92 const int illegal_regions[] = {0, 4, 5, 6, 7}; // 0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000
93 for (size_t i = 0; i < sizeof(illegal_regions) / sizeof(illegal_regions[0]); ++i) {
94 mpu_hal_set_region_access(illegal_regions[i], MPU_REGION_ILLEGAL);
95 }
96
97 mpu_hal_set_region_access(1, MPU_REGION_RW); // 0x20000000
98 }
99
100 #endif
101
