1menu "ESP32-specific" 2 # TODO: this component simply shouldn't be included 3 # in the build at the CMake level, but this is currently 4 # not working so we just hide all items here 5 visible if IDF_TARGET_ESP32 6 7 config ESP32_ECO3_CACHE_LOCK_FIX 8 bool 9 default y 10 depends on !FREERTOS_UNICORE && ESP32_SPIRAM_SUPPORT 11 12 choice ESP32_REV_MIN 13 prompt "Minimum Supported ESP32 Revision" 14 default ESP32_REV_MIN_0 15 help 16 Minimum revision that ESP-IDF would support. 17 ESP-IDF performs different strategy on different esp32 revision. 18 19 config ESP32_REV_MIN_0 20 bool "Rev 0" 21 config ESP32_REV_MIN_1 22 bool "Rev 1" 23 config ESP32_REV_MIN_2 24 bool "Rev 2" 25 config ESP32_REV_MIN_3 26 bool "Rev 3" 27 select ESP_INT_WDT if ESP32_ECO3_CACHE_LOCK_FIX 28 endchoice 29 30 config ESP32_REV_MIN 31 int 32 default 0 if ESP32_REV_MIN_0 33 default 1 if ESP32_REV_MIN_1 34 default 2 if ESP32_REV_MIN_2 35 default 3 if ESP32_REV_MIN_3 36 37 config ESP32_DPORT_WORKAROUND 38 bool 39 default "y" if !FREERTOS_UNICORE && ESP32_REV_MIN < 2 40 41 choice ESP32_DEFAULT_CPU_FREQ_MHZ 42 prompt "CPU frequency" 43 default ESP32_DEFAULT_CPU_FREQ_40 if IDF_ENV_FPGA 44 default ESP32_DEFAULT_CPU_FREQ_160 45 help 46 CPU frequency to be set on application startup. 47 48 config ESP32_DEFAULT_CPU_FREQ_40 49 bool "40 MHz" 50 depends on IDF_ENV_FPGA 51 config ESP32_DEFAULT_CPU_FREQ_80 52 bool "80 MHz" 53 config ESP32_DEFAULT_CPU_FREQ_160 54 bool "160 MHz" 55 config ESP32_DEFAULT_CPU_FREQ_240 56 bool "240 MHz" 57 endchoice 58 59 config ESP32_DEFAULT_CPU_FREQ_MHZ 60 int 61 default 40 if ESP32_DEFAULT_CPU_FREQ_40 62 default 80 if ESP32_DEFAULT_CPU_FREQ_80 63 default 160 if ESP32_DEFAULT_CPU_FREQ_160 64 default 240 if ESP32_DEFAULT_CPU_FREQ_240 65 66 # Note: to support SPIRAM across multiple chips, check CONFIG_SPIRAM 67 # instead 68 config ESP32_SPIRAM_SUPPORT 69 bool "Support for external, SPI-connected RAM" 70 default "n" 71 select SPIRAM 72 help 73 This enables support for an external SPI RAM chip, connected in parallel with the 74 main SPI flash chip. 75 76 menu "SPI RAM config" 77 depends on ESP32_SPIRAM_SUPPORT 78 79 choice SPIRAM_TYPE 80 prompt "Type of SPI RAM chip in use" 81 default SPIRAM_TYPE_AUTO 82 83 config SPIRAM_TYPE_AUTO 84 bool "Auto-detect" 85 86 config SPIRAM_TYPE_ESPPSRAM16 87 bool "ESP-PSRAM16 or APS1604" 88 89 config SPIRAM_TYPE_ESPPSRAM32 90 bool "ESP-PSRAM32 or IS25WP032" 91 92 config SPIRAM_TYPE_ESPPSRAM64 93 bool "ESP-PSRAM64 or LY68L6400" 94 95 endchoice 96 97 config SPIRAM_SIZE 98 int 99 default -1 if SPIRAM_TYPE_AUTO 100 default 2097152 if SPIRAM_TYPE_ESPPSRAM16 101 default 4194304 if SPIRAM_TYPE_ESPPSRAM32 102 default 8388608 if SPIRAM_TYPE_ESPPSRAM64 103 default 0 104 105 choice SPIRAM_SPEED 106 prompt "Set RAM clock speed" 107 default SPIRAM_SPEED_40M 108 help 109 Select the speed for the SPI RAM chip. 110 If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now: 111 112 1. Flash SPI running at 40Mhz and RAM SPI running at 40Mhz 113 2. Flash SPI running at 80Mhz and RAM SPI running at 40Mhz 114 3. Flash SPI running at 80Mhz and RAM SPI running at 80Mhz 115 116 Note: If the third mode(80Mhz+80Mhz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host 117 will be occupied by the system. Which SPI host to use can be selected by the config item 118 SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The 119 option to select 80MHz will only be visible if the flash SPI speed is also 80MHz. 120 (ESPTOOLPY_FLASHFREQ_80M is true) 121 122 config SPIRAM_SPEED_40M 123 bool "40MHz clock speed" 124 config SPIRAM_SPEED_80M 125 depends on ESPTOOLPY_FLASHFREQ_80M 126 bool "80MHz clock speed" 127 endchoice 128 129 # insert non-chip-specific items here 130 source "$IDF_PATH/components/esp_hw_support/Kconfig.spiram.common" 131 132 config SPIRAM_CACHE_WORKAROUND 133 bool "Enable workaround for bug in SPI RAM cache for Rev1 ESP32s" 134 depends on (SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC) && (ESP32_REV_MIN < 3) 135 default "y" 136 help 137 Revision 1 of the ESP32 has a bug that can cause a write to PSRAM not to take place in some situations 138 when the cache line needs to be fetched from external RAM and an interrupt occurs. This enables a 139 fix in the compiler (-mfix-esp32-psram-cache-issue) that makes sure the specific code that is 140 vulnerable to this will not be emitted. 141 142 This will also not use any bits of newlib that are located in ROM, opting for a version that is 143 compiled with the workaround and located in flash instead. 144 145 The workaround is not required for ESP32 revision 3 and above. 146 147 menu "SPIRAM cache workaround debugging" 148 149 choice SPIRAM_CACHE_WORKAROUND_STRATEGY 150 prompt "Workaround strategy" 151 depends on SPIRAM_CACHE_WORKAROUND 152 default SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW 153 help 154 Select the workaround strategy. Note that the strategy for precompiled 155 libraries (libgcc, newlib, bt, wifi) is not affected by this selection. 156 157 Unless you know you need a different strategy, it's suggested you stay 158 with the default MEMW strategy. Note that DUPLDST can interfere with hardware 159 encryption and this will be automatically disabled if this workaround is selected. 160 'Insert nops' is the workaround that was used in older esp-idf versions. This workaround 161 still can cause faulty data transfers from/to SPI RAM in some situation. 162 163 config SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW 164 bool "Insert memw after vulnerable instructions (default)" 165 166 config SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST 167 bool "Duplicate LD/ST for 32-bit, memw for 8/16 bit" 168 169 config SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS 170 bool "Insert nops between vulnerable loads/stores (old strategy, obsolete)" 171 endchoice 172 173 #This needs to be Y only for the dupldst workaround 174 config SPIRAM_WORKAROUND_NEED_VOLATILE_SPINLOCK 175 bool 176 default "y" if SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST 177 endmenu 178 179 menu "SPIRAM workaround libraries placement" 180 visible if SPIRAM_CACHE_WORKAROUND 181 182 config SPIRAM_CACHE_LIBJMP_IN_IRAM 183 bool "Put libc's jump related functions in IRAM" 184 depends on SPIRAM_CACHE_WORKAROUND 185 default "y" 186 help 187 The functions affected by this option are: longjmp and setjmp. 188 Putting these function in IRAM will allow them to be called when flash cache is disabled 189 but it will also reduce the available size of free IRAM for the user application. 190 191 config SPIRAM_CACHE_LIBMATH_IN_IRAM 192 bool "Put libc's math related functions in IRAM" 193 depends on SPIRAM_CACHE_WORKAROUND 194 default "y" 195 help 196 The functions affected by this option are: abs, div, labs, ldiv, quorem, fpclassify, 197 and nan. 198 Putting these function in IRAM will allow them to be called when flash cache is disabled 199 but it will also reduce the available size of free IRAM for the user application. 200 201 config SPIRAM_CACHE_LIBNUMPARSER_IN_IRAM 202 bool "Put libc's number parsing related functions in IRAM" 203 depends on SPIRAM_CACHE_WORKAROUND 204 default "y" 205 help 206 The functions affected by this option are: utoa, itoa, atoi, atol, strtol, and strtoul. 207 Putting these function in IRAM will allow them to be called when flash cache is disabled 208 but it will also reduce the available size of free IRAM for the user application. 209 210 config SPIRAM_CACHE_LIBIO_IN_IRAM 211 bool "Put libc's I/O related functions in IRAM" 212 depends on SPIRAM_CACHE_WORKAROUND 213 default "y" 214 help 215 The functions affected by this option are: wcrtomb, fvwrite, wbuf, wsetup, fputwc, wctomb_r, 216 ungetc, makebuf, fflush, refill, and sccl. 217 Putting these function in IRAM will allow them to be called when flash cache is disabled 218 but it will also reduce the available size of free IRAM for the user application. 219 220 config SPIRAM_CACHE_LIBTIME_IN_IRAM 221 bool "Put libc's time related functions in IRAM" 222 depends on SPIRAM_CACHE_WORKAROUND 223 default "y" 224 help 225 The functions affected by this option are: asctime, asctime_r, ctime, ctime_r, lcltime, lcltime_r, 226 gmtime, gmtime_r, strftime, mktime, tzset_r, tzset, time, gettzinfo, systimes, month_lengths, 227 timelocal, tzvars, tzlock, tzcalc_limits, and strptime. 228 Putting these function in IRAM will allow them to be called when flash cache is disabled 229 but it will also reduce the available size of free IRAM for the user application. 230 231 config SPIRAM_CACHE_LIBCHAR_IN_IRAM 232 bool "Put libc's characters related functions in IRAM" 233 depends on SPIRAM_CACHE_WORKAROUND 234 default "y" 235 help 236 The functions affected by this option are: ctype_, toupper, tolower, toascii, strupr, bzero, 237 isalnum, isalpha, isascii, isblank, iscntrl, isdigit, isgraph, islower, isprint, ispunct, 238 isspace, and isupper. 239 Putting these function in IRAM will allow them to be called when flash cache is disabled 240 but it will also reduce the available size of free IRAM for the user application. 241 242 config SPIRAM_CACHE_LIBMEM_IN_IRAM 243 bool "Put libc's memory related functions in IRAM" 244 depends on SPIRAM_CACHE_WORKAROUND 245 default "y" 246 help 247 The functions affected by this option are: memccpy, memchr memmove, and memrchr. 248 Putting these function in IRAM will allow them to be called when flash cache is disabled 249 but it will also reduce the available size of free IRAM for the user application. 250 251 config SPIRAM_CACHE_LIBSTR_IN_IRAM 252 bool "Put libc's string related functions in IRAM" 253 depends on SPIRAM_CACHE_WORKAROUND 254 default "y" 255 help 256 The functions affected by this option are: strcasecmp, strcasestr, strchr, strcoll, 257 strcpy, strcspn, strdup, strdup_r, strlcat, strlcpy, strlen, strlwr, strncasecmp, 258 strncat, strncmp, strncpy, strndup, strndup_r, strrchr, strsep, strspn, strstr, 259 strtok_r, and strupr. 260 Putting these function in IRAM will allow them to be called when flash cache is disabled 261 but it will also reduce the available size of free IRAM for the user application. 262 263 config SPIRAM_CACHE_LIBRAND_IN_IRAM 264 bool "Put libc's random related functions in IRAM" 265 depends on SPIRAM_CACHE_WORKAROUND 266 default "y" 267 help 268 The functions affected by this option are: srand, rand, and rand_r. 269 Putting these function in IRAM will allow them to be called when flash cache is disabled 270 but it will also reduce the available size of free IRAM for the user application. 271 272 config SPIRAM_CACHE_LIBENV_IN_IRAM 273 bool "Put libc's environment related functions in IRAM" 274 depends on SPIRAM_CACHE_WORKAROUND 275 default "y" 276 help 277 The functions affected by this option are: environ, envlock, and getenv_r. 278 Putting these function in IRAM will allow them to be called when flash cache is disabled 279 but it will also reduce the available size of free IRAM for the user application. 280 281 config SPIRAM_CACHE_LIBFILE_IN_IRAM 282 bool "Put libc's file related functions in IRAM" 283 depends on SPIRAM_CACHE_WORKAROUND 284 default "y" 285 help 286 The functions affected by this option are: lock, isatty, fclose, open, close, creat, read, 287 rshift, sbrk, stdio, syssbrk, sysclose, sysopen, creat, sysread, syswrite, impure, fwalk, 288 and findfp. 289 Putting these function in IRAM will allow them to be called when flash cache is disabled 290 but it will also reduce the available size of free IRAM for the user application. 291 292 config SPIRAM_CACHE_LIBMISC_IN_IRAM 293 bool "Put libc's miscellaneous functions in IRAM, see help" 294 depends on SPIRAM_CACHE_WORKAROUND 295 default "y" 296 help 297 The functions affected by this option are: raise and system 298 Putting these function in IRAM will allow them to be called when flash cache is disabled 299 but it will also reduce the available size of free IRAM for the user application. 300 endmenu 301 302 config SPIRAM_BANKSWITCH_ENABLE 303 bool "Enable bank switching for >4MiB external RAM" 304 default y 305 depends on SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC 306 help 307 The ESP32 only supports 4MiB of external RAM in its address space. The hardware does support larger 308 memories, but these have to be bank-switched in and out of this address space. Enabling this allows you 309 to reserve some MMU pages for this, which allows the use of the esp_himem api to manage these banks. 310 311 #Note that this is limited to 62 banks, as esp_spiram_writeback_cache needs some kind of mapping of 312 #some banks below that mark to work. We cannot at this moment guarantee this to exist when himem is 313 #enabled. 314 315 If spiram 2T mode is enabled, the size of 64Mbit psram will be changed as 32Mbit, so himem will be 316 unusable. 317 config SPIRAM_BANKSWITCH_RESERVE 318 int "Amount of 32K pages to reserve for bank switching" 319 depends on SPIRAM_BANKSWITCH_ENABLE 320 default 8 321 range 1 62 322 help 323 Select the amount of banks reserved for bank switching. Note that the amount of RAM allocatable with 324 malloc/esp_heap_alloc_caps will decrease by 32K for each page reserved here. 325 326 Note that this reservation is only actually done if your program actually uses the himem API. Without 327 any himem calls, the reservation is not done and the original amount of memory will be available 328 to malloc/esp_heap_alloc_caps. 329 330 config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY 331 bool "Allow external memory as an argument to xTaskCreateStatic" 332 default n 333 depends on SPIRAM_USE_MALLOC 334 help 335 Because some bits of the ESP32 code environment cannot be recompiled with the cache workaround, 336 normally tasks cannot be safely run with their stack residing in external memory; for this reason 337 xTaskCreate (and related task creaton functions) always allocate stack in internal memory and 338 xTaskCreateStatic will check if the memory passed to it is in internal memory. If you have a task that 339 needs a large amount of stack and does not call on ROM code in any way (no direct calls, but also no 340 Bluetooth/WiFi), you can try enable this to cause xTaskCreateStatic to allow tasks stack in external 341 memory. 342 343 choice SPIRAM_OCCUPY_SPI_HOST 344 prompt "SPI host to use for 32MBit PSRAM" 345 default SPIRAM_OCCUPY_VSPI_HOST 346 depends on SPIRAM_SPEED_80M 347 help 348 When both flash and PSRAM is working under 80MHz, and the PSRAM is of type 32MBit, one of the HSPI/VSPI 349 host will be used to output the clock. Select which one to use here. 350 351 config SPIRAM_OCCUPY_HSPI_HOST 352 bool "HSPI host (SPI2)" 353 config SPIRAM_OCCUPY_VSPI_HOST 354 bool "VSPI host (SPI3)" 355 config SPIRAM_OCCUPY_NO_HOST 356 bool "Will not try to use any host, will abort if not able to use the PSRAM" 357 358 endchoice 359 360 menu "PSRAM clock and cs IO for ESP32-DOWD" 361 362 config D0WD_PSRAM_CLK_IO 363 int "PSRAM CLK IO number" 364 depends on ESP32_SPIRAM_SUPPORT 365 range 0 33 366 default 17 367 help 368 The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use 369 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. 370 371 config D0WD_PSRAM_CS_IO 372 int "PSRAM CS IO number" 373 depends on ESP32_SPIRAM_SUPPORT 374 range 0 33 375 default 16 376 help 377 The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use 378 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. 379 endmenu 380 381 menu "PSRAM clock and cs IO for ESP32-D2WD" 382 383 config D2WD_PSRAM_CLK_IO 384 int "PSRAM CLK IO number" 385 depends on ESP32_SPIRAM_SUPPORT 386 range 0 33 387 default 9 388 help 389 User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, 390 so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. 391 392 config D2WD_PSRAM_CS_IO 393 int "PSRAM CS IO number" 394 depends on ESP32_SPIRAM_SUPPORT 395 range 0 33 396 default 10 397 help 398 User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, 399 so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. 400 endmenu 401 402 menu "PSRAM clock and cs IO for ESP32-PICO" 403 404 config PICO_PSRAM_CS_IO 405 int "PSRAM CS IO number" 406 depends on ESP32_SPIRAM_SUPPORT 407 range 0 33 408 default 10 409 help 410 The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. 411 412 For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock 413 IO. 414 For the reference hardware design, please refer to 415 https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf 416 417 endmenu 418 419 config SPIRAM_CUSTOM_SPIWP_SD3_PIN 420 bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)" 421 depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT) 422 default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5 423 default n 424 help 425 This setting is only used if the SPI flash pins have been overridden by setting the eFuses 426 SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT. 427 428 When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka 429 ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI 430 mode, so a WP pin setting is necessary. 431 432 If this config item is set to N (default), the correct WP pin will be automatically used for any 433 Espressif chip or module with integrated flash. If a custom setting is needed, set this config item 434 to Y and specify the GPIO number connected to the WP pin. 435 436 When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin 437 configured in the bootloader. 438 439 config SPIRAM_SPIWP_SD3_PIN 440 int "Custom SPI PSRAM WP(SD3) Pin" 441 depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT) 442 #depends on SPIRAM_CUSTOM_SPIWP_SD3_PIN # backwards compatibility, can uncomment in IDF 5 443 range 0 33 444 default 7 445 help 446 The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored 447 448 If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this 449 value to the GPIO number of the SPIRAM WP pin. 450 451 config SPIRAM_2T_MODE 452 bool "Enable SPI PSRAM 2T mode" 453 depends on ESP32_SPIRAM_SUPPORT 454 default "n" 455 help 456 Enable this option to fix single bit errors inside 64Mbit PSRAM. 457 458 Some 64Mbit PSRAM chips have a hardware issue in the RAM which causes bit errors at multiple 459 fixed bit positions. 460 461 Note: If this option is enabled, the 64Mbit PSRAM chip will appear to be 32Mbit in size. 462 Applications will not be affected unless the use the esp_himem APIs, which are not supported 463 in 2T mode. 464 465 endmenu # "SPI RAM config" 466 467 config ESP32_MEMMAP_TRACEMEM 468 bool 469 default "n" 470 471 config ESP32_MEMMAP_TRACEMEM_TWOBANKS 472 bool 473 default "n" 474 475 config ESP32_TRAX 476 bool "Use TRAX tracing feature" 477 default "n" 478 select ESP32_MEMMAP_TRACEMEM 479 help 480 The ESP32 contains a feature which allows you to trace the execution path the processor 481 has taken through the program. This is stored in a chunk of 32K (16K for single-processor) 482 of memory that can't be used for general purposes anymore. Disable this if you do not know 483 what this is. 484 485 config ESP32_TRAX_TWOBANKS 486 bool "Reserve memory for tracing both pro as well as app cpu execution" 487 default "n" 488 depends on ESP32_TRAX && !FREERTOS_UNICORE 489 select ESP32_MEMMAP_TRACEMEM_TWOBANKS 490 help 491 The ESP32 contains a feature which allows you to trace the execution path the processor 492 has taken through the program. This is stored in a chunk of 32K (16K for single-processor) 493 of memory that can't be used for general purposes anymore. Disable this if you do not know 494 what this is. 495 496 # Memory to reverse for trace, used in linker script 497 config ESP32_TRACEMEM_RESERVE_DRAM 498 hex 499 default 0x8000 if ESP32_MEMMAP_TRACEMEM && ESP32_MEMMAP_TRACEMEM_TWOBANKS 500 default 0x4000 if ESP32_MEMMAP_TRACEMEM && !ESP32_MEMMAP_TRACEMEM_TWOBANKS 501 default 0x0 502 503 504 505 config ESP32_ULP_COPROC_ENABLED 506 bool "Enable Ultra Low Power (ULP) Coprocessor" 507 default "n" 508 help 509 Set to 'y' if you plan to load a firmware for the coprocessor. 510 511 If this option is enabled, further coprocessor configuration will appear in the Components menu. 512 513 config ESP32_ULP_COPROC_RESERVE_MEM 514 int 515 prompt "RTC slow memory reserved for coprocessor" if ESP32_ULP_COPROC_ENABLED 516 default 512 if ESP32_ULP_COPROC_ENABLED 517 range 32 8176 if ESP32_ULP_COPROC_ENABLED 518 default 0 if !ESP32_ULP_COPROC_ENABLED 519 range 0 0 if !ESP32_ULP_COPROC_ENABLED 520 help 521 Bytes of memory to reserve for ULP coprocessor firmware & data. 522 523 Data is reserved at the beginning of RTC slow memory. 524 525 config ESP32_DEBUG_OCDAWARE 526 bool "Make exception and panic handlers JTAG/OCD aware" 527 default y 528 select FREERTOS_DEBUG_OCDAWARE 529 help 530 The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and 531 instead of panicking, have the debugger stop on the offending instruction. 532 533 config ESP32_BROWNOUT_DET 534 bool "Hardware brownout detect & reset" 535 depends on !IDF_ENV_FPGA 536 default y 537 help 538 The ESP32 has a built-in brownout detector which can detect if the voltage is lower than 539 a specific value. If this happens, it will reset the chip in order to prevent unintended 540 behaviour. 541 542 choice ESP32_BROWNOUT_DET_LVL_SEL 543 prompt "Brownout voltage level" 544 depends on ESP32_BROWNOUT_DET 545 default ESP32_BROWNOUT_DET_LVL_SEL_0 546 help 547 The brownout detector will reset the chip when the supply voltage is approximately 548 below this level. Note that there may be some variation of brownout voltage level 549 between each ESP32 chip. 550 551 #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages 552 #of the brownout threshold levels. 553 config ESP32_BROWNOUT_DET_LVL_SEL_0 554 bool "2.43V +/- 0.05" 555 config ESP32_BROWNOUT_DET_LVL_SEL_1 556 bool "2.48V +/- 0.05" 557 config ESP32_BROWNOUT_DET_LVL_SEL_2 558 bool "2.58V +/- 0.05" 559 config ESP32_BROWNOUT_DET_LVL_SEL_3 560 bool "2.62V +/- 0.05" 561 config ESP32_BROWNOUT_DET_LVL_SEL_4 562 bool "2.67V +/- 0.05" 563 config ESP32_BROWNOUT_DET_LVL_SEL_5 564 bool "2.70V +/- 0.05" 565 config ESP32_BROWNOUT_DET_LVL_SEL_6 566 bool "2.77V +/- 0.05" 567 config ESP32_BROWNOUT_DET_LVL_SEL_7 568 bool "2.80V +/- 0.05" 569 endchoice 570 571 config ESP32_BROWNOUT_DET_LVL 572 int 573 default 0 if ESP32_BROWNOUT_DET_LVL_SEL_0 574 default 1 if ESP32_BROWNOUT_DET_LVL_SEL_1 575 default 2 if ESP32_BROWNOUT_DET_LVL_SEL_2 576 default 3 if ESP32_BROWNOUT_DET_LVL_SEL_3 577 default 4 if ESP32_BROWNOUT_DET_LVL_SEL_4 578 default 5 if ESP32_BROWNOUT_DET_LVL_SEL_5 579 default 6 if ESP32_BROWNOUT_DET_LVL_SEL_6 580 default 7 if ESP32_BROWNOUT_DET_LVL_SEL_7 581 582 choice ESP32_TIME_SYSCALL 583 prompt "Timers used for gettimeofday function" 584 default ESP32_TIME_SYSCALL_USE_RTC_FRC1 585 help 586 This setting defines which hardware timers are used to 587 implement 'gettimeofday' and 'time' functions in C library. 588 589 - If both high-resolution and RTC timers are used, timekeeping will 590 continue in deep sleep. Time will be reported at 1 microsecond 591 resolution. This is the default, and the recommended option. 592 - If only high-resolution timer is used, gettimeofday will 593 provide time at microsecond resolution. 594 Time will not be preserved when going into deep sleep mode. 595 - If only RTC timer is used, timekeeping will continue in 596 deep sleep, but time will be measured at 6.(6) microsecond 597 resolution. Also the gettimeofday function itself may take 598 longer to run. 599 - If no timers are used, gettimeofday and time functions 600 return -1 and set errno to ENOSYS. 601 - When RTC is used for timekeeping, two RTC_STORE registers are 602 used to keep time in deep sleep mode. 603 604 config ESP32_TIME_SYSCALL_USE_RTC_FRC1 605 bool "RTC and high-resolution timer" 606 select ESP_TIME_FUNCS_USE_RTC_TIMER 607 select ESP_TIME_FUNCS_USE_ESP_TIMER 608 config ESP32_TIME_SYSCALL_USE_RTC 609 bool "RTC" 610 select ESP_TIME_FUNCS_USE_RTC_TIMER 611 config ESP32_TIME_SYSCALL_USE_FRC1 612 bool "High-resolution timer" 613 select ESP_TIME_FUNCS_USE_ESP_TIMER 614 config ESP32_TIME_SYSCALL_USE_NONE 615 bool "None" 616 select ESP_TIME_FUNCS_USE_NONE 617 endchoice 618 619 choice ESP32_RTC_CLK_SRC 620 prompt "RTC clock source" 621 default ESP32_RTC_CLK_SRC_INT_RC 622 help 623 Choose which clock is used as RTC clock source. 624 625 - "Internal 150kHz oscillator" option provides lowest deep sleep current 626 consumption, and does not require extra external components. However 627 frequency stability with respect to temperature is poor, so time may 628 drift in deep/light sleep modes. 629 - "External 32kHz crystal" provides better frequency stability, at the 630 expense of slightly higher (1uA) deep sleep current consumption. 631 - "External 32kHz oscillator" allows using 32kHz clock generated by an 632 external circuit. In this case, external clock signal must be connected 633 to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, 634 and <1V in case of square wave signal. Common mode voltage should be 635 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. 636 Additionally, 1nF capacitor must be connected between 32K_XP pin and 637 ground. 32K_XP pin can not be used as a GPIO in this case. 638 - "Internal 8.5MHz oscillator divided by 256" option results in higher 639 deep sleep current (by 5uA) but has better frequency stability than 640 the internal 150kHz oscillator. It does not require external components. 641 642 config ESP32_RTC_CLK_SRC_INT_RC 643 bool "Internal 150kHz RC oscillator" 644 config ESP32_RTC_CLK_SRC_EXT_CRYS 645 bool "External 32kHz crystal" 646 select ESP_SYSTEM_RTC_EXT_XTAL 647 config ESP32_RTC_CLK_SRC_EXT_OSC 648 bool "External 32kHz oscillator at 32K_XN pin" 649 select ESP_SYSTEM_RTC_EXT_OSC 650 config ESP32_RTC_CLK_SRC_INT_8MD256 651 bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)" 652 endchoice 653 654 choice ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_METHOD 655 prompt "Additional current for external 32kHz crystal" 656 depends on ESP32_RTC_CLK_SRC_EXT_CRYS 657 depends on ESP32_REV_MIN <= 1 658 default ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_NONE 659 help 660 With some 32kHz crystal configurations, the X32N and X32P pins may not have enough 661 drive strength to keep the crystal oscillating. Choose the method to provide 662 additional current from touchpad 9 to the external 32kHz crystal. Note that 663 the deep sleep current is slightly high (4-5uA) and the touchpad and the 664 wakeup sources of both touchpad and ULP are not available in method 1 and method 2. 665 666 This problem is fixed in ESP32 ECO 3, so this workaround is not needed. Setting the 667 project configuration to minimum revision ECO3 will disable this option, , allow 668 all wakeup sources, and save some code size. 669 670 - "None" option will not provide additional current to external crystal 671 - "Method 1" option can't ensure 100% to solve the external 32k crystal start failed 672 issue, but the touchpad can work in this method. 673 - "Method 2" option can solve the external 32k issue, but the touchpad can't work 674 in this method. 675 676 config ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_NONE 677 bool "None" 678 config ESP32_RTC_EXT_CRYST_ADDIT_CURRENT 679 bool "Method 1" 680 config ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2 681 bool "Method 2" 682 endchoice 683 684 config ESP32_RTC_CLK_CAL_CYCLES 685 int "Number of cycles for RTC_SLOW_CLK calibration" 686 default 3000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256 687 default 1024 if ESP32_RTC_CLK_SRC_INT_RC 688 range 0 27000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256 689 range 0 32766 if ESP32_RTC_CLK_SRC_INT_RC 690 help 691 When the startup code initializes RTC_SLOW_CLK, it can perform 692 calibration by comparing the RTC_SLOW_CLK frequency with main XTAL 693 frequency. This option sets the number of RTC_SLOW_CLK cycles measured 694 by the calibration routine. Higher numbers increase calibration 695 precision, which may be important for applications which spend a lot of 696 time in deep sleep. Lower numbers reduce startup time. 697 698 When this option is set to 0, clock calibration will not be performed at 699 startup, and approximate clock frequencies will be assumed: 700 701 - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. 702 - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. 703 In case more value will help improve the definition of the launch of the crystal. 704 If the crystal could not start, it will be switched to internal RC. 705 706 config ESP32_RTC_XTAL_CAL_RETRY 707 int "Number of attempts to repeat 32k XTAL calibration" 708 default 1 709 depends on ESP32_RTC_CLK_SRC_EXT_CRYS 710 help 711 Number of attempts to repeat 32k XTAL calibration 712 before giving up and switching to the internal RC. 713 Increase this option if the 32k crystal oscillator 714 does not start and switches to internal RC. 715 716 config ESP32_DEEP_SLEEP_WAKEUP_DELAY 717 int "Extra delay in deep sleep wake stub (in us)" 718 default 2000 719 range 0 5000 720 help 721 When ESP32 exits deep sleep, the CPU and the flash chip are powered on 722 at the same time. CPU will run deep sleep stub first, and then 723 proceed to load code from flash. Some flash chips need sufficient 724 time to pass between power on and first read operation. By default, 725 without any extra delay, this time is approximately 900us, although 726 some flash chip types need more than that. 727 728 By default extra delay is set to 2000us. When optimizing startup time 729 for applications which require it, this value may be reduced. 730 731 If you are seeing "flash read err, 1000" message printed to the 732 console after deep sleep reset, try increasing this value. 733 734 choice ESP32_XTAL_FREQ_SEL 735 prompt "Main XTAL frequency" 736 default ESP32_XTAL_FREQ_40 737 help 738 ESP32 currently supports the following XTAL frequencies: 739 740 - 26 MHz 741 - 40 MHz 742 743 Startup code can automatically estimate XTAL frequency. This feature 744 uses the internal 8MHz oscillator as a reference. Because the internal 745 oscillator frequency is temperature dependent, it is not recommended 746 to use automatic XTAL frequency detection in applications which need 747 to work at high ambient temperatures and use high-temperature 748 qualified chips and modules. 749 config ESP32_XTAL_FREQ_40 750 bool "40 MHz" 751 config ESP32_XTAL_FREQ_26 752 bool "26 MHz" 753 config ESP32_XTAL_FREQ_AUTO 754 bool "Autodetect" 755 endchoice 756 757 # Keep these values in sync with rtc_xtal_freq_t enum in soc/rtc.h 758 config ESP32_XTAL_FREQ 759 int 760 default 0 if ESP32_XTAL_FREQ_AUTO 761 default 40 if ESP32_XTAL_FREQ_40 762 default 26 if ESP32_XTAL_FREQ_26 763 764 config ESP32_DISABLE_BASIC_ROM_CONSOLE 765 bool "Permanently disable BASIC ROM Console" 766 default n 767 help 768 If set, the first time the app boots it will disable the BASIC ROM Console 769 permanently (by burning an eFuse). 770 771 Otherwise, the BASIC ROM Console starts on reset if no valid bootloader is 772 read from the flash. 773 774 (Enabling secure boot also disables the BASIC ROM Console by default.) 775 776 config ESP32_NO_BLOBS 777 bool "No Binary Blobs" 778 depends on !BT_ENABLED 779 default n 780 help 781 If enabled, this disables the linking of binary libraries in the application build. Note 782 that after enabling this Wi-Fi/Bluetooth will not work. 783 784 config ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS 785 bool "App compatible with bootloaders before ESP-IDF v2.1" 786 select ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS 787 default n 788 help 789 Bootloaders before ESP-IDF v2.1 did less initialisation of the 790 system clock. This setting needs to be enabled to build an app 791 which can be booted by these older bootloaders. 792 793 If this setting is enabled, the app can be booted by any bootloader 794 from IDF v1.0 up to the current version. 795 796 If this setting is disabled, the app can only be booted by bootloaders 797 from IDF v2.1 or newer. 798 799 Enabling this setting adds approximately 1KB to the app's IRAM usage. 800 801 config ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS 802 bool "App compatible with bootloader and partition table before ESP-IDF v3.1" 803 default n 804 help 805 Partition tables before ESP-IDF V3.1 do not contain an MD5 checksum 806 field, and the bootloader before ESP-IDF v3.1 cannot read a partition 807 table that contains an MD5 checksum field. 808 809 Enable this option only if your app needs to boot on a bootloader and/or 810 partition table that was generated from a version *before* ESP-IDF v3.1. 811 812 If this option and Flash Encryption are enabled at the same time, and any 813 data partitions in the partition table are marked Encrypted, then the 814 partition encrypted flag should be manually verified in the app before accessing 815 the partition (see CVE-2021-27926). 816 817 config ESP32_APP_INIT_CLK 818 bool 819 default y if ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS 820 default y if APP_BUILD_TYPE_ELF_RAM 821 822 config ESP32_RTCDATA_IN_FAST_MEM 823 bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment" 824 default n 825 depends on FREERTOS_UNICORE 826 help 827 This option allows to place .rtc_data and .rtc_rodata sections into 828 RTC fast memory segment to free the slow memory region for ULP programs. 829 This option depends on the CONFIG_FREERTOS_UNICORE option because RTC fast memory 830 can be accessed only by PRO_CPU core. 831 832 config ESP32_USE_FIXED_STATIC_RAM_SIZE 833 bool "Use fixed static RAM size" 834 default n 835 help 836 If this option is disabled, the DRAM part of the heap starts right after the .bss section, 837 within the dram0_0 region. As a result, adding or removing some static variables 838 will change the available heap size. 839 840 If this option is enabled, the DRAM part of the heap starts right after the dram0_0 region, 841 where its length is set with ESP32_FIXED_STATIC_RAM_SIZE 842 843 config ESP32_FIXED_STATIC_RAM_SIZE 844 hex "Fixed Static RAM size" 845 default 0x1E000 846 range 0 0x2c200 847 depends on ESP32_USE_FIXED_STATIC_RAM_SIZE 848 help 849 RAM size dedicated for static variables (.data & .bss sections). 850 Please note that the actual length will be reduced by BTDM_RESERVE_DRAM if Bluetooth 851 controller is enabled. 852 853 config ESP32_DPORT_DIS_INTERRUPT_LVL 854 int "Disable the interrupt level for the DPORT workarounds" 855 default 5 856 help 857 To prevent interrupting DPORT workarounds, 858 need to disable interrupt with a maximum used level in the system. 859 860 config ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY 861 bool "Enable IRAM as 8 bit accessible memory" 862 depends on FREERTOS_UNICORE 863 help 864 If enabled, application can use IRAM as byte accessible region for storing data 865 (Note: IRAM region cannot be used as task stack) 866 867 This is possible due to handling of exceptions `LoadStoreError (3)` and `LoadStoreAlignmentError (9)` 868 Each unaligned read/write access will incur a penalty of maximum of 167 CPU cycles. 869 870endmenu # ESP32-Specific 871
