1 /*
2 * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdlib.h>
8 #include <stdbool.h>
9 #include <string.h>
10 #include <sys/param.h>
11
12 #include "esp_attr.h"
13 #include "esp_err.h"
14 #include "esp_pm.h"
15 #include "esp_log.h"
16
17 #include "esp_private/crosscore_int.h"
18
19 #include "soc/rtc.h"
20 #include "hal/cpu_hal.h"
21 #include "hal/uart_ll.h"
22 #include "hal/uart_types.h"
23
24 #if !defined(__ZEPHYR__)
25 #include "freertos/FreeRTOS.h"
26 #include "freertos/task.h"
27 #if CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
28 #include "freertos/xtensa_timer.h"
29 #include "xtensa/core-macros.h"
30 #endif
31 #else
32 #include <zephyr/kernel.h>
33 #include "stubs.h"
34 #endif //__ZEPHYR__
35
36 #include "esp_private/pm_impl.h"
37 #include "esp_private/pm_trace.h"
38 #include "esp_private/esp_timer_private.h"
39
40 #include "esp_sleep.h"
41
42 #include "sdkconfig.h"
43
44 // [refactor-todo] opportunity for further refactor
45 #if CONFIG_IDF_TARGET_ESP32
46 #include "esp32/clk.h"
47 #include "esp32/pm.h"
48 #include "driver/gpio.h"
49 #elif CONFIG_IDF_TARGET_ESP32S2
50 #include "esp32s2/clk.h"
51 #include "esp32s2/pm.h"
52 #include "driver/gpio.h"
53 #elif CONFIG_IDF_TARGET_ESP32S3
54 #include "esp32s3/clk.h"
55 #include "esp32s3/pm.h"
56 #elif CONFIG_IDF_TARGET_ESP32C3
57 #include "esp32c3/clk.h"
58 #include "esp32c3/pm.h"
59 #include "driver/gpio.h"
60 #elif CONFIG_IDF_TARGET_ESP32H2
61 #include "esp32h2/clk.h"
62 #include "esp32h2/pm.h"
63 #include "driver/gpio.h"
64 #endif
65
66 #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
67 /* CCOMPARE update timeout, in CPU cycles. Any value above ~600 cycles will work
68 * for the purpose of detecting a deadlock.
69 */
70 #define CCOMPARE_UPDATE_TIMEOUT 1000000
71
72 /* When changing CCOMPARE, don't allow changes if the difference is less
73 * than this. This is to prevent setting CCOMPARE below CCOUNT.
74 */
75 #define CCOMPARE_MIN_CYCLES_IN_FUTURE 1000
76 #endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
77
78 /* When light sleep is used, wake this number of microseconds earlier than
79 * the next tick.
80 */
81 #define LIGHT_SLEEP_EARLY_WAKEUP_US 100
82
83 #define DEFAULT_CPU_FREQ ESP_SOC_DEFAULT_CPU_FREQ_MHZ
84
85 #if CONFIG_IDF_TARGET_ESP32
86 /* Minimal divider at which REF_CLK_FREQ can be obtained */
87 #define REF_CLK_DIV_MIN 10
88 #elif CONFIG_IDF_TARGET_ESP32S2
89 /* Minimal divider at which REF_CLK_FREQ can be obtained */
90 #define REF_CLK_DIV_MIN 2
91 #elif CONFIG_IDF_TARGET_ESP32S3
92 /* Minimal divider at which REF_CLK_FREQ can be obtained */
93 #define REF_CLK_DIV_MIN 2
94 #define DEFAULT_CPU_FREQ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
95 #elif CONFIG_IDF_TARGET_ESP32C3
96 #define REF_CLK_DIV_MIN 2
97 #elif CONFIG_IDF_TARGET_ESP32H2
98 #define REF_CLK_DIV_MIN 2
99 #define DEFAULT_CPU_FREQ CONFIG_ESP32H2_DEFAULT_CPU_FREQ_MHZ
100 #endif
101
102 #ifdef CONFIG_PM_PROFILING
103 #define WITH_PROFILING
104 #endif
105
106 static int s_switch_lock;
107 /* The following state variables are protected using s_switch_lock: */
108 /* Current sleep mode; When switching, contains old mode until switch is complete */
109 static pm_mode_t s_mode = PM_MODE_CPU_MAX;
110 /* True when switch is in progress */
111 static volatile bool s_is_switching;
112 /* Number of times each mode was locked */
113 static size_t s_mode_lock_counts[PM_MODE_COUNT];
114 /* Bit mask of locked modes. BIT(i) is set iff s_mode_lock_counts[i] > 0. */
115 static uint32_t s_mode_mask;
116
117 #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
118
119 #define PERIPH_SKIP_LIGHT_SLEEP_NO 1
120
121 /* Indicates if light sleep shoule be skipped by peripherals. */
122 static skip_light_sleep_cb_t s_periph_skip_light_sleep_cb[PERIPH_SKIP_LIGHT_SLEEP_NO];
123
124 /* Indicates if light sleep entry was skipped in vApplicationSleep for given CPU.
125 * This in turn gets used in IDLE hook to decide if `waiti` needs
126 * to be invoked or not.
127 */
128 static bool s_skipped_light_sleep[CONFIG_MP_NUM_CPUS];
129
130 #if CONFIG_NUM_CPUS == 2
131 /* When light sleep is finished on one CPU, it is possible that the other CPU
132 * will enter light sleep again very soon, before interrupts on the first CPU
133 * get a chance to run. To avoid such situation, set a flag for the other CPU to
134 * skip light sleep attempt.
135 */
136 static bool s_skip_light_sleep[CONFIG_MP_NUM_CPUS];
137 #endif // CONFIG_NUM_CPUS == 2
138 #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
139
140 /* A flag indicating that Idle hook has run on a given CPU;
141 * Next interrupt on the same CPU will take s_rtos_lock_handle.
142 */
143 static bool s_core_idle[CONFIG_MP_NUM_CPUS];
144
145 /* When no RTOS tasks are active, these locks are released to allow going into
146 * a lower power mode. Used by ISR hook and idle hook.
147 */
148 static esp_pm_lock_handle_t s_rtos_lock_handle[CONFIG_MP_NUM_CPUS];
149
150 /* Lookup table of CPU frequency configs to be used in each mode.
151 * Initialized by esp_pm_impl_init and modified by esp_pm_configure.
152 */
153 static rtc_cpu_freq_config_t s_cpu_freq_by_mode[PM_MODE_COUNT];
154
155 /* Whether automatic light sleep is enabled */
156 static bool s_light_sleep_en = false;
157
158 /* When configuration is changed, current frequency may not match the
159 * newly configured frequency for the current mode. This is an indicator
160 * to the mode switch code to get the actual current frequency instead of
161 * relying on the current mode.
162 */
163 static bool s_config_changed = false;
164
165 #ifdef WITH_PROFILING
166 /* Time, in microseconds, spent so far in each mode */
167 static pm_time_t s_time_in_mode[PM_MODE_COUNT];
168 /* Timestamp, in microseconds, when the mode switch last happened */
169 static pm_time_t s_last_mode_change_time;
170 /* User-readable mode names, used by esp_pm_impl_dump_stats */
171 static const char* s_mode_names[] = {
172 "SLEEP",
173 "APB_MIN",
174 "APB_MAX",
175 "CPU_MAX"
176 };
177 #endif // WITH_PROFILING
178
179 #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
180 /* Indicates to the ISR hook that CCOMPARE needs to be updated on the given CPU.
181 * Used in conjunction with cross-core interrupt to update CCOMPARE on the other CPU.
182 */
183 static volatile bool s_need_update_ccompare[CONFIG_NUM_CPUS];
184
185 /* Divider and multiplier used to adjust (ccompare - ccount) duration.
186 * Only set to non-zero values when switch is in progress.
187 */
188 static uint32_t s_ccount_div;
189 static uint32_t s_ccount_mul;
190
191 static void update_ccompare(void);
192 #endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
193
194 static const char* TAG = "pm";
195
196 static void do_switch(pm_mode_t new_mode);
197 static void on_freq_update(uint32_t old_ticks_per_us, uint32_t ticks_per_us);
198 #if CONFIG_PM_SLP_DEFAULT_PARAMS_OPT
199 static void esp_pm_light_sleep_default_params_config(int min_freq_mhz, int max_freq_mhz);
200 #endif
201 #ifdef CONFIG_IDF_TARGET_ESP32
202 extern uint32_t esp_core_id(void);
203 #define ESP_CORE_ID() esp_core_id()
204 #else
205 #define ESP_CORE_ID() 0
206 #endif
207
esp_pm_configure(const void * vconfig)208 esp_err_t esp_pm_configure(const void* vconfig)
209 {
210 #ifndef CONFIG_PM_ENABLE
211 return ESP_ERR_NOT_SUPPORTED;
212 #endif
213
214 #if CONFIG_IDF_TARGET_ESP32
215 const esp_pm_config_esp32_t* config = (const esp_pm_config_esp32_t*) vconfig;
216 #elif CONFIG_IDF_TARGET_ESP32S2
217 const esp_pm_config_esp32s2_t* config = (const esp_pm_config_esp32s2_t*) vconfig;
218 #elif CONFIG_IDF_TARGET_ESP32S3
219 const esp_pm_config_esp32s3_t* config = (const esp_pm_config_esp32s3_t*) vconfig;
220 #elif CONFIG_IDF_TARGET_ESP32C3
221 const esp_pm_config_esp32c3_t* config = (const esp_pm_config_esp32c3_t*) vconfig;
222 #elif CONFIG_IDF_TARGET_ESP32H2
223 const esp_pm_config_esp32h2_t* config = (const esp_pm_config_esp32h2_t*) vconfig;
224 #endif
225
226 #ifndef CONFIG_FREERTOS_USE_TICKLESS_IDLE
227 if (config->light_sleep_enable) {
228 return ESP_ERR_NOT_SUPPORTED;
229 }
230 #endif
231
232 int min_freq_mhz = config->min_freq_mhz;
233 int max_freq_mhz = config->max_freq_mhz;
234
235 if (min_freq_mhz > max_freq_mhz) {
236 return ESP_ERR_INVALID_ARG;
237 }
238
239 rtc_cpu_freq_config_t freq_config;
240 if (!rtc_clk_cpu_freq_mhz_to_config(min_freq_mhz, &freq_config)) {
241 ESP_LOGW(TAG, "invalid min_freq_mhz value (%d)", min_freq_mhz);
242 return ESP_ERR_INVALID_ARG;
243 }
244
245 int xtal_freq_mhz = (int) rtc_clk_xtal_freq_get();
246 if (min_freq_mhz < xtal_freq_mhz && MHZ(min_freq_mhz) / REF_CLK_FREQ < REF_CLK_DIV_MIN) {
247 ESP_LOGW(TAG, "min_freq_mhz should be >= %d", REF_CLK_FREQ * REF_CLK_DIV_MIN / MHZ(1));
248 return ESP_ERR_INVALID_ARG;
249 }
250
251 if (!rtc_clk_cpu_freq_mhz_to_config(max_freq_mhz, &freq_config)) {
252 ESP_LOGW(TAG, "invalid max_freq_mhz value (%d)", max_freq_mhz);
253 return ESP_ERR_INVALID_ARG;
254 }
255
256 #if CONFIG_IDF_TARGET_ESP32
257 int apb_max_freq = max_freq_mhz; /* CPU frequency in APB_MAX mode */
258 if (max_freq_mhz == 240) {
259 /* We can't switch between 240 and 80/160 without disabling PLL,
260 * so use 240MHz CPU frequency when 80MHz APB frequency is requested.
261 */
262 apb_max_freq = 240;
263 } else if (max_freq_mhz == 160 || max_freq_mhz == 80) {
264 /* Otherwise, can use 80MHz
265 * CPU frequency when 80MHz APB frequency is requested.
266 */
267 apb_max_freq = 80;
268 }
269 #else
270 int apb_max_freq = MIN(max_freq_mhz, 80); /* CPU frequency in APB_MAX mode */
271 #endif
272
273 apb_max_freq = MAX(apb_max_freq, min_freq_mhz);
274
275 ESP_LOGI(TAG, "Frequency switching config: "
276 "CPU_MAX: %d, APB_MAX: %d, APB_MIN: %d, Light sleep: %s",
277 max_freq_mhz,
278 apb_max_freq,
279 min_freq_mhz,
280 config->light_sleep_enable ? "ENABLED" : "DISABLED");
281 s_switch_lock = irq_lock();
282
283 bool res __attribute__((unused));
284 res = rtc_clk_cpu_freq_mhz_to_config(max_freq_mhz, &s_cpu_freq_by_mode[PM_MODE_CPU_MAX]);
285 assert(res);
286 res = rtc_clk_cpu_freq_mhz_to_config(apb_max_freq, &s_cpu_freq_by_mode[PM_MODE_APB_MAX]);
287 assert(res);
288 res = rtc_clk_cpu_freq_mhz_to_config(min_freq_mhz, &s_cpu_freq_by_mode[PM_MODE_APB_MIN]);
289 assert(res);
290 s_cpu_freq_by_mode[PM_MODE_LIGHT_SLEEP] = s_cpu_freq_by_mode[PM_MODE_APB_MIN];
291 s_light_sleep_en = config->light_sleep_enable;
292 s_config_changed = true;
293 irq_unlock(s_switch_lock);
294
295 #if CONFIG_PM_SLP_DISABLE_GPIO && SOC_GPIO_SUPPORT_SLP_SWITCH
296 esp_sleep_enable_gpio_switch(config->light_sleep_enable);
297 #endif
298
299 #if CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP && SOC_PM_SUPPORT_CPU_PD
300 esp_err_t ret = esp_sleep_cpu_pd_low_init(config->light_sleep_enable);
301 if (config->light_sleep_enable && ret != ESP_OK) {
302 ESP_LOGW(TAG, "Failed to enable CPU power down during light sleep.");
303 }
304 #endif
305
306 #if CONFIG_PM_SLP_DEFAULT_PARAMS_OPT
307 if (config->light_sleep_enable) {
308 esp_pm_light_sleep_default_params_config(min_freq_mhz, max_freq_mhz);
309 }
310 #endif
311
312 return ESP_OK;
313 }
314
esp_pm_get_configuration(void * vconfig)315 esp_err_t esp_pm_get_configuration(void* vconfig)
316 {
317 if (vconfig == NULL) {
318 return ESP_ERR_INVALID_ARG;
319 }
320
321 #if CONFIG_IDF_TARGET_ESP32
322 esp_pm_config_esp32_t* config = (esp_pm_config_esp32_t*) vconfig;
323 #elif CONFIG_IDF_TARGET_ESP32S2
324 esp_pm_config_esp32s2_t* config = (esp_pm_config_esp32s2_t*) vconfig;
325 #elif CONFIG_IDF_TARGET_ESP32S3
326 esp_pm_config_esp32s3_t* config = (esp_pm_config_esp32s3_t*) vconfig;
327 #elif CONFIG_IDF_TARGET_ESP32C3
328 esp_pm_config_esp32c3_t* config = (esp_pm_config_esp32c3_t*) vconfig;
329 #elif CONFIG_IDF_TARGET_ESP32H2
330 esp_pm_config_esp32h2_t* config = (esp_pm_config_esp32h2_t*) vconfig;
331 #endif
332
333 s_switch_lock = irq_lock();
334 config->light_sleep_enable = s_light_sleep_en;
335 config->max_freq_mhz = s_cpu_freq_by_mode[PM_MODE_CPU_MAX].freq_mhz;
336 config->min_freq_mhz = s_cpu_freq_by_mode[PM_MODE_APB_MIN].freq_mhz;
337 irq_unlock(s_switch_lock);
338
339 return ESP_OK;
340 }
341
get_lowest_allowed_mode(void)342 static pm_mode_t IRAM_ATTR get_lowest_allowed_mode(void)
343 {
344 /* TODO: optimize using ffs/clz */
345 if (s_mode_mask >= BIT(PM_MODE_CPU_MAX)) {
346 return PM_MODE_CPU_MAX;
347 } else if (s_mode_mask >= BIT(PM_MODE_APB_MAX)) {
348 return PM_MODE_APB_MAX;
349 } else if (s_mode_mask >= BIT(PM_MODE_APB_MIN) || !s_light_sleep_en) {
350 return PM_MODE_APB_MIN;
351 } else {
352 return PM_MODE_LIGHT_SLEEP;
353 }
354 }
355
esp_pm_impl_switch_mode(pm_mode_t mode,pm_mode_switch_t lock_or_unlock,pm_time_t now)356 void IRAM_ATTR esp_pm_impl_switch_mode(pm_mode_t mode,
357 pm_mode_switch_t lock_or_unlock, pm_time_t now)
358 {
359 bool need_switch = false;
360 uint32_t mode_mask = BIT(mode);
361 s_switch_lock = irq_lock();
362 uint32_t count;
363 if (lock_or_unlock == MODE_LOCK) {
364 count = ++s_mode_lock_counts[mode];
365 } else {
366 count = s_mode_lock_counts[mode]--;
367 }
368 if (count == 1) {
369 if (lock_or_unlock == MODE_LOCK) {
370 s_mode_mask |= mode_mask;
371 } else {
372 s_mode_mask &= ~mode_mask;
373 }
374 need_switch = true;
375 }
376
377 pm_mode_t new_mode = s_mode;
378 if (need_switch) {
379 new_mode = get_lowest_allowed_mode();
380 #ifdef WITH_PROFILING
381 if (s_last_mode_change_time != 0) {
382 pm_time_t diff = now - s_last_mode_change_time;
383 s_time_in_mode[s_mode] += diff;
384 }
385 s_last_mode_change_time = now;
386 #endif // WITH_PROFILING
387 }
388 irq_unlock(s_switch_lock);
389 if (need_switch) {
390 do_switch(new_mode);
391 }
392 }
393
394 /**
395 * @brief Update clock dividers in esp_timer and FreeRTOS, and adjust CCOMPARE
396 * values on both CPUs.
397 * @param old_ticks_per_us old CPU frequency
398 * @param ticks_per_us new CPU frequency
399 */
on_freq_update(uint32_t old_ticks_per_us,uint32_t ticks_per_us)400 static void IRAM_ATTR on_freq_update(uint32_t old_ticks_per_us, uint32_t ticks_per_us)
401 {
402 uint32_t old_apb_ticks_per_us = MIN(old_ticks_per_us, 80);
403 uint32_t apb_ticks_per_us = MIN(ticks_per_us, 80);
404 /* Update APB frequency value used by the timer */
405 if (old_apb_ticks_per_us != apb_ticks_per_us) {
406 esp_timer_private_update_apb_freq(apb_ticks_per_us);
407 }
408
409 #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
410 #ifdef XT_RTOS_TIMER_INT
411 /* Calculate new tick divisor */
412 _xt_tick_divisor = MHZ(ticks_per_us) / XT_TICK_PER_SEC;
413 #endif
414
415 int core_id = ESP_CORE_ID();
416 if (s_rtos_lock_handle[core_id] != NULL) {
417 ESP_PM_TRACE_ENTER(CCOMPARE_UPDATE, core_id);
418 /* ccount_div and ccount_mul are used in esp_pm_impl_update_ccompare
419 * to calculate new CCOMPARE value.
420 */
421 s_ccount_div = old_ticks_per_us;
422 s_ccount_mul = ticks_per_us;
423
424 /* Update CCOMPARE value on this CPU */
425 update_ccompare();
426
427 #if CONFIG_NUM_CPUS == 2
428 /* Send interrupt to the other CPU to update CCOMPARE value */
429 int other_core_id = (core_id == 0) ? 1 : 0;
430
431 s_need_update_ccompare[other_core_id] = true;
432 esp_crosscore_int_send_freq_switch(other_core_id);
433
434 int timeout = 0;
435 while (s_need_update_ccompare[other_core_id]) {
436 if (++timeout == CCOMPARE_UPDATE_TIMEOUT) {
437 assert(false && "failed to update CCOMPARE, possible deadlock");
438 }
439 }
440 #endif // CONFIG_NUM_CPUS == 2
441
442 s_ccount_mul = 0;
443 s_ccount_div = 0;
444 ESP_PM_TRACE_EXIT(CCOMPARE_UPDATE, core_id);
445 }
446 #endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
447 }
448
449 /**
450 * Perform the switch to new power mode.
451 * Currently only changes the CPU frequency and adjusts clock dividers.
452 * No light sleep yet.
453 * @param new_mode mode to switch to
454 */
do_switch(pm_mode_t new_mode)455 static void IRAM_ATTR do_switch(pm_mode_t new_mode)
456 {
457 const int core_id = ESP_CORE_ID();
458
459 do {
460 s_switch_lock = irq_lock();
461 if (!s_is_switching) {
462 break;
463 }
464 #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
465 if (s_need_update_ccompare[core_id]) {
466 s_need_update_ccompare[core_id] = false;
467 }
468 #endif
469 irq_unlock(s_switch_lock);
470 } while (true);
471 if (new_mode == s_mode) {
472 irq_unlock(s_switch_lock);
473 return;
474 }
475 s_is_switching = true;
476 bool config_changed = s_config_changed;
477 s_config_changed = false;
478 irq_unlock(s_switch_lock);
479
480 rtc_cpu_freq_config_t new_config = s_cpu_freq_by_mode[new_mode];
481 rtc_cpu_freq_config_t old_config;
482
483 if (!config_changed) {
484 old_config = s_cpu_freq_by_mode[s_mode];
485 } else {
486 rtc_clk_cpu_freq_get_config(&old_config);
487 }
488
489 if (new_config.freq_mhz != old_config.freq_mhz) {
490 uint32_t old_ticks_per_us = old_config.freq_mhz;
491 uint32_t new_ticks_per_us = new_config.freq_mhz;
492
493 bool switch_down = new_ticks_per_us < old_ticks_per_us;
494
495 ESP_PM_TRACE_ENTER(FREQ_SWITCH, core_id);
496 if (switch_down) {
497 on_freq_update(old_ticks_per_us, new_ticks_per_us);
498 }
499 rtc_clk_cpu_freq_set_config_fast(&new_config);
500 if (!switch_down) {
501 on_freq_update(old_ticks_per_us, new_ticks_per_us);
502 }
503 ESP_PM_TRACE_EXIT(FREQ_SWITCH, core_id);
504 }
505
506 s_switch_lock = irq_lock();
507 s_mode = new_mode;
508 s_is_switching = false;
509 irq_unlock(s_switch_lock);
510 }
511
512 #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
513 /**
514 * @brief Calculate new CCOMPARE value based on s_ccount_{mul,div}
515 *
516 * Adjusts CCOMPARE value so that the interrupt happens at the same time as it
517 * would happen without the frequency change.
518 * Assumes that the new_frequency = old_frequency * s_ccount_mul / s_ccount_div.
519 */
update_ccompare(void)520 static void IRAM_ATTR update_ccompare(void)
521 {
522 #if CONFIG_PM_UPDATE_CCOMPARE_HLI_WORKAROUND
523 /* disable level 4 and below */
524 uint32_t irq_status = XTOS_SET_INTLEVEL(XCHAL_DEBUGLEVEL - 2);
525 #endif
526 uint32_t ccount = cpu_hal_get_cycle_count();
527 uint32_t ccompare = XTHAL_GET_CCOMPARE(XT_TIMER_INDEX);
528 if ((ccompare - CCOMPARE_MIN_CYCLES_IN_FUTURE) - ccount < UINT32_MAX / 2) {
529 uint32_t diff = ccompare - ccount;
530 uint32_t diff_scaled = (diff * s_ccount_mul + s_ccount_div - 1) / s_ccount_div;
531 if (diff_scaled < _xt_tick_divisor) {
532 uint32_t new_ccompare = ccount + diff_scaled;
533 XTHAL_SET_CCOMPARE(XT_TIMER_INDEX, new_ccompare);
534 }
535 }
536 #if CONFIG_PM_UPDATE_CCOMPARE_HLI_WORKAROUND
537 XTOS_RESTORE_INTLEVEL(irq_status);
538 #endif
539 }
540 #endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
541
542 #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
543
esp_pm_register_skip_light_sleep_callback(skip_light_sleep_cb_t cb)544 esp_err_t esp_pm_register_skip_light_sleep_callback(skip_light_sleep_cb_t cb)
545 {
546 for (int i = 0; i < PERIPH_SKIP_LIGHT_SLEEP_NO; i++) {
547 if (s_periph_skip_light_sleep_cb[i] == cb) {
548 return ESP_OK;
549 } else if (s_periph_skip_light_sleep_cb[i] == NULL) {
550 s_periph_skip_light_sleep_cb[i] = cb;
551 return ESP_OK;
552 }
553 }
554 return ESP_ERR_NO_MEM;
555 }
556
esp_pm_unregister_skip_light_sleep_callback(skip_light_sleep_cb_t cb)557 esp_err_t esp_pm_unregister_skip_light_sleep_callback(skip_light_sleep_cb_t cb)
558 {
559 for (int i = 0; i < PERIPH_SKIP_LIGHT_SLEEP_NO; i++) {
560 if (s_periph_skip_light_sleep_cb[i] == cb) {
561 s_periph_skip_light_sleep_cb[i] = NULL;
562 return ESP_OK;
563 }
564 }
565 return ESP_ERR_INVALID_STATE;
566 }
567
periph_should_skip_light_sleep(void)568 static inline bool IRAM_ATTR periph_should_skip_light_sleep(void)
569 {
570 if (s_light_sleep_en) {
571 for (int i = 0; i < PERIPH_SKIP_LIGHT_SLEEP_NO; i++) {
572 if (s_periph_skip_light_sleep_cb[i]) {
573 if (s_periph_skip_light_sleep_cb[i]() == true) {
574 return true;
575 }
576 }
577 }
578 }
579 return false;
580 }
581
should_skip_light_sleep(int core_id)582 static inline bool IRAM_ATTR should_skip_light_sleep(int core_id)
583 {
584 #if portNUM_PROCESSORS == 2
585 if (s_skip_light_sleep[core_id]) {
586 s_skip_light_sleep[core_id] = false;
587 s_skipped_light_sleep[core_id] = true;
588 return true;
589 }
590 #endif // portNUM_PROCESSORS == 2
591
592 if (s_mode != PM_MODE_LIGHT_SLEEP || s_is_switching || periph_should_skip_light_sleep()) {
593 s_skipped_light_sleep[core_id] = true;
594 } else {
595 s_skipped_light_sleep[core_id] = false;
596 }
597 return s_skipped_light_sleep[core_id];
598 }
599
other_core_should_skip_light_sleep(int core_id)600 static inline void IRAM_ATTR other_core_should_skip_light_sleep(int core_id)
601 {
602 #if portNUM_PROCESSORS == 2
603 s_skip_light_sleep[!core_id] = true;
604 #endif
605 }
606
vApplicationSleep(TickType_t xExpectedIdleTime)607 void IRAM_ATTR vApplicationSleep( TickType_t xExpectedIdleTime )
608 {
609 s_switch_lock = irq_lock();
610 int core_id = ESP_CORE_ID();
611 if (!should_skip_light_sleep(core_id)) {
612 /* Calculate how much we can sleep */
613 int64_t next_esp_timer_alarm = esp_timer_get_next_alarm_for_wake_up();
614 int64_t now = esp_timer_get_time();
615 int64_t time_until_next_alarm = next_esp_timer_alarm - now;
616 int64_t wakeup_delay_us = portTICK_PERIOD_MS * 1000LL * xExpectedIdleTime;
617 int64_t sleep_time_us = MIN(wakeup_delay_us, time_until_next_alarm);
618 if (sleep_time_us >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP * portTICK_PERIOD_MS * 1000LL) {
619 esp_sleep_enable_timer_wakeup(sleep_time_us - LIGHT_SLEEP_EARLY_WAKEUP_US);
620 #ifdef CONFIG_PM_TRACE
621 /* to force tracing GPIOs to keep state */
622 esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
623 #endif
624 /* Enter sleep */
625 ESP_PM_TRACE_ENTER(SLEEP, core_id);
626 int64_t sleep_start = esp_timer_get_time();
627 esp_light_sleep_start();
628 int64_t slept_us = esp_timer_get_time() - sleep_start;
629 ESP_PM_TRACE_EXIT(SLEEP, core_id);
630
631 uint32_t slept_ticks = slept_us / (portTICK_PERIOD_MS * 1000LL);
632 if (slept_ticks > 0) {
633 /* Adjust RTOS tick count based on the amount of time spent in sleep */
634 vTaskStepTick(slept_ticks);
635
636 #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
637 /* Trigger tick interrupt, since sleep time was longer
638 * than portTICK_PERIOD_MS. Note that setting INTSET does not
639 * work for timer interrupt, and changing CCOMPARE would clear
640 * the interrupt flag.
641 */
642 cpu_hal_set_cycle_count(XTHAL_GET_CCOMPARE(XT_TIMER_INDEX) - 16);
643 while (!(XTHAL_GET_INTERRUPT() & BIT(XT_TIMER_INTNUM))) {
644 ;
645 }
646 #else
647 portYIELD_WITHIN_API();
648 #endif
649 }
650 other_core_should_skip_light_sleep(core_id);
651 }
652 }
653 irq_unlock(s_switch_lock);
654 }
655 #endif //CONFIG_FREERTOS_USE_TICKLESS_IDLE
656
657 #ifdef WITH_PROFILING
esp_pm_impl_dump_stats(FILE * out)658 void esp_pm_impl_dump_stats(FILE* out)
659 {
660 pm_time_t time_in_mode[PM_MODE_COUNT];
661
662 s_switch_lock = irq_lock();
663 memcpy(time_in_mode, s_time_in_mode, sizeof(time_in_mode));
664 pm_time_t last_mode_change_time = s_last_mode_change_time;
665 pm_mode_t cur_mode = s_mode;
666 pm_time_t now = pm_get_time();
667 irq_unlock(s_switch_lock);
668
669 time_in_mode[cur_mode] += now - last_mode_change_time;
670
671 fprintf(out, "\nMode stats:\n");
672 fprintf(out, "%-8s %-10s %-10s %-10s\n", "Mode", "CPU_freq", "Time(us)", "Time(%)");
673 for (int i = 0; i < PM_MODE_COUNT; ++i) {
674 if (i == PM_MODE_LIGHT_SLEEP && !s_light_sleep_en) {
675 /* don't display light sleep mode if it's not enabled */
676 continue;
677 }
678 fprintf(out, "%-8s %-3dM%-7s %-10lld %-2d%%\n",
679 s_mode_names[i],
680 s_cpu_freq_by_mode[i].freq_mhz,
681 "", //Empty space to align columns
682 time_in_mode[i],
683 (int) (time_in_mode[i] * 100 / now));
684 }
685 }
686 #endif // WITH_PROFILING
687
esp_pm_impl_get_cpu_freq(pm_mode_t mode)688 int esp_pm_impl_get_cpu_freq(pm_mode_t mode)
689 {
690 int freq_mhz = 0;
691 if (mode >= PM_MODE_LIGHT_SLEEP && mode < PM_MODE_COUNT) {
692 s_switch_lock = irq_lock();
693 freq_mhz = s_cpu_freq_by_mode[mode].freq_mhz;
694 irq_unlock(s_switch_lock);
695 } else {
696 abort();
697 }
698 return freq_mhz;
699 }
700
esp_pm_impl_init(void)701 void esp_pm_impl_init(void)
702 {
703 #if defined(CONFIG_ESP_CONSOLE_UART)
704 //This clock source should be a source which won't be affected by DFS
705 uint32_t clk_source;
706 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
707 clk_source = UART_SCLK_REF_TICK;
708 #else
709 clk_source = UART_SCLK_XTAL;
710 #endif
711 while(!uart_ll_is_tx_idle(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM)));
712 /* When DFS is enabled, override system setting and use REFTICK as UART clock source */
713 uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), clk_source);
714 uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE);
715 #endif // CONFIG_ESP_CONSOLE_UART
716
717 #ifdef CONFIG_PM_TRACE
718 esp_pm_trace_init();
719 #endif
720
721 #if CONFIG_PM_SLP_DISABLE_GPIO && SOC_GPIO_SUPPORT_SLP_SWITCH
722 esp_sleep_config_gpio_isolate();
723 #endif
724 ESP_ERROR_CHECK(esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "rtos0",
725 &s_rtos_lock_handle[0]));
726 ESP_ERROR_CHECK(esp_pm_lock_acquire(s_rtos_lock_handle[0]));
727
728 #if portNUM_PROCESSORS == 2
729 ESP_ERROR_CHECK(esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "rtos1",
730 &s_rtos_lock_handle[1]));
731 ESP_ERROR_CHECK(esp_pm_lock_acquire(s_rtos_lock_handle[1]));
732 #endif // portNUM_PROCESSORS == 2
733
734 /* Configure all modes to use the default CPU frequency.
735 * This will be modified later by a call to esp_pm_configure.
736 */
737 rtc_cpu_freq_config_t default_config;
738 if (!rtc_clk_cpu_freq_mhz_to_config(DEFAULT_CPU_FREQ, &default_config)) {
739 assert(false && "unsupported frequency");
740 }
741 for (size_t i = 0; i < PM_MODE_COUNT; ++i) {
742 s_cpu_freq_by_mode[i] = default_config;
743 }
744
745 #ifdef CONFIG_PM_DFS_INIT_AUTO
746 int xtal_freq = (int) rtc_clk_xtal_freq_get();
747 #if CONFIG_IDF_TARGET_ESP32
748 esp_pm_config_esp32_t cfg = {
749 #elif CONFIG_IDF_TARGET_ESP32S2
750 esp_pm_config_esp32s2_t cfg = {
751 #elif CONFIG_IDF_TARGET_ESP32S3
752 esp_pm_config_esp32s3_t cfg = {
753 #elif CONFIG_IDF_TARGET_ESP32C3
754 esp_pm_config_esp32c3_t cfg = {
755 #elif CONFIG_IDF_TARGET_ESP32H2
756 esp_pm_config_esp32h2_t cfg = {
757 #endif
758 .max_freq_mhz = DEFAULT_CPU_FREQ,
759 .min_freq_mhz = xtal_freq,
760 };
761
762 esp_pm_configure(&cfg);
763 #endif //CONFIG_PM_DFS_INIT_AUTO
764 }
765
766 void esp_pm_impl_waiti(void)
767 {
768 #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
769 int core_id = ESP_CORE_ID();
770 if (s_skipped_light_sleep[core_id]) {
771 cpu_hal_waiti();
772 /* Interrupt took the CPU out of waiti and s_rtos_lock_handle[core_id]
773 * is now taken. However since we are back to idle task, we can release
774 * the lock so that vApplicationSleep can attempt to enter light sleep.
775 */
776 esp_pm_impl_idle_hook();
777 s_skipped_light_sleep[core_id] = false;
778 }
779 #else
780 cpu_hal_waiti();
781 #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
782 }
783
784 #define PERIPH_INFORM_OUT_LIGHT_SLEEP_OVERHEAD_NO 1
785
786 /* Inform peripherals of light sleep wakeup overhead time */
787 static inform_out_light_sleep_overhead_cb_t s_periph_inform_out_light_sleep_overhead_cb[PERIPH_INFORM_OUT_LIGHT_SLEEP_OVERHEAD_NO];
788
789 esp_err_t esp_pm_register_inform_out_light_sleep_overhead_callback(inform_out_light_sleep_overhead_cb_t cb)
790 {
791 for (int i = 0; i < PERIPH_INFORM_OUT_LIGHT_SLEEP_OVERHEAD_NO; i++) {
792 if (s_periph_inform_out_light_sleep_overhead_cb[i] == cb) {
793 return ESP_OK;
794 } else if (s_periph_inform_out_light_sleep_overhead_cb[i] == NULL) {
795 s_periph_inform_out_light_sleep_overhead_cb[i] = cb;
796 return ESP_OK;
797 }
798 }
799 return ESP_ERR_NO_MEM;
800 }
801
802 esp_err_t esp_pm_unregister_inform_out_light_sleep_overhead_callback(inform_out_light_sleep_overhead_cb_t cb)
803 {
804 for (int i = 0; i < PERIPH_INFORM_OUT_LIGHT_SLEEP_OVERHEAD_NO; i++) {
805 if (s_periph_inform_out_light_sleep_overhead_cb[i] == cb) {
806 s_periph_inform_out_light_sleep_overhead_cb[i] = NULL;
807 return ESP_OK;
808 }
809 }
810 return ESP_ERR_INVALID_STATE;
811 }
812
813 void periph_inform_out_light_sleep_overhead(uint32_t out_light_sleep_time)
814 {
815 for (int i = 0; i < PERIPH_INFORM_OUT_LIGHT_SLEEP_OVERHEAD_NO; i++) {
816 if (s_periph_inform_out_light_sleep_overhead_cb[i]) {
817 s_periph_inform_out_light_sleep_overhead_cb[i](out_light_sleep_time);
818 }
819 }
820 }
821
822 static update_light_sleep_default_params_config_cb_t s_light_sleep_default_params_config_cb = NULL;
823
824 void esp_pm_register_light_sleep_default_params_config_callback(update_light_sleep_default_params_config_cb_t cb)
825 {
826 if (s_light_sleep_default_params_config_cb == NULL) {
827 s_light_sleep_default_params_config_cb = cb;
828 }
829 }
830
831 void esp_pm_unregister_light_sleep_default_params_config_callback(void)
832 {
833 if (s_light_sleep_default_params_config_cb) {
834 s_light_sleep_default_params_config_cb = NULL;
835 }
836 }
837
838 #if CONFIG_PM_SLP_DEFAULT_PARAMS_OPT
839 static void esp_pm_light_sleep_default_params_config(int min_freq_mhz, int max_freq_mhz)
840 {
841 if (s_light_sleep_default_params_config_cb) {
842 (*s_light_sleep_default_params_config_cb)(min_freq_mhz, max_freq_mhz);
843 }
844 }
845 #endif
846
