1 // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <stdlib.h>
16 #include <string.h>
17 #include <sys/param.h> // For MIN/MAX
18 #include "esp_log.h"
19 #include "spi_flash_chip_generic.h"
20 #include "spi_flash_chip_gd.h"
21 #include "spi_flash_defs.h"
22
23 #define ADDR_32BIT(addr) (addr >= (1<<24))
24
25 #define REGION_32BIT(start, len) ((start) + (len) > (1<<24))
26
27 extern esp_err_t spi_flash_chip_winbond_read(esp_flash_t *chip, void *buffer, uint32_t address, uint32_t length);
28 extern esp_err_t spi_flash_chip_winbond_page_program(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length);
29 extern esp_err_t spi_flash_chip_winbond_erase_sector(esp_flash_t *chip, uint32_t start_address);
30 extern esp_err_t spi_flash_chip_winbond_erase_block(esp_flash_t *chip, uint32_t start_address);
31
32 #define spi_flash_chip_gd_read spi_flash_chip_winbond_read
33 #define spi_flash_chip_gd_page_program spi_flash_chip_winbond_page_program
34 #define spi_flash_chip_gd_erase_sector spi_flash_chip_winbond_erase_sector
35 #define spi_flash_chip_gd_erase_block spi_flash_chip_winbond_erase_block
36
spi_flash_chip_gd_get_caps(esp_flash_t * chip)37 spi_flash_caps_t spi_flash_chip_gd_get_caps(esp_flash_t *chip)
38 {
39 spi_flash_caps_t caps_flags = 0;
40 // 32M-bits address support
41 if ((chip->chip_id & 0xFF) >= 0x19) {
42 caps_flags |= SPI_FLASH_CHIP_CAP_32MB_SUPPORT;
43 }
44 // flash-suspend is not supported
45 // flash read unique id.
46 caps_flags |= SPI_FLASH_CHIP_CAP_UNIQUE_ID;
47 return caps_flags;
48 }
49
50 #ifndef CONFIG_SPI_FLASH_ROM_IMPL
51
52 #define FLASH_ID_MASK 0xFF00
53 #define FLASH_SIZE_MASK 0xFF
54 #define GD25Q_PRODUCT_ID 0x4000
55 #define GD25LQ_PRODUCT_ID 0x6000
56
57 #define WRSR_16B_REQUIRED(chip_id) (((chip_id) & FLASH_ID_MASK) == GD25LQ_PRODUCT_ID || \
58 ((chip_id) & FLASH_SIZE_MASK) <= 0x15)
59
60 /* Driver for GD flash chip */
61
spi_flash_chip_gd_probe(esp_flash_t * chip,uint32_t flash_id)62 esp_err_t spi_flash_chip_gd_probe(esp_flash_t *chip, uint32_t flash_id)
63 {
64 /* Check manufacturer and product IDs match our desired masks */
65 const uint8_t MFG_ID = 0xC8;
66 if (flash_id >> 16 != MFG_ID) {
67 return ESP_ERR_NOT_FOUND;
68 }
69
70 uint32_t product_id = flash_id & FLASH_ID_MASK;
71 if (product_id != GD25Q_PRODUCT_ID && product_id != GD25LQ_PRODUCT_ID) {
72 return ESP_ERR_NOT_FOUND;
73 }
74
75 return ESP_OK;
76 }
77
spi_flash_chip_gd_set_io_mode(esp_flash_t * chip)78 esp_err_t spi_flash_chip_gd_set_io_mode(esp_flash_t *chip)
79 {
80 if (WRSR_16B_REQUIRED(chip->chip_id)) {
81 const uint32_t qe = 1<<9;
82 return spi_flash_common_set_io_mode(chip,
83 spi_flash_common_write_status_16b_wrsr,
84 spi_flash_common_read_status_16b_rdsr_rdsr2,
85 qe);
86 } else {
87 const uint32_t qe = 1<<1;
88 return spi_flash_common_set_io_mode(chip,
89 spi_flash_common_write_status_8b_wrsr2,
90 spi_flash_common_read_status_8b_rdsr2,
91 qe);
92 }
93 }
94
spi_flash_chip_gd_get_io_mode(esp_flash_t * chip,esp_flash_io_mode_t * out_io_mode)95 esp_err_t spi_flash_chip_gd_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
96 {
97 /* GD uses bit 1 of SR2 as Quad Enable */
98 const uint8_t BIT_QE = 1 << 1;
99 uint32_t sr;
100 esp_err_t ret = spi_flash_common_read_status_8b_rdsr2(chip, &sr);
101 if (ret == ESP_OK) {
102 *out_io_mode = ((sr & BIT_QE)? SPI_FLASH_QOUT: 0);
103 }
104 return ret;
105 }
106 #endif //CONFIG_SPI_FLASH_ROM_IMPL
107
108 static const char chip_name[] = "gd";
109
110 // The issi chip can use the functions for generic chips except from set read mode and probe,
111 // So we only replace these two functions.
112 const spi_flash_chip_t esp_flash_chip_gd = {
113 .name = chip_name,
114 .timeout = &spi_flash_chip_generic_timeout,
115 .probe = spi_flash_chip_gd_probe,
116 .reset = spi_flash_chip_generic_reset,
117 .detect_size = spi_flash_chip_generic_detect_size,
118 .erase_chip = spi_flash_chip_generic_erase_chip,
119 .erase_sector = spi_flash_chip_gd_erase_sector,
120 .erase_block = spi_flash_chip_gd_erase_block,
121 .sector_size = 4 * 1024,
122 .block_erase_size = 64 * 1024,
123
124 .get_chip_write_protect = spi_flash_chip_generic_get_write_protect,
125 .set_chip_write_protect = spi_flash_chip_generic_set_write_protect,
126
127 .num_protectable_regions = 0,
128 .protectable_regions = NULL,
129 .get_protected_regions = NULL,
130 .set_protected_regions = NULL,
131
132 .read = spi_flash_chip_gd_read,
133 .write = spi_flash_chip_generic_write,
134 .program_page = spi_flash_chip_gd_page_program,
135 .page_size = 256,
136 .write_encrypted = spi_flash_chip_generic_write_encrypted,
137
138 .wait_idle = spi_flash_chip_generic_wait_idle,
139 .set_io_mode = spi_flash_chip_gd_set_io_mode,
140 .get_io_mode = spi_flash_chip_gd_get_io_mode,
141
142 .read_reg = spi_flash_chip_generic_read_reg,
143 .yield = spi_flash_chip_generic_yield,
144 .sus_setup = spi_flash_chip_generic_suspend_cmd_conf,
145 .read_unique_id = spi_flash_chip_generic_read_unique_id,
146 .get_chip_caps = spi_flash_chip_gd_get_caps,
147 .config_host_io_mode = spi_flash_chip_generic_config_host_io_mode,
148 };
149
