1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #include <stdint.h> 18 #include "soc/soc.h" 19 #include "soc.h" 20 #ifdef __cplusplus 21 extern "C" { 22 #endif 23 24 /** Control/Status registers */ 25 /** USB_GOTGCTL_REG register 26 * OTG Control and Status Register 27 */ 28 #define USB_GOTGCTL_REG (SOC_DPORT_USB_BASE + 0x0) 29 /** USB_SESREQSCS : RO; bitpos: [0]; default: 0; 30 * Session Request Success.The core sets this bit when a session request initiation is 31 * successful 32 */ 33 #define USB_SESREQSCS (BIT(0)) 34 #define USB_SESREQSCS_M (USB_SESREQSCS_V << USB_SESREQSCS_S) 35 #define USB_SESREQSCS_V 0x00000001 36 #define USB_SESREQSCS_S 0 37 /** USB_SESREQ : R/W; bitpos: [1]; default: 0; 38 * Session Request.The application sets this bit to initiate a session request on the 39 * USB. The application can clear this bit by writing a 0 when the Host Negotiation 40 * Success Status Change bit in the OTG Interrupt register 41 * (GOTGINT_REG.USB_HSTNEGSUCSTSCHNG) is SET. The core clears this bit when the 42 * USB_HSTNEGSUCSTSCHNG bit is cleared 43 */ 44 #define USB_SESREQ (BIT(1)) 45 #define USB_SESREQ_M (USB_SESREQ_V << USB_SESREQ_S) 46 #define USB_SESREQ_V 0x00000001 47 #define USB_SESREQ_S 1 48 /** USB_VBVALIDOVEN : R/W; bitpos: [2]; default: 0; 49 * VBUS Valid Override Enable 50 * 1'b1 : Internally Bvalid received from the PHY is overridden with 51 * GOTGCTL_REG.REG_VBVALIDOVVAl 52 * 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is 53 * used internally by the controller 54 */ 55 #define USB_VBVALIDOVEN (BIT(2)) 56 #define USB_VBVALIDOVEN_M (USB_VBVALIDOVEN_V << USB_VBVALIDOVEN_S) 57 #define USB_VBVALIDOVEN_V 0x00000001 58 #define USB_VBVALIDOVEN_S 2 59 /** USB_VBVALIDOVVAL : R/W; bitpos: [3]; default: 0; 60 * VBUS Valid OverrideValue 61 * 1'b0 : vbusvalid value is 1'b0 when GOTGCTL_REG.USB_VBVALIDOVEN =1 62 * 1'b1 : vbusvalid value is 1'b1 when GOTGCTL_REG.USB_VBVALIDOVEN =1 63 */ 64 #define USB_VBVALIDOVVAL (BIT(3)) 65 #define USB_VBVALIDOVVAL_M (USB_VBVALIDOVVAL_V << USB_VBVALIDOVVAL_S) 66 #define USB_VBVALIDOVVAL_V 0x00000001 67 #define USB_VBVALIDOVVAL_S 3 68 /** USB_AVALIDOVEN : R/W; bitpos: [4]; default: 0; 69 * This bit is used to enable/disable the software to override the Avalid signal using 70 * the GOTGCTL.AVALIDOVVAL 71 * 1'b1: Internally Avalid received from the PHY is overridden with 72 * GOTGCTL_REG.REG_AVALIDOVVAL 73 * 1'b0: Override is disabled and avalid signal from the respective PHY selected is 74 * used internally by the core 75 */ 76 #define USB_AVALIDOVEN (BIT(4)) 77 #define USB_AVALIDOVEN_M (USB_AVALIDOVEN_V << USB_AVALIDOVEN_S) 78 #define USB_AVALIDOVEN_V 0x00000001 79 #define USB_AVALIDOVEN_S 4 80 /** USB_AVALIDOVVAL : R/W; bitpos: [5]; default: 0; 81 * A-Peripheral Session Valid OverrideValue 82 * 1'b0 : Avalid value is 1'b0 when GOTGCTL_REG.USB_AVALIDOVEN =1 83 * 1'b1 : Avalid value is 1'b1 when GOTGCTL_REG.USB_AVALIDOVEN =1 84 */ 85 #define USB_AVALIDOVVAL (BIT(5)) 86 #define USB_AVALIDOVVAL_M (USB_AVALIDOVVAL_V << USB_AVALIDOVVAL_S) 87 #define USB_AVALIDOVVAL_V 0x00000001 88 #define USB_AVALIDOVVAL_S 5 89 /** USB_BVALIDOVEN : R/W; bitpos: [6]; default: 0; 90 * This bit is used to enable/disable the software to override the Bvalid signal using 91 * the GOTGCTLREG.BVALIDOVVAL 92 * 1'b1 : Internally Bvalid received from the PHY is overridden with 93 * GOTGCTL_REG.USB_BVALIDOVVAL 94 * 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is 95 * used internally by the force 96 */ 97 #define USB_BVALIDOVEN (BIT(6)) 98 #define USB_BVALIDOVEN_M (USB_BVALIDOVEN_V << USB_BVALIDOVEN_S) 99 #define USB_BVALIDOVEN_V 0x00000001 100 #define USB_BVALIDOVEN_S 6 101 /** USB_BVALIDOVVAL : R/W; bitpos: [7]; default: 0; 102 * B-Peripheral Session Valid OverrideValue 103 * 1'b0 : Bvalid value is 1'b0 when GOTGCTL_REG.USB_BVALIDOVEN =1 104 * 1'b1 : Bvalid value is 1'b1 when GOTGCTL_REG.USB_BVALIDOVEN =1 105 */ 106 #define USB_BVALIDOVVAL (BIT(7)) 107 #define USB_BVALIDOVVAL_M (USB_BVALIDOVVAL_V << USB_BVALIDOVVAL_S) 108 #define USB_BVALIDOVVAL_V 0x00000001 109 #define USB_BVALIDOVVAL_S 7 110 /** USB_HSTNEGSCS : RO; bitpos: [8]; default: 0; 111 * Host Negotiation Success.The controller sets this bit when host negotiation is 112 * successful. The controller clears this bit when the HNP Request (HNPReq) bit in 113 * this register is set. 114 */ 115 #define USB_HSTNEGSCS (BIT(8)) 116 #define USB_HSTNEGSCS_M (USB_HSTNEGSCS_V << USB_HSTNEGSCS_S) 117 #define USB_HSTNEGSCS_V 0x00000001 118 #define USB_HSTNEGSCS_S 8 119 /** USB_HNPREQ : R/W; bitpos: [9]; default: 0; 120 * HNP Request .The application sets this bit to initiate an HNP request to the 121 * Connected USB host. The application can clear this bit by writing a 0 when the Host 122 * Negotiation Success Status Change bit in the OTG Interrupt register 123 * (GOTGINT_REG.HSTNEGSUCSTSCHNG) is SET. The controller clears this bit when the 124 * HSTNEGSUCSTSCHNG bit is cleared. 125 */ 126 #define USB_HNPREQ (BIT(9)) 127 #define USB_HNPREQ_M (USB_HNPREQ_V << USB_HNPREQ_S) 128 #define USB_HNPREQ_V 0x00000001 129 #define USB_HNPREQ_S 9 130 /** USB_HSTSETHNPEN : R/W; bitpos: [10]; default: 0; 131 * Host Set HNP Enable.The application sets this bit when it has successfully enabled 132 * HNP (using the SetFeature.SetHNPEnable command) on the connected device 133 * 1'b0: Host Set HNP is not enabled 134 * 1'b1: Host Set HNP is enabled 135 */ 136 #define USB_HSTSETHNPEN (BIT(10)) 137 #define USB_HSTSETHNPEN_M (USB_HSTSETHNPEN_V << USB_HSTSETHNPEN_S) 138 #define USB_HSTSETHNPEN_V 0x00000001 139 #define USB_HSTSETHNPEN_S 10 140 /** USB_DEVHNPEN : R/W; bitpos: [11]; default: 0; 141 * Device HNP Enabled.The application sets this bit when it successfully receives a 142 * SetFeature.SetHNPEnable command from the connected USB host 143 * 1'b0: HNP is not enabled in the application 144 * 1'b1: HNP is enabled in the application 145 */ 146 #define USB_DEVHNPEN (BIT(11)) 147 #define USB_DEVHNPEN_M (USB_DEVHNPEN_V << USB_DEVHNPEN_S) 148 #define USB_DEVHNPEN_V 0x00000001 149 #define USB_DEVHNPEN_S 11 150 /** USB_EHEN : R/W; bitpos: [12]; default: 0; 151 * Embedded Host Enable.It is used to select between OTG A Device state Machine and 152 * Embedded Host state machine 153 * 1'b0: OTG A Device state machine is selected 154 * 1'b1: Embedded Host State Machine is selected 155 */ 156 #define USB_EHEN (BIT(12)) 157 #define USB_EHEN_M (USB_EHEN_V << USB_EHEN_S) 158 #define USB_EHEN_V 0x00000001 159 #define USB_EHEN_S 12 160 /** USB_DBNCEFLTRBYPASS : R/W; bitpos: [15]; default: 0; 161 * Bypass Debounce filters for avalid, bvalid, vbusvalid, sessend, iddig signals when 162 * enabled 163 * 1'b0: Disabled 164 * 1'b1: Enabled 165 */ 166 #define USB_DBNCEFLTRBYPASS (BIT(15)) 167 #define USB_DBNCEFLTRBYPASS_M (USB_DBNCEFLTRBYPASS_V << USB_DBNCEFLTRBYPASS_S) 168 #define USB_DBNCEFLTRBYPASS_V 0x00000001 169 #define USB_DBNCEFLTRBYPASS_S 15 170 /** USB_CONIDSTS : RO; bitpos: [16]; default: 0; 171 * Connector ID Status. Indicates the connector ID status on a connect event 172 * 1'b0: The core is in A-Device mode 173 * 1'b1: The core is in B-Device mode 174 */ 175 #define USB_CONIDSTS (BIT(16)) 176 #define USB_CONIDSTS_M (USB_CONIDSTS_V << USB_CONIDSTS_S) 177 #define USB_CONIDSTS_V 0x00000001 178 #define USB_CONIDSTS_S 16 179 /** USB_DBNCTIME : RO; bitpos: [17]; default: 0; 180 * Long/Short Debounce Time. Indicates the debounce time of a detected connection 181 * 1'b0: Long debounce time, used for physical connections (100ms + 2.5 micro-sec) 182 * 1'b1: Short debounce time, used for soft connections (2.5 micro-sec) 183 */ 184 #define USB_DBNCTIME (BIT(17)) 185 #define USB_DBNCTIME_M (USB_DBNCTIME_V << USB_DBNCTIME_S) 186 #define USB_DBNCTIME_V 0x00000001 187 #define USB_DBNCTIME_S 17 188 /** USB_ASESVLD : RO; bitpos: [18]; default: 0; 189 * A-Session Valid. Indicates the Host mode transceiver status 190 * 1'b0: A-session is not valid 191 * 1'b1: A-session is valid 192 */ 193 #define USB_ASESVLD (BIT(18)) 194 #define USB_ASESVLD_M (USB_ASESVLD_V << USB_ASESVLD_S) 195 #define USB_ASESVLD_V 0x00000001 196 #define USB_ASESVLD_S 18 197 /** USB_BSESVLD : RO; bitpos: [19]; default: 0; 198 * B-Session Valid.Indicates the Device mode transceiver status 199 * 1'b0: B-session is not valid 200 * 1'b1: B-session is valid 201 */ 202 #define USB_BSESVLD (BIT(19)) 203 #define USB_BSESVLD_M (USB_BSESVLD_V << USB_BSESVLD_S) 204 #define USB_BSESVLD_V 0x00000001 205 #define USB_BSESVLD_S 19 206 /** USB_OTGVER : R/W; bitpos: [20]; default: 0; 207 * OTG Version 208 * 1'b0:Supports OTG Version 1.3 209 * 1'b1:Supports OTG Version 2.0 210 */ 211 #define USB_OTGVER (BIT(20)) 212 #define USB_OTGVER_M (USB_OTGVER_V << USB_OTGVER_S) 213 #define USB_OTGVER_V 0x00000001 214 #define USB_OTGVER_S 20 215 /** USB_CURMOD : RO; bitpos: [21]; default: 0; 216 * Current Mode of Operation 217 * 1'b0: Device mode 218 * 1'b1:Host mode 219 */ 220 #define USB_CURMOD (BIT(21)) 221 #define USB_CURMOD_M (USB_CURMOD_V << USB_CURMOD_S) 222 #define USB_CURMOD_V 0x00000001 223 #define USB_CURMOD_S 21 224 225 226 /** USB_GDFIFOCFG_REG register 227 * Global DFIFO Configuration Register 228 */ 229 #define USB_GDFIFOCFG_REG (SOC_DPORT_USB_BASE + 0x5c) 230 /** USB_GDFIFOCFG : R/W; bitpos: [16:0]; default: 0; 231 * GDFIFOCfg 232 */ 233 #define USB_GDFIFOCFG 0x0000FFFF 234 #define USB_GDFIFOCFG_M (USB_GDFIFOCFG_V << USB_GDFIFOCFG_S) 235 #define USB_GDFIFOCFG_V 0x0000FFFF 236 #define USB_GDFIFOCFG_S 0 237 /** USB_EPINFOBASEADDR : R/W; bitpos: [32:16]; default: 0; 238 * EPInfoBaseAddr 239 */ 240 #define USB_EPINFOBASEADDR 0x0000FFFF 241 #define USB_EPINFOBASEADDR_M (USB_EPINFOBASEADDR_V << USB_EPINFOBASEADDR_S) 242 #define USB_EPINFOBASEADDR_V 0x0000FFFF 243 #define USB_EPINFOBASEADDR_S 16 244 245 246 /** USB_HPTXFSIZ_REG register 247 * Host Periodic Transmit FIFO Size Register 248 */ 249 #define USB_HPTXFSIZ_REG (SOC_DPORT_USB_BASE + 0x100) 250 /** USB_PTXFSTADDR : R/W; bitpos: [16:0]; default: 512; 251 * Host Periodic TxFIFO Start Address. 252 */ 253 #define USB_PTXFSTADDR 0x0000FFFF 254 #define USB_PTXFSTADDR_M (USB_PTXFSTADDR_V << USB_PTXFSTADDR_S) 255 #define USB_PTXFSTADDR_V 0x0000FFFF 256 #define USB_PTXFSTADDR_S 0 257 /** USB_PTXFSIZE : R/W; bitpos: [32:16]; default: 4096; 258 * Host Periodic TxFIFO Depth,This value is in terms of 32-bit words.. 259 */ 260 #define USB_PTXFSIZE 0x0000FFFF 261 #define USB_PTXFSIZE_M (USB_PTXFSIZE_V << USB_PTXFSIZE_S) 262 #define USB_PTXFSIZE_V 0x0000FFFF 263 #define USB_PTXFSIZE_S 16 264 265 266 /** USB_DIEPTXF1_REG register 267 * Device IN Endpoint Transmit FIFO Size Register 268 */ 269 #define USB_DIEPTXF1_REG (SOC_DPORT_USB_BASE + 0x104) 270 /** USB_INEP1TXFSTADDR : R/W; bitpos: [16:0]; default: 512; 271 * IN Endpoint FIFOn Transmit RAM Start Address. 272 */ 273 #define USB_INEP1TXFSTADDR 0x0000FFFF 274 #define USB_INEP1TXFSTADDR_M (USB_INEP1TXFSTADDR_V << USB_INEP1TXFSTADDR_S) 275 #define USB_INEP1TXFSTADDR_V 0x0000FFFF 276 #define USB_INEP1TXFSTADDR_S 0 277 /** USB_INEP1TXFDEP : R/W; bitpos: [32:16]; default: 4096; 278 * IN Endpoint TxFIFO Depth 279 */ 280 #define USB_INEP1TXFDEP 0x0000FFFF 281 #define USB_INEP1TXFDEP_M (USB_INEP1TXFDEP_V << USB_INEP1TXFDEP_S) 282 #define USB_INEP1TXFDEP_V 0x0000FFFF 283 #define USB_INEP1TXFDEP_S 16 284 285 286 /** USB_DIEPTXF2_REG register 287 * Device IN Endpoint Transmit FIFO Size Register 288 */ 289 #define USB_DIEPTXF2_REG (SOC_DPORT_USB_BASE + 0x108) 290 /** USB_INEP2TXFSTADDR : R/W; bitpos: [16:0]; default: 512; 291 * IN Endpoint FIFOn Transmit RAM Start Address. 292 */ 293 #define USB_INEP2TXFSTADDR 0x0000FFFF 294 #define USB_INEP2TXFSTADDR_M (USB_INEP2TXFSTADDR_V << USB_INEP2TXFSTADDR_S) 295 #define USB_INEP2TXFSTADDR_V 0x0000FFFF 296 #define USB_INEP2TXFSTADDR_S 0 297 /** USB_INEP2TXFDEP : R/W; bitpos: [32:16]; default: 4096; 298 * IN Endpoint TxFIFO Depth 299 */ 300 #define USB_INEP2TXFDEP 0x0000FFFF 301 #define USB_INEP2TXFDEP_M (USB_INEP2TXFDEP_V << USB_INEP2TXFDEP_S) 302 #define USB_INEP2TXFDEP_V 0x0000FFFF 303 #define USB_INEP2TXFDEP_S 16 304 305 306 /** USB_DIEPTXF3_REG register 307 * Device IN Endpoint Transmit FIFO Size Register 308 */ 309 #define USB_DIEPTXF3_REG (SOC_DPORT_USB_BASE + 0x10c) 310 /** USB_INEP3TXFSTADDR : R/W; bitpos: [16:0]; default: 512; 311 * IN Endpoint FIFOn Transmit RAM Start Address. 312 */ 313 #define USB_INEP3TXFSTADDR 0x0000FFFF 314 #define USB_INEP3TXFSTADDR_M (USB_INEP3TXFSTADDR_V << USB_INEP3TXFSTADDR_S) 315 #define USB_INEP3TXFSTADDR_V 0x0000FFFF 316 #define USB_INEP3TXFSTADDR_S 0 317 /** USB_INEP3TXFDEP : R/W; bitpos: [32:16]; default: 4096; 318 * IN Endpoint TxFIFO Depth 319 */ 320 #define USB_INEP3TXFDEP 0x0000FFFF 321 #define USB_INEP3TXFDEP_M (USB_INEP3TXFDEP_V << USB_INEP3TXFDEP_S) 322 #define USB_INEP3TXFDEP_V 0x0000FFFF 323 #define USB_INEP3TXFDEP_S 16 324 325 326 /** USB_DIEPTXF4_REG register 327 * Device IN Endpoint Transmit FIFO Size Register 328 */ 329 #define USB_DIEPTXF4_REG (SOC_DPORT_USB_BASE + 0x110) 330 /** USB_INEP4TXFSTADDR : R/W; bitpos: [16:0]; default: 512; 331 * IN Endpoint FIFOn Transmit RAM Start Address. 332 */ 333 #define USB_INEP4TXFSTADDR 0x0000FFFF 334 #define USB_INEP4TXFSTADDR_M (USB_INEP4TXFSTADDR_V << USB_INEP4TXFSTADDR_S) 335 #define USB_INEP4TXFSTADDR_V 0x0000FFFF 336 #define USB_INEP4TXFSTADDR_S 0 337 /** USB_INEP4TXFDEP : R/W; bitpos: [32:16]; default: 4096; 338 * IN Endpoint TxFIFO Depth 339 */ 340 #define USB_INEP4TXFDEP 0x0000FFFF 341 #define USB_INEP4TXFDEP_M (USB_INEP4TXFDEP_V << USB_INEP4TXFDEP_S) 342 #define USB_INEP4TXFDEP_V 0x0000FFFF 343 #define USB_INEP4TXFDEP_S 16 344 345 346 /** USB_HCFG_REG register 347 * Host Configuration Register 348 */ 349 #define USB_HCFG_REG (SOC_DPORT_USB_BASE + 0x400) 350 /** USB_H_FSLSPCLKSEL : R/W; bitpos: [2:0]; default: 0; 351 * 0x0 : PHY clock is running at 30/60 MHz 352 * 0x1 : PHY clock is running at 48 MHz 353 * 0x2 : PHY clock is running at 6 MHz 354 */ 355 #define USB_H_FSLSPCLKSEL 0x00000003 356 #define USB_H_FSLSPCLKSEL_M (USB_H_FSLSPCLKSEL_V << USB_H_FSLSPCLKSEL_S) 357 #define USB_H_FSLSPCLKSEL_V 0x00000003 358 #define USB_H_FSLSPCLKSEL_S 0 359 /** USB_H_FSLSSUPP : R/W; bitpos: [2]; default: 0; 360 * FS- and LS-Only Support 361 * 1'b0: HS/FS/LS, based on the maximum speed supported by the connected device 362 * 1'b1: FS/LS-only, even If the connected device can support HS 363 */ 364 #define USB_H_FSLSSUPP (BIT(2)) 365 #define USB_H_FSLSSUPP_M (USB_H_FSLSSUPP_V << USB_H_FSLSSUPP_S) 366 #define USB_H_FSLSSUPP_V 0x00000001 367 #define USB_H_FSLSSUPP_S 2 368 /** USB_H_ENA32KHZS : R/W; bitpos: [7]; default: 0; 369 * 1'b0:32 KHz Suspend mode disabled 370 * 1'b1:32 KHz Suspend mode enabled 371 */ 372 #define USB_H_ENA32KHZS (BIT(7)) 373 #define USB_H_ENA32KHZS_M (USB_H_ENA32KHZS_V << USB_H_ENA32KHZS_S) 374 #define USB_H_ENA32KHZS_V 0x00000001 375 #define USB_H_ENA32KHZS_S 7 376 /** USB_H_DESCDMA : R/W; bitpos: [23]; default: 0; 377 * GAHBCFG_REG.USB_DMAEN=0,HCFG_REG.USB_DESCDMA=0 => Slave mode 378 * GAHBCFG_REG.USB_DMAEN=0,HCFG_REG.USB_DESCDMA=1 => Invalid 379 * GAHBCFG_REG.USB_DMAEN=1,HCFG_REG.USB_DESCDMA=0 => Buffered DMA 380 * GAHBCFG_REG.USB_DMAEN=1,HCFG_REG.USB_DESCDMA=1 => Scatter/Gather DMA mode 381 */ 382 #define USB_H_DESCDMA (BIT(23)) 383 #define USB_H_DESCDMA_M (USB_H_DESCDMA_V << USB_H_DESCDMA_S) 384 #define USB_H_DESCDMA_V 0x00000001 385 #define USB_H_DESCDMA_S 23 386 /** USB_H_FRLISTEN : R/W; bitpos: [26:24]; default: 0; 387 * Frame List Entries 388 * 2'b00: 8 Entries 389 * 2'b01: 16 Entries 390 * 2'b10: 32 Entries 391 * 2'b11: 64 Entries 392 */ 393 #define USB_H_FRLISTEN 0x00000003 394 #define USB_H_FRLISTEN_M (USB_H_FRLISTEN_V << USB_H_FRLISTEN_S) 395 #define USB_H_FRLISTEN_V 0x00000003 396 #define USB_H_FRLISTEN_S 24 397 /** USB_H_PERSCHEDENA : R/W; bitpos: [26]; default: 0; 398 * 0x0 (DISABLED): Disables periodic scheduling within the core 399 * 0x1 (ENABLED): Enables periodic scheduling within the core 400 */ 401 #define USB_H_PERSCHEDENA (BIT(26)) 402 #define USB_H_PERSCHEDENA_M (USB_H_PERSCHEDENA_V << USB_H_PERSCHEDENA_S) 403 #define USB_H_PERSCHEDENA_V 0x00000001 404 #define USB_H_PERSCHEDENA_S 26 405 /** USB_H_MODECHTIMEN : R/W; bitpos: [31]; default: 0; 406 * Mode Change Ready Timer Enable, 407 * 1'b0 : The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at 408 * the end of resume to the change the opmode from 2'b10 to 2'b00. 409 * 1'b1 : The Host core waits only for a linstate of SE0 at the end of resume to 410 * change the opmode from 2'b10 to 2'b00. 411 */ 412 #define USB_H_MODECHTIMEN (BIT(31)) 413 #define USB_H_MODECHTIMEN_M (USB_H_MODECHTIMEN_V << USB_H_MODECHTIMEN_S) 414 #define USB_H_MODECHTIMEN_V 0x00000001 415 #define USB_H_MODECHTIMEN_S 31 416 417 418 /** USB_HFIR_REG register 419 * Host Frame Interval Register 420 */ 421 #define USB_HFIR_REG (SOC_DPORT_USB_BASE + 0x404) 422 /** USB_FRINT : R/W; bitpos: [16:0]; default: 6103; 423 * Frame Interval . 1 ms * (PHY clock frequency for FS/LS) 424 */ 425 #define USB_FRINT 0x0000FFFF 426 #define USB_FRINT_M (USB_FRINT_V << USB_FRINT_S) 427 #define USB_FRINT_V 0x0000FFFF 428 #define USB_FRINT_S 0 429 /** USB_HFIRRLDCTRL : R/W; bitpos: [16]; default: 0; 430 * Reload Control 431 * 1'b0 : The HFIR cannot be reloaded dynamically 432 * 1'b1: the HFIR can be dynamically reloaded during runtime 433 */ 434 #define USB_HFIRRLDCTRL (BIT(16)) 435 #define USB_HFIRRLDCTRL_M (USB_HFIRRLDCTRL_V << USB_HFIRRLDCTRL_S) 436 #define USB_HFIRRLDCTRL_V 0x00000001 437 #define USB_HFIRRLDCTRL_S 16 438 439 440 /** USB_HFLBADDR_REG register 441 * Host Frame List Base Address Register 442 */ 443 #define USB_HFLBADDR_REG (SOC_DPORT_USB_BASE + 0x41c) 444 /** USB_HFLBADDR : R/W; bitpos: [32:0]; default: 0; 445 * The starting address of the Frame list. This register is used only for Isochronous 446 * and Interrupt Channels. 447 */ 448 #define USB_HFLBADDR 0xFFFFFFFF 449 #define USB_HFLBADDR_M (USB_HFLBADDR_V << USB_HFLBADDR_S) 450 #define USB_HFLBADDR_V 0xFFFFFFFF 451 #define USB_HFLBADDR_S 0 452 453 454 /** USB_HPRT_REG register 455 * Host Port Control and Status Register 456 */ 457 #define USB_HPRT_REG (SOC_DPORT_USB_BASE + 0x440) 458 /** USB_PRTCONNSTS : RO; bitpos: [0]; default: 0; 459 * Port Connect Status 460 * 0x0: No device is attached to the port 461 * 0x1: A device is attached to the port 462 */ 463 #define USB_PRTCONNSTS (BIT(0)) 464 #define USB_PRTCONNSTS_M (USB_PRTCONNSTS_V << USB_PRTCONNSTS_S) 465 #define USB_PRTCONNSTS_V 0x00000001 466 #define USB_PRTCONNSTS_S 0 467 /** USB_PRTCONNDET : R/W; bitpos: [1]; default: 0; 468 * Port Connect Detected. 469 * 0x1 : Device connection detected. 470 * 0x0 : No device connection detected. 471 */ 472 #define USB_PRTCONNDET (BIT(1)) 473 #define USB_PRTCONNDET_M (USB_PRTCONNDET_V << USB_PRTCONNDET_S) 474 #define USB_PRTCONNDET_V 0x00000001 475 #define USB_PRTCONNDET_S 1 476 /** USB_PRTENA : R/W; bitpos: [2]; default: 0; 477 * Port Enable 478 * 1'b0: Port disabled 479 * 1'b1: Port enabled 480 */ 481 #define USB_PRTENA (BIT(2)) 482 #define USB_PRTENA_M (USB_PRTENA_V << USB_PRTENA_S) 483 #define USB_PRTENA_V 0x00000001 484 #define USB_PRTENA_S 2 485 /** USB_PRTENCHNG : R/W; bitpos: [3]; default: 0; 486 * Port Enable/Disable Change 487 * 0x0 : Port Enable bit 2 has not changed 488 * 0x1 : Port Enable bit 2 changed 489 */ 490 #define USB_PRTENCHNG (BIT(3)) 491 #define USB_PRTENCHNG_M (USB_PRTENCHNG_V << USB_PRTENCHNG_S) 492 #define USB_PRTENCHNG_V 0x00000001 493 #define USB_PRTENCHNG_S 3 494 /** USB_PRTOVRCURRACT : RO; bitpos: [4]; default: 0; 495 * Port Overcurrent Active 496 * 1'b0: No overcurrent condition 497 * 1'b1: Overcurrent condition 498 */ 499 #define USB_PRTOVRCURRACT (BIT(4)) 500 #define USB_PRTOVRCURRACT_M (USB_PRTOVRCURRACT_V << USB_PRTOVRCURRACT_S) 501 #define USB_PRTOVRCURRACT_V 0x00000001 502 #define USB_PRTOVRCURRACT_S 4 503 /** USB_PRTOVRCURRCHNG : R/W; bitpos: [5]; default: 0; 504 * Port Overcurrent Change 505 * 0x0: Status of port overcurrent status is not changed 506 * 0x1: Status of port overcurrent changed 507 */ 508 #define USB_PRTOVRCURRCHNG (BIT(5)) 509 #define USB_PRTOVRCURRCHNG_M (USB_PRTOVRCURRCHNG_V << USB_PRTOVRCURRCHNG_S) 510 #define USB_PRTOVRCURRCHNG_V 0x00000001 511 #define USB_PRTOVRCURRCHNG_S 5 512 /** USB_PRTRES : R/W; bitpos: [6]; default: 0; 513 * Port Resume 514 * 1'b0: No resume driven 515 * 1'b1: Resume driven 516 */ 517 #define USB_PRTRES (BIT(6)) 518 #define USB_PRTRES_M (USB_PRTRES_V << USB_PRTRES_S) 519 #define USB_PRTRES_V 0x00000001 520 #define USB_PRTRES_S 6 521 /** USB_PRTSUSP : R/W; bitpos: [7]; default: 0; 522 * Port Suspend 523 * 1'b0: Port not in Suspend mode 524 * 1'b1: Port in Suspend mode 525 */ 526 #define USB_PRTSUSP (BIT(7)) 527 #define USB_PRTSUSP_M (USB_PRTSUSP_V << USB_PRTSUSP_S) 528 #define USB_PRTSUSP_V 0x00000001 529 #define USB_PRTSUSP_S 7 530 /** USB_PRTRST : R/W; bitpos: [8]; default: 0; 531 * Port Reset. 532 * 1'b0: Port not in reset 533 * 1'b1: Port in reset 534 */ 535 #define USB_PRTRST (BIT(8)) 536 #define USB_PRTRST_M (USB_PRTRST_V << USB_PRTRST_S) 537 #define USB_PRTRST_V 0x00000001 538 #define USB_PRTRST_S 8 539 /** USB_PRTLNSTS : RO; bitpos: [12:10]; default: 0; 540 * Port Line Status 541 * Bit [10]: Logic level of D+ 542 * Bit [11]: Logic level of D- 543 */ 544 #define USB_PRTLNSTS 0x00000003 545 #define USB_PRTLNSTS_M (USB_PRTLNSTS_V << USB_PRTLNSTS_S) 546 #define USB_PRTLNSTS_V 0x00000003 547 #define USB_PRTLNSTS_S 10 548 /** USB_PRTPWR : R/W; bitpos: [12]; default: 0; 549 * Port Power 550 * 1'b0: Power off 551 * 1'b1: Power on 552 */ 553 #define USB_PRTPWR (BIT(12)) 554 #define USB_PRTPWR_M (USB_PRTPWR_V << USB_PRTPWR_S) 555 #define USB_PRTPWR_V 0x00000001 556 #define USB_PRTPWR_S 12 557 /** USB_PRTTSTCTL : R/W; bitpos: [17:13]; default: 0; 558 * Port Test Control 559 * 4'b0000: Test mode disabled 560 * 4'b0001: Test_J mode 561 * 4'b0010: Test_K mode 562 * 4'b0011: Test_SE0_NAK mode 563 * 4'b0100: Test_Packet mode 564 * 4'b0101: Test_Force_Enable 565 * Others: Reserved 566 */ 567 #define USB_PRTTSTCTL 0x0000000F 568 #define USB_PRTTSTCTL_M (USB_PRTTSTCTL_V << USB_PRTTSTCTL_S) 569 #define USB_PRTTSTCTL_V 0x0000000F 570 #define USB_PRTTSTCTL_S 13 571 /** USB_PRTSPD : RO; bitpos: [19:17]; default: 0; 572 * Port Speed 573 * 2'b00: High speed 574 * 2'b01: Full speed 575 * 2'b10: Low speed 576 * 2'b11: Reserved 577 */ 578 #define USB_PRTSPD 0x00000003 579 #define USB_PRTSPD_M (USB_PRTSPD_V << USB_PRTSPD_S) 580 #define USB_PRTSPD_V 0x00000003 581 #define USB_PRTSPD_S 17 582 583 584 /** USB_HCCHAR0_REG register 585 * Host Channel 0 Characteristics Register 586 */ 587 #define USB_HCCHAR0_REG (SOC_DPORT_USB_BASE + 0x500) 588 /** USB_H_MPS0 : R/W; bitpos: [11:0]; default: 0; 589 * Maximum Packet Size. 590 */ 591 #define USB_H_MPS0 0x000007FF 592 #define USB_H_MPS0_M (USB_H_MPS0_V << USB_H_MPS0_S) 593 #define USB_H_MPS0_V 0x000007FF 594 #define USB_H_MPS0_S 0 595 /** USB_H_EPNUM0 : R/W; bitpos: [15:11]; default: 0; 596 * Endpoint Number. 597 */ 598 #define USB_H_EPNUM0 0x0000000F 599 #define USB_H_EPNUM0_M (USB_H_EPNUM0_V << USB_H_EPNUM0_S) 600 #define USB_H_EPNUM0_V 0x0000000F 601 #define USB_H_EPNUM0_S 11 602 /** USB_H_EPDIR0 : R/W; bitpos: [15]; default: 0; 603 * 1'b0: OUT 604 * 1'b1: IN 605 */ 606 #define USB_H_EPDIR0 (BIT(15)) 607 #define USB_H_EPDIR0_M (USB_H_EPDIR0_V << USB_H_EPDIR0_S) 608 #define USB_H_EPDIR0_V 0x00000001 609 #define USB_H_EPDIR0_S 15 610 /** USB_H_LSPDDEV0 : R/W; bitpos: [17]; default: 0; 611 * 0x0: Not Communicating with low speed device 612 * 0x1: Communicating with low speed device 613 */ 614 #define USB_H_LSPDDEV0 (BIT(17)) 615 #define USB_H_LSPDDEV0_M (USB_H_LSPDDEV0_V << USB_H_LSPDDEV0_S) 616 #define USB_H_LSPDDEV0_V 0x00000001 617 #define USB_H_LSPDDEV0_S 17 618 /** USB_H_EPTYPE0 : R/W; bitpos: [20:18]; default: 0; 619 * 0x0 (CTRL): Contro 620 * 0x1 (ISOC): Isochronous 621 * 0x2 (BULK): Bulk 622 * 0x3 (INTERR): Interrupt 623 */ 624 #define USB_H_EPTYPE0 0x00000003 625 #define USB_H_EPTYPE0_M (USB_H_EPTYPE0_V << USB_H_EPTYPE0_S) 626 #define USB_H_EPTYPE0_V 0x00000003 627 #define USB_H_EPTYPE0_S 18 628 /** USB_H_EC0 : R/W; bitpos: [21]; default: 0; 629 * Multi Count (MC) / Error Count(EC) 630 * 0x0 (RESERVED): Reserved. This field yields undefined result 631 * 0x1 (TRANSONE): 1 transaction 632 * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe 633 * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe 634 */ 635 #define USB_H_EC0 (BIT(21)) 636 #define USB_H_EC0_M (USB_H_EC0_V << USB_H_EC0_S) 637 #define USB_H_EC0_V 0x00000001 638 #define USB_H_EC0_S 21 639 /** USB_H_DEVADDR0 : R/W; bitpos: [29:22]; default: 0; 640 * Device Address . This field selects the specific device serving as the data 641 * source or sink. 642 */ 643 #define USB_H_DEVADDR0 0x0000007F 644 #define USB_H_DEVADDR0_M (USB_H_DEVADDR0_V << USB_H_DEVADDR0_S) 645 #define USB_H_DEVADDR0_V 0x0000007F 646 #define USB_H_DEVADDR0_S 22 647 /** USB_H_ODDFRM0 : R/W; bitpos: [29]; default: 0; 648 * Odd Frame 649 * 1'b0: Even (micro)Frame 650 * 1'b1: Odd (micro)Frame 651 */ 652 #define USB_H_ODDFRM0 (BIT(29)) 653 #define USB_H_ODDFRM0_M (USB_H_ODDFRM0_V << USB_H_ODDFRM0_S) 654 #define USB_H_ODDFRM0_V 0x00000001 655 #define USB_H_ODDFRM0_S 29 656 /** USB_H_CHDIS0 : R/W; bitpos: [30]; default: 0; 657 * Channel Disable 658 * 0x0 : Transmit/Recieve norma 659 * 0x1 : Stop transmitting/receiving data on channel 660 */ 661 #define USB_H_CHDIS0 (BIT(30)) 662 #define USB_H_CHDIS0_M (USB_H_CHDIS0_V << USB_H_CHDIS0_S) 663 #define USB_H_CHDIS0_V 0x00000001 664 #define USB_H_CHDIS0_S 30 665 /** USB_H_CHENA0 : R/W; bitpos: [31]; default: 0; 666 * Channel Enable 667 * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is 668 * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is 669 * disabled 670 * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure 671 * and data buffer with data is set up and this channel can access the descriptor. If 672 * Scatter/Gather mode is disabled, indicates that the channel is enabled 673 */ 674 #define USB_H_CHENA0 (BIT(31)) 675 #define USB_H_CHENA0_M (USB_H_CHENA0_V << USB_H_CHENA0_S) 676 #define USB_H_CHENA0_V 0x00000001 677 #define USB_H_CHENA0_S 31 678 679 680 /** USB_HCDMA0_REG register 681 * Host Channel 0 DMA Address Register 682 */ 683 #define USB_HCDMA0_REG (SOC_DPORT_USB_BASE + 0x514) 684 /** USB_H_DMAADDR0 : R/W; bitpos: [32:0]; default: 0; 685 * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: 686 * [31:9]: DMA Address 687 * [8:3]: Current Transfer Desc 688 * [2:0]: Reserved 689 */ 690 #define USB_H_DMAADDR0 0xFFFFFFFF 691 #define USB_H_DMAADDR0_M (USB_H_DMAADDR0_V << USB_H_DMAADDR0_S) 692 #define USB_H_DMAADDR0_V 0xFFFFFFFF 693 #define USB_H_DMAADDR0_S 0 694 695 696 /** USB_HCCHAR1_REG register 697 * Host Channel 1 Characteristics Register 698 */ 699 #define USB_HCCHAR1_REG (SOC_DPORT_USB_BASE + 0x520) 700 /** USB_H_MPS1 : R/W; bitpos: [11:0]; default: 0; 701 * Maximum Packet Size. 702 */ 703 #define USB_H_MPS1 0x000007FF 704 #define USB_H_MPS1_M (USB_H_MPS1_V << USB_H_MPS1_S) 705 #define USB_H_MPS1_V 0x000007FF 706 #define USB_H_MPS1_S 0 707 /** USB_H_EPNUM1 : R/W; bitpos: [15:11]; default: 0; 708 * Endpoint Number. 709 */ 710 #define USB_H_EPNUM1 0x0000000F 711 #define USB_H_EPNUM1_M (USB_H_EPNUM1_V << USB_H_EPNUM1_S) 712 #define USB_H_EPNUM1_V 0x0000000F 713 #define USB_H_EPNUM1_S 11 714 /** USB_H_EPDIR1 : R/W; bitpos: [15]; default: 0; 715 * 1'b0: OUT 716 * 1'b1: IN 717 */ 718 #define USB_H_EPDIR1 (BIT(15)) 719 #define USB_H_EPDIR1_M (USB_H_EPDIR1_V << USB_H_EPDIR1_S) 720 #define USB_H_EPDIR1_V 0x00000001 721 #define USB_H_EPDIR1_S 15 722 /** USB_H_LSPDDEV1 : R/W; bitpos: [17]; default: 0; 723 * 0x0: Not Communicating with low speed device 724 * 0x1: Communicating with low speed device 725 */ 726 #define USB_H_LSPDDEV1 (BIT(17)) 727 #define USB_H_LSPDDEV1_M (USB_H_LSPDDEV1_V << USB_H_LSPDDEV1_S) 728 #define USB_H_LSPDDEV1_V 0x00000001 729 #define USB_H_LSPDDEV1_S 17 730 /** USB_H_EPTYPE1 : R/W; bitpos: [20:18]; default: 0; 731 * 0x0 (CTRL): Contro 732 * 0x1 (ISOC): Isochronous 733 * 0x2 (BULK): Bulk 734 * 0x3 (INTERR): Interrupt 735 */ 736 #define USB_H_EPTYPE1 0x00000003 737 #define USB_H_EPTYPE1_M (USB_H_EPTYPE1_V << USB_H_EPTYPE1_S) 738 #define USB_H_EPTYPE1_V 0x00000003 739 #define USB_H_EPTYPE1_S 18 740 /** USB_H_EC1 : R/W; bitpos: [21]; default: 0; 741 * Multi Count (MC) / Error Count(EC) 742 * 0x0 (RESERVED): Reserved. This field yields undefined result 743 * 0x1 (TRANSONE): 1 transaction 744 * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe 745 * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe 746 */ 747 #define USB_H_EC1 (BIT(21)) 748 #define USB_H_EC1_M (USB_H_EC1_V << USB_H_EC1_S) 749 #define USB_H_EC1_V 0x00000001 750 #define USB_H_EC1_S 21 751 /** USB_H_DEVADDR1 : R/W; bitpos: [29:22]; default: 0; 752 * Device Address . This field selects the specific device serving as the data 753 * source or sink. 754 */ 755 #define USB_H_DEVADDR1 0x0000007F 756 #define USB_H_DEVADDR1_M (USB_H_DEVADDR1_V << USB_H_DEVADDR1_S) 757 #define USB_H_DEVADDR1_V 0x0000007F 758 #define USB_H_DEVADDR1_S 22 759 /** USB_H_ODDFRM1 : R/W; bitpos: [29]; default: 0; 760 * Odd Frame 761 * 1'b0: Even (micro)Frame 762 * 1'b1: Odd (micro)Frame 763 */ 764 #define USB_H_ODDFRM1 (BIT(29)) 765 #define USB_H_ODDFRM1_M (USB_H_ODDFRM1_V << USB_H_ODDFRM1_S) 766 #define USB_H_ODDFRM1_V 0x00000001 767 #define USB_H_ODDFRM1_S 29 768 /** USB_H_CHDIS1 : R/W; bitpos: [30]; default: 0; 769 * Channel Disable 770 * 0x0 : Transmit/Recieve norma 771 * 0x1 : Stop transmitting/receiving data on channel 772 */ 773 #define USB_H_CHDIS1 (BIT(30)) 774 #define USB_H_CHDIS1_M (USB_H_CHDIS1_V << USB_H_CHDIS1_S) 775 #define USB_H_CHDIS1_V 0x00000001 776 #define USB_H_CHDIS1_S 30 777 /** USB_H_CHENA1 : R/W; bitpos: [31]; default: 0; 778 * Channel Enable 779 * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is 780 * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is 781 * disabled 782 * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure 783 * and data buffer with data is set up and this channel can access the descriptor. If 784 * Scatter/Gather mode is disabled, indicates that the channel is enabled 785 */ 786 #define USB_H_CHENA1 (BIT(31)) 787 #define USB_H_CHENA1_M (USB_H_CHENA1_V << USB_H_CHENA1_S) 788 #define USB_H_CHENA1_V 0x00000001 789 #define USB_H_CHENA1_S 31 790 791 792 /** USB_HCDMA1_REG register 793 * Host Channel 1 DMA Address Register 794 */ 795 #define USB_HCDMA1_REG (SOC_DPORT_USB_BASE + 0x534) 796 /** USB_H_DMAADDR1 : R/W; bitpos: [32:0]; default: 0; 797 * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: 798 * [31:9]: DMA Address 799 * [8:3]: Current Transfer Desc 800 * [2:0]: Reserved 801 */ 802 #define USB_H_DMAADDR1 0xFFFFFFFF 803 #define USB_H_DMAADDR1_M (USB_H_DMAADDR1_V << USB_H_DMAADDR1_S) 804 #define USB_H_DMAADDR1_V 0xFFFFFFFF 805 #define USB_H_DMAADDR1_S 0 806 807 808 /** USB_HCCHAR2_REG register 809 * Host Channel 2 Characteristics Register 810 */ 811 #define USB_HCCHAR2_REG (SOC_DPORT_USB_BASE + 0x540) 812 /** USB_H_MPS2 : R/W; bitpos: [11:0]; default: 0; 813 * Maximum Packet Size. 814 */ 815 #define USB_H_MPS2 0x000007FF 816 #define USB_H_MPS2_M (USB_H_MPS2_V << USB_H_MPS2_S) 817 #define USB_H_MPS2_V 0x000007FF 818 #define USB_H_MPS2_S 0 819 /** USB_H_EPNUM2 : R/W; bitpos: [15:11]; default: 0; 820 * Endpoint Number. 821 */ 822 #define USB_H_EPNUM2 0x0000000F 823 #define USB_H_EPNUM2_M (USB_H_EPNUM2_V << USB_H_EPNUM2_S) 824 #define USB_H_EPNUM2_V 0x0000000F 825 #define USB_H_EPNUM2_S 11 826 /** USB_H_EPDIR2 : R/W; bitpos: [15]; default: 0; 827 * 1'b0: OUT 828 * 1'b1: IN 829 */ 830 #define USB_H_EPDIR2 (BIT(15)) 831 #define USB_H_EPDIR2_M (USB_H_EPDIR2_V << USB_H_EPDIR2_S) 832 #define USB_H_EPDIR2_V 0x00000001 833 #define USB_H_EPDIR2_S 15 834 /** USB_H_LSPDDEV2 : R/W; bitpos: [17]; default: 0; 835 * 0x0: Not Communicating with low speed device 836 * 0x1: Communicating with low speed device 837 */ 838 #define USB_H_LSPDDEV2 (BIT(17)) 839 #define USB_H_LSPDDEV2_M (USB_H_LSPDDEV2_V << USB_H_LSPDDEV2_S) 840 #define USB_H_LSPDDEV2_V 0x00000001 841 #define USB_H_LSPDDEV2_S 17 842 /** USB_H_EPTYPE2 : R/W; bitpos: [20:18]; default: 0; 843 * 0x0 (CTRL): Contro 844 * 0x1 (ISOC): Isochronous 845 * 0x2 (BULK): Bulk 846 * 0x3 (INTERR): Interrupt 847 */ 848 #define USB_H_EPTYPE2 0x00000003 849 #define USB_H_EPTYPE2_M (USB_H_EPTYPE2_V << USB_H_EPTYPE2_S) 850 #define USB_H_EPTYPE2_V 0x00000003 851 #define USB_H_EPTYPE2_S 18 852 /** USB_H_EC2 : R/W; bitpos: [21]; default: 0; 853 * Multi Count (MC) / Error Count(EC) 854 * 0x0 (RESERVED): Reserved. This field yields undefined result 855 * 0x1 (TRANSONE): 1 transaction 856 * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe 857 * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe 858 */ 859 #define USB_H_EC2 (BIT(21)) 860 #define USB_H_EC2_M (USB_H_EC2_V << USB_H_EC2_S) 861 #define USB_H_EC2_V 0x00000001 862 #define USB_H_EC2_S 21 863 /** USB_H_DEVADDR2 : R/W; bitpos: [29:22]; default: 0; 864 * Device Address . This field selects the specific device serving as the data 865 * source or sink. 866 */ 867 #define USB_H_DEVADDR2 0x0000007F 868 #define USB_H_DEVADDR2_M (USB_H_DEVADDR2_V << USB_H_DEVADDR2_S) 869 #define USB_H_DEVADDR2_V 0x0000007F 870 #define USB_H_DEVADDR2_S 22 871 /** USB_H_ODDFRM2 : R/W; bitpos: [29]; default: 0; 872 * Odd Frame 873 * 1'b0: Even (micro)Frame 874 * 1'b1: Odd (micro)Frame 875 */ 876 #define USB_H_ODDFRM2 (BIT(29)) 877 #define USB_H_ODDFRM2_M (USB_H_ODDFRM2_V << USB_H_ODDFRM2_S) 878 #define USB_H_ODDFRM2_V 0x00000001 879 #define USB_H_ODDFRM2_S 29 880 /** USB_H_CHDIS2 : R/W; bitpos: [30]; default: 0; 881 * Channel Disable 882 * 0x0 : Transmit/Recieve norma 883 * 0x1 : Stop transmitting/receiving data on channel 884 */ 885 #define USB_H_CHDIS2 (BIT(30)) 886 #define USB_H_CHDIS2_M (USB_H_CHDIS2_V << USB_H_CHDIS2_S) 887 #define USB_H_CHDIS2_V 0x00000001 888 #define USB_H_CHDIS2_S 30 889 /** USB_H_CHENA2 : R/W; bitpos: [31]; default: 0; 890 * Channel Enable 891 * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is 892 * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is 893 * disabled 894 * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure 895 * and data buffer with data is set up and this channel can access the descriptor. If 896 * Scatter/Gather mode is disabled, indicates that the channel is enabled 897 */ 898 #define USB_H_CHENA2 (BIT(31)) 899 #define USB_H_CHENA2_M (USB_H_CHENA2_V << USB_H_CHENA2_S) 900 #define USB_H_CHENA2_V 0x00000001 901 #define USB_H_CHENA2_S 31 902 903 904 /** USB_HCDMA2_REG register 905 * Host Channel 2 DMA Address Register 906 */ 907 #define USB_HCDMA2_REG (SOC_DPORT_USB_BASE + 0x554) 908 /** USB_H_DMAADDR2 : R/W; bitpos: [32:0]; default: 0; 909 * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: 910 * [31:9]: DMA Address 911 * [8:3]: Current Transfer Desc 912 * [2:0]: Reserved 913 */ 914 #define USB_H_DMAADDR2 0xFFFFFFFF 915 #define USB_H_DMAADDR2_M (USB_H_DMAADDR2_V << USB_H_DMAADDR2_S) 916 #define USB_H_DMAADDR2_V 0xFFFFFFFF 917 #define USB_H_DMAADDR2_S 0 918 919 920 /** USB_HCCHAR3_REG register 921 * Host Channel 3 Characteristics Register 922 */ 923 #define USB_HCCHAR3_REG (SOC_DPORT_USB_BASE + 0x560) 924 /** USB_H_MPS3 : R/W; bitpos: [11:0]; default: 0; 925 * Maximum Packet Size. 926 */ 927 #define USB_H_MPS3 0x000007FF 928 #define USB_H_MPS3_M (USB_H_MPS3_V << USB_H_MPS3_S) 929 #define USB_H_MPS3_V 0x000007FF 930 #define USB_H_MPS3_S 0 931 /** USB_H_EPNUM3 : R/W; bitpos: [15:11]; default: 0; 932 * Endpoint Number. 933 */ 934 #define USB_H_EPNUM3 0x0000000F 935 #define USB_H_EPNUM3_M (USB_H_EPNUM3_V << USB_H_EPNUM3_S) 936 #define USB_H_EPNUM3_V 0x0000000F 937 #define USB_H_EPNUM3_S 11 938 /** USB_H_EPDIR3 : R/W; bitpos: [15]; default: 0; 939 * 1'b0: OUT 940 * 1'b1: IN 941 */ 942 #define USB_H_EPDIR3 (BIT(15)) 943 #define USB_H_EPDIR3_M (USB_H_EPDIR3_V << USB_H_EPDIR3_S) 944 #define USB_H_EPDIR3_V 0x00000001 945 #define USB_H_EPDIR3_S 15 946 /** USB_H_LSPDDEV3 : R/W; bitpos: [17]; default: 0; 947 * 0x0: Not Communicating with low speed device 948 * 0x1: Communicating with low speed device 949 */ 950 #define USB_H_LSPDDEV3 (BIT(17)) 951 #define USB_H_LSPDDEV3_M (USB_H_LSPDDEV3_V << USB_H_LSPDDEV3_S) 952 #define USB_H_LSPDDEV3_V 0x00000001 953 #define USB_H_LSPDDEV3_S 17 954 /** USB_H_EPTYPE3 : R/W; bitpos: [20:18]; default: 0; 955 * 0x0 (CTRL): Contro 956 * 0x1 (ISOC): Isochronous 957 * 0x2 (BULK): Bulk 958 * 0x3 (INTERR): Interrupt 959 */ 960 #define USB_H_EPTYPE3 0x00000003 961 #define USB_H_EPTYPE3_M (USB_H_EPTYPE3_V << USB_H_EPTYPE3_S) 962 #define USB_H_EPTYPE3_V 0x00000003 963 #define USB_H_EPTYPE3_S 18 964 /** USB_H_EC3 : R/W; bitpos: [21]; default: 0; 965 * Multi Count (MC) / Error Count(EC) 966 * 0x0 (RESERVED): Reserved. This field yields undefined result 967 * 0x1 (TRANSONE): 1 transaction 968 * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe 969 * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe 970 */ 971 #define USB_H_EC3 (BIT(21)) 972 #define USB_H_EC3_M (USB_H_EC3_V << USB_H_EC3_S) 973 #define USB_H_EC3_V 0x00000001 974 #define USB_H_EC3_S 21 975 /** USB_H_DEVADDR3 : R/W; bitpos: [29:22]; default: 0; 976 * Device Address . This field selects the specific device serving as the data 977 * source or sink. 978 */ 979 #define USB_H_DEVADDR3 0x0000007F 980 #define USB_H_DEVADDR3_M (USB_H_DEVADDR3_V << USB_H_DEVADDR3_S) 981 #define USB_H_DEVADDR3_V 0x0000007F 982 #define USB_H_DEVADDR3_S 22 983 /** USB_H_ODDFRM3 : R/W; bitpos: [29]; default: 0; 984 * Odd Frame 985 * 1'b0: Even (micro)Frame 986 * 1'b1: Odd (micro)Frame 987 */ 988 #define USB_H_ODDFRM3 (BIT(29)) 989 #define USB_H_ODDFRM3_M (USB_H_ODDFRM3_V << USB_H_ODDFRM3_S) 990 #define USB_H_ODDFRM3_V 0x00000001 991 #define USB_H_ODDFRM3_S 29 992 /** USB_H_CHDIS3 : R/W; bitpos: [30]; default: 0; 993 * Channel Disable 994 * 0x0 : Transmit/Recieve norma 995 * 0x1 : Stop transmitting/receiving data on channel 996 */ 997 #define USB_H_CHDIS3 (BIT(30)) 998 #define USB_H_CHDIS3_M (USB_H_CHDIS3_V << USB_H_CHDIS3_S) 999 #define USB_H_CHDIS3_V 0x00000001 1000 #define USB_H_CHDIS3_S 30 1001 /** USB_H_CHENA3 : R/W; bitpos: [31]; default: 0; 1002 * Channel Enable 1003 * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is 1004 * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is 1005 * disabled 1006 * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure 1007 * and data buffer with data is set up and this channel can access the descriptor. If 1008 * Scatter/Gather mode is disabled, indicates that the channel is enabled 1009 */ 1010 #define USB_H_CHENA3 (BIT(31)) 1011 #define USB_H_CHENA3_M (USB_H_CHENA3_V << USB_H_CHENA3_S) 1012 #define USB_H_CHENA3_V 0x00000001 1013 #define USB_H_CHENA3_S 31 1014 1015 1016 /** USB_HCDMA3_REG register 1017 * Host Channel 3 DMA Address Register 1018 */ 1019 #define USB_HCDMA3_REG (SOC_DPORT_USB_BASE + 0x574) 1020 /** USB_H_DMAADDR3 : R/W; bitpos: [32:0]; default: 0; 1021 * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: 1022 * [31:9]: DMA Address 1023 * [8:3]: Current Transfer Desc 1024 * [2:0]: Reserved 1025 */ 1026 #define USB_H_DMAADDR3 0xFFFFFFFF 1027 #define USB_H_DMAADDR3_M (USB_H_DMAADDR3_V << USB_H_DMAADDR3_S) 1028 #define USB_H_DMAADDR3_V 0xFFFFFFFF 1029 #define USB_H_DMAADDR3_S 0 1030 1031 1032 /** USB_HCCHAR4_REG register 1033 * Host Channel 4 Characteristics Register 1034 */ 1035 #define USB_HCCHAR4_REG (SOC_DPORT_USB_BASE + 0x580) 1036 /** USB_H_MPS4 : R/W; bitpos: [11:0]; default: 0; 1037 * Maximum Packet Size. 1038 */ 1039 #define USB_H_MPS4 0x000007FF 1040 #define USB_H_MPS4_M (USB_H_MPS4_V << USB_H_MPS4_S) 1041 #define USB_H_MPS4_V 0x000007FF 1042 #define USB_H_MPS4_S 0 1043 /** USB_H_EPNUM4 : R/W; bitpos: [15:11]; default: 0; 1044 * Endpoint Number. 1045 */ 1046 #define USB_H_EPNUM4 0x0000000F 1047 #define USB_H_EPNUM4_M (USB_H_EPNUM4_V << USB_H_EPNUM4_S) 1048 #define USB_H_EPNUM4_V 0x0000000F 1049 #define USB_H_EPNUM4_S 11 1050 /** USB_H_EPDIR4 : R/W; bitpos: [15]; default: 0; 1051 * 1'b0: OUT 1052 * 1'b1: IN 1053 */ 1054 #define USB_H_EPDIR4 (BIT(15)) 1055 #define USB_H_EPDIR4_M (USB_H_EPDIR4_V << USB_H_EPDIR4_S) 1056 #define USB_H_EPDIR4_V 0x00000001 1057 #define USB_H_EPDIR4_S 15 1058 /** USB_H_LSPDDEV4 : R/W; bitpos: [17]; default: 0; 1059 * 0x0: Not Communicating with low speed device 1060 * 0x1: Communicating with low speed device 1061 */ 1062 #define USB_H_LSPDDEV4 (BIT(17)) 1063 #define USB_H_LSPDDEV4_M (USB_H_LSPDDEV4_V << USB_H_LSPDDEV4_S) 1064 #define USB_H_LSPDDEV4_V 0x00000001 1065 #define USB_H_LSPDDEV4_S 17 1066 /** USB_H_EPTYPE4 : R/W; bitpos: [20:18]; default: 0; 1067 * 0x0 (CTRL): Contro 1068 * 0x1 (ISOC): Isochronous 1069 * 0x2 (BULK): Bulk 1070 * 0x3 (INTERR): Interrupt 1071 */ 1072 #define USB_H_EPTYPE4 0x00000003 1073 #define USB_H_EPTYPE4_M (USB_H_EPTYPE4_V << USB_H_EPTYPE4_S) 1074 #define USB_H_EPTYPE4_V 0x00000003 1075 #define USB_H_EPTYPE4_S 18 1076 /** USB_H_EC4 : R/W; bitpos: [21]; default: 0; 1077 * Multi Count (MC) / Error Count(EC) 1078 * 0x0 (RESERVED): Reserved. This field yields undefined result 1079 * 0x1 (TRANSONE): 1 transaction 1080 * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe 1081 * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe 1082 */ 1083 #define USB_H_EC4 (BIT(21)) 1084 #define USB_H_EC4_M (USB_H_EC4_V << USB_H_EC4_S) 1085 #define USB_H_EC4_V 0x00000001 1086 #define USB_H_EC4_S 21 1087 /** USB_H_DEVADDR4 : R/W; bitpos: [29:22]; default: 0; 1088 * Device Address . This field selects the specific device serving as the data 1089 * source or sink. 1090 */ 1091 #define USB_H_DEVADDR4 0x0000007F 1092 #define USB_H_DEVADDR4_M (USB_H_DEVADDR4_V << USB_H_DEVADDR4_S) 1093 #define USB_H_DEVADDR4_V 0x0000007F 1094 #define USB_H_DEVADDR4_S 22 1095 /** USB_H_ODDFRM4 : R/W; bitpos: [29]; default: 0; 1096 * Odd Frame 1097 * 1'b0: Even (micro)Frame 1098 * 1'b1: Odd (micro)Frame 1099 */ 1100 #define USB_H_ODDFRM4 (BIT(29)) 1101 #define USB_H_ODDFRM4_M (USB_H_ODDFRM4_V << USB_H_ODDFRM4_S) 1102 #define USB_H_ODDFRM4_V 0x00000001 1103 #define USB_H_ODDFRM4_S 29 1104 /** USB_H_CHDIS4 : R/W; bitpos: [30]; default: 0; 1105 * Channel Disable 1106 * 0x0 : Transmit/Recieve norma 1107 * 0x1 : Stop transmitting/receiving data on channel 1108 */ 1109 #define USB_H_CHDIS4 (BIT(30)) 1110 #define USB_H_CHDIS4_M (USB_H_CHDIS4_V << USB_H_CHDIS4_S) 1111 #define USB_H_CHDIS4_V 0x00000001 1112 #define USB_H_CHDIS4_S 30 1113 /** USB_H_CHENA4 : R/W; bitpos: [31]; default: 0; 1114 * Channel Enable 1115 * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is 1116 * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is 1117 * disabled 1118 * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure 1119 * and data buffer with data is set up and this channel can access the descriptor. If 1120 * Scatter/Gather mode is disabled, indicates that the channel is enabled 1121 */ 1122 #define USB_H_CHENA4 (BIT(31)) 1123 #define USB_H_CHENA4_M (USB_H_CHENA4_V << USB_H_CHENA4_S) 1124 #define USB_H_CHENA4_V 0x00000001 1125 #define USB_H_CHENA4_S 31 1126 1127 1128 /** USB_HCDMA4_REG register 1129 * Host Channel 4 DMA Address Register 1130 */ 1131 #define USB_HCDMA4_REG (SOC_DPORT_USB_BASE + 0x594) 1132 /** USB_H_DMAADDR4 : R/W; bitpos: [32:0]; default: 0; 1133 * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: 1134 * [31:9]: DMA Address 1135 * [8:3]: Current Transfer Desc 1136 * [2:0]: Reserved 1137 */ 1138 #define USB_H_DMAADDR4 0xFFFFFFFF 1139 #define USB_H_DMAADDR4_M (USB_H_DMAADDR4_V << USB_H_DMAADDR4_S) 1140 #define USB_H_DMAADDR4_V 0xFFFFFFFF 1141 #define USB_H_DMAADDR4_S 0 1142 1143 1144 /** USB_HCCHAR5_REG register 1145 * Host Channel 5 Characteristics Register 1146 */ 1147 #define USB_HCCHAR5_REG (SOC_DPORT_USB_BASE + 0x5a0) 1148 /** USB_H_MPS5 : R/W; bitpos: [11:0]; default: 0; 1149 * Maximum Packet Size. 1150 */ 1151 #define USB_H_MPS5 0x000007FF 1152 #define USB_H_MPS5_M (USB_H_MPS5_V << USB_H_MPS5_S) 1153 #define USB_H_MPS5_V 0x000007FF 1154 #define USB_H_MPS5_S 0 1155 /** USB_H_EPNUM5 : R/W; bitpos: [15:11]; default: 0; 1156 * Endpoint Number. 1157 */ 1158 #define USB_H_EPNUM5 0x0000000F 1159 #define USB_H_EPNUM5_M (USB_H_EPNUM5_V << USB_H_EPNUM5_S) 1160 #define USB_H_EPNUM5_V 0x0000000F 1161 #define USB_H_EPNUM5_S 11 1162 /** USB_H_EPDIR5 : R/W; bitpos: [15]; default: 0; 1163 * 1'b0: OUT 1164 * 1'b1: IN 1165 */ 1166 #define USB_H_EPDIR5 (BIT(15)) 1167 #define USB_H_EPDIR5_M (USB_H_EPDIR5_V << USB_H_EPDIR5_S) 1168 #define USB_H_EPDIR5_V 0x00000001 1169 #define USB_H_EPDIR5_S 15 1170 /** USB_H_LSPDDEV5 : R/W; bitpos: [17]; default: 0; 1171 * 0x0: Not Communicating with low speed device 1172 * 0x1: Communicating with low speed device 1173 */ 1174 #define USB_H_LSPDDEV5 (BIT(17)) 1175 #define USB_H_LSPDDEV5_M (USB_H_LSPDDEV5_V << USB_H_LSPDDEV5_S) 1176 #define USB_H_LSPDDEV5_V 0x00000001 1177 #define USB_H_LSPDDEV5_S 17 1178 /** USB_H_EPTYPE5 : R/W; bitpos: [20:18]; default: 0; 1179 * 0x0 (CTRL): Contro 1180 * 0x1 (ISOC): Isochronous 1181 * 0x2 (BULK): Bulk 1182 * 0x3 (INTERR): Interrupt 1183 */ 1184 #define USB_H_EPTYPE5 0x00000003 1185 #define USB_H_EPTYPE5_M (USB_H_EPTYPE5_V << USB_H_EPTYPE5_S) 1186 #define USB_H_EPTYPE5_V 0x00000003 1187 #define USB_H_EPTYPE5_S 18 1188 /** USB_H_EC5 : R/W; bitpos: [21]; default: 0; 1189 * Multi Count (MC) / Error Count(EC) 1190 * 0x0 (RESERVED): Reserved. This field yields undefined result 1191 * 0x1 (TRANSONE): 1 transaction 1192 * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe 1193 * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe 1194 */ 1195 #define USB_H_EC5 (BIT(21)) 1196 #define USB_H_EC5_M (USB_H_EC5_V << USB_H_EC5_S) 1197 #define USB_H_EC5_V 0x00000001 1198 #define USB_H_EC5_S 21 1199 /** USB_H_DEVADDR5 : R/W; bitpos: [29:22]; default: 0; 1200 * Device Address . This field selects the specific device serving as the data 1201 * source or sink. 1202 */ 1203 #define USB_H_DEVADDR5 0x0000007F 1204 #define USB_H_DEVADDR5_M (USB_H_DEVADDR5_V << USB_H_DEVADDR5_S) 1205 #define USB_H_DEVADDR5_V 0x0000007F 1206 #define USB_H_DEVADDR5_S 22 1207 /** USB_H_ODDFRM5 : R/W; bitpos: [29]; default: 0; 1208 * Odd Frame 1209 * 1'b0: Even (micro)Frame 1210 * 1'b1: Odd (micro)Frame 1211 */ 1212 #define USB_H_ODDFRM5 (BIT(29)) 1213 #define USB_H_ODDFRM5_M (USB_H_ODDFRM5_V << USB_H_ODDFRM5_S) 1214 #define USB_H_ODDFRM5_V 0x00000001 1215 #define USB_H_ODDFRM5_S 29 1216 /** USB_H_CHDIS5 : R/W; bitpos: [30]; default: 0; 1217 * Channel Disable 1218 * 0x0 : Transmit/Recieve norma 1219 * 0x1 : Stop transmitting/receiving data on channel 1220 */ 1221 #define USB_H_CHDIS5 (BIT(30)) 1222 #define USB_H_CHDIS5_M (USB_H_CHDIS5_V << USB_H_CHDIS5_S) 1223 #define USB_H_CHDIS5_V 0x00000001 1224 #define USB_H_CHDIS5_S 30 1225 /** USB_H_CHENA5 : R/W; bitpos: [31]; default: 0; 1226 * Channel Enable 1227 * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is 1228 * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is 1229 * disabled 1230 * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure 1231 * and data buffer with data is set up and this channel can access the descriptor. If 1232 * Scatter/Gather mode is disabled, indicates that the channel is enabled 1233 */ 1234 #define USB_H_CHENA5 (BIT(31)) 1235 #define USB_H_CHENA5_M (USB_H_CHENA5_V << USB_H_CHENA5_S) 1236 #define USB_H_CHENA5_V 0x00000001 1237 #define USB_H_CHENA5_S 31 1238 1239 1240 /** USB_HCDMA5_REG register 1241 * Host Channel 5 DMA Address Register 1242 */ 1243 #define USB_HCDMA5_REG (SOC_DPORT_USB_BASE + 0x5b4) 1244 /** USB_H_DMAADDR5 : R/W; bitpos: [32:0]; default: 0; 1245 * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: 1246 * [31:9]: DMA Address 1247 * [8:3]: Current Transfer Desc 1248 * [2:0]: Reserved 1249 */ 1250 #define USB_H_DMAADDR5 0xFFFFFFFF 1251 #define USB_H_DMAADDR5_M (USB_H_DMAADDR5_V << USB_H_DMAADDR5_S) 1252 #define USB_H_DMAADDR5_V 0xFFFFFFFF 1253 #define USB_H_DMAADDR5_S 0 1254 1255 1256 /** USB_HCCHAR6_REG register 1257 * Host Channel 6 Characteristics Register 1258 */ 1259 #define USB_HCCHAR6_REG (SOC_DPORT_USB_BASE + 0x5c0) 1260 /** USB_H_MPS6 : R/W; bitpos: [11:0]; default: 0; 1261 * Maximum Packet Size. 1262 */ 1263 #define USB_H_MPS6 0x000007FF 1264 #define USB_H_MPS6_M (USB_H_MPS6_V << USB_H_MPS6_S) 1265 #define USB_H_MPS6_V 0x000007FF 1266 #define USB_H_MPS6_S 0 1267 /** USB_H_EPNUM6 : R/W; bitpos: [15:11]; default: 0; 1268 * Endpoint Number. 1269 */ 1270 #define USB_H_EPNUM6 0x0000000F 1271 #define USB_H_EPNUM6_M (USB_H_EPNUM6_V << USB_H_EPNUM6_S) 1272 #define USB_H_EPNUM6_V 0x0000000F 1273 #define USB_H_EPNUM6_S 11 1274 /** USB_H_EPDIR6 : R/W; bitpos: [15]; default: 0; 1275 * 1'b0: OUT 1276 * 1'b1: IN 1277 */ 1278 #define USB_H_EPDIR6 (BIT(15)) 1279 #define USB_H_EPDIR6_M (USB_H_EPDIR6_V << USB_H_EPDIR6_S) 1280 #define USB_H_EPDIR6_V 0x00000001 1281 #define USB_H_EPDIR6_S 15 1282 /** USB_H_LSPDDEV6 : R/W; bitpos: [17]; default: 0; 1283 * 0x0: Not Communicating with low speed device 1284 * 0x1: Communicating with low speed device 1285 */ 1286 #define USB_H_LSPDDEV6 (BIT(17)) 1287 #define USB_H_LSPDDEV6_M (USB_H_LSPDDEV6_V << USB_H_LSPDDEV6_S) 1288 #define USB_H_LSPDDEV6_V 0x00000001 1289 #define USB_H_LSPDDEV6_S 17 1290 /** USB_H_EPTYPE6 : R/W; bitpos: [20:18]; default: 0; 1291 * 0x0 (CTRL): Contro 1292 * 0x1 (ISOC): Isochronous 1293 * 0x2 (BULK): Bulk 1294 * 0x3 (INTERR): Interrupt 1295 */ 1296 #define USB_H_EPTYPE6 0x00000003 1297 #define USB_H_EPTYPE6_M (USB_H_EPTYPE6_V << USB_H_EPTYPE6_S) 1298 #define USB_H_EPTYPE6_V 0x00000003 1299 #define USB_H_EPTYPE6_S 18 1300 /** USB_H_EC6 : R/W; bitpos: [21]; default: 0; 1301 * Multi Count (MC) / Error Count(EC) 1302 * 0x0 (RESERVED): Reserved. This field yields undefined result 1303 * 0x1 (TRANSONE): 1 transaction 1304 * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe 1305 * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe 1306 */ 1307 #define USB_H_EC6 (BIT(21)) 1308 #define USB_H_EC6_M (USB_H_EC6_V << USB_H_EC6_S) 1309 #define USB_H_EC6_V 0x00000001 1310 #define USB_H_EC6_S 21 1311 /** USB_H_DEVADDR6 : R/W; bitpos: [29:22]; default: 0; 1312 * Device Address . This field selects the specific device serving as the data 1313 * source or sink. 1314 */ 1315 #define USB_H_DEVADDR6 0x0000007F 1316 #define USB_H_DEVADDR6_M (USB_H_DEVADDR6_V << USB_H_DEVADDR6_S) 1317 #define USB_H_DEVADDR6_V 0x0000007F 1318 #define USB_H_DEVADDR6_S 22 1319 /** USB_H_ODDFRM6 : R/W; bitpos: [29]; default: 0; 1320 * Odd Frame 1321 * 1'b0: Even (micro)Frame 1322 * 1'b1: Odd (micro)Frame 1323 */ 1324 #define USB_H_ODDFRM6 (BIT(29)) 1325 #define USB_H_ODDFRM6_M (USB_H_ODDFRM6_V << USB_H_ODDFRM6_S) 1326 #define USB_H_ODDFRM6_V 0x00000001 1327 #define USB_H_ODDFRM6_S 29 1328 /** USB_H_CHDIS6 : R/W; bitpos: [30]; default: 0; 1329 * Channel Disable 1330 * 0x0 : Transmit/Recieve norma 1331 * 0x1 : Stop transmitting/receiving data on channel 1332 */ 1333 #define USB_H_CHDIS6 (BIT(30)) 1334 #define USB_H_CHDIS6_M (USB_H_CHDIS6_V << USB_H_CHDIS6_S) 1335 #define USB_H_CHDIS6_V 0x00000001 1336 #define USB_H_CHDIS6_S 30 1337 /** USB_H_CHENA6 : R/W; bitpos: [31]; default: 0; 1338 * Channel Enable 1339 * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is 1340 * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is 1341 * disabled 1342 * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure 1343 * and data buffer with data is set up and this channel can access the descriptor. If 1344 * Scatter/Gather mode is disabled, indicates that the channel is enabled 1345 */ 1346 #define USB_H_CHENA6 (BIT(31)) 1347 #define USB_H_CHENA6_M (USB_H_CHENA6_V << USB_H_CHENA6_S) 1348 #define USB_H_CHENA6_V 0x00000001 1349 #define USB_H_CHENA6_S 31 1350 1351 1352 /** USB_HCDMA6_REG register 1353 * Host Channel 6 DMA Address Register 1354 */ 1355 #define USB_HCDMA6_REG (SOC_DPORT_USB_BASE + 0x5d4) 1356 /** USB_H_DMAADDR6 : R/W; bitpos: [32:0]; default: 0; 1357 * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: 1358 * [31:9]: DMA Address 1359 * [8:3]: Current Transfer Desc 1360 * [2:0]: Reserved 1361 */ 1362 #define USB_H_DMAADDR6 0xFFFFFFFF 1363 #define USB_H_DMAADDR6_M (USB_H_DMAADDR6_V << USB_H_DMAADDR6_S) 1364 #define USB_H_DMAADDR6_V 0xFFFFFFFF 1365 #define USB_H_DMAADDR6_S 0 1366 1367 1368 /** USB_HCCHAR7_REG register 1369 * Host Channel 7 Characteristics Register 1370 */ 1371 #define USB_HCCHAR7_REG (SOC_DPORT_USB_BASE + 0x5e0) 1372 /** USB_H_MPS7 : R/W; bitpos: [11:0]; default: 0; 1373 * Maximum Packet Size. 1374 */ 1375 #define USB_H_MPS7 0x000007FF 1376 #define USB_H_MPS7_M (USB_H_MPS7_V << USB_H_MPS7_S) 1377 #define USB_H_MPS7_V 0x000007FF 1378 #define USB_H_MPS7_S 0 1379 /** USB_H_EPNUM7 : R/W; bitpos: [15:11]; default: 0; 1380 * Endpoint Number. 1381 */ 1382 #define USB_H_EPNUM7 0x0000000F 1383 #define USB_H_EPNUM7_M (USB_H_EPNUM7_V << USB_H_EPNUM7_S) 1384 #define USB_H_EPNUM7_V 0x0000000F 1385 #define USB_H_EPNUM7_S 11 1386 /** USB_H_EPDIR7 : R/W; bitpos: [15]; default: 0; 1387 * 1'b0: OUT 1388 * 1'b1: IN 1389 */ 1390 #define USB_H_EPDIR7 (BIT(15)) 1391 #define USB_H_EPDIR7_M (USB_H_EPDIR7_V << USB_H_EPDIR7_S) 1392 #define USB_H_EPDIR7_V 0x00000001 1393 #define USB_H_EPDIR7_S 15 1394 /** USB_H_LSPDDEV7 : R/W; bitpos: [17]; default: 0; 1395 * 0x0: Not Communicating with low speed device 1396 * 0x1: Communicating with low speed device 1397 */ 1398 #define USB_H_LSPDDEV7 (BIT(17)) 1399 #define USB_H_LSPDDEV7_M (USB_H_LSPDDEV7_V << USB_H_LSPDDEV7_S) 1400 #define USB_H_LSPDDEV7_V 0x00000001 1401 #define USB_H_LSPDDEV7_S 17 1402 /** USB_H_EPTYPE7 : R/W; bitpos: [20:18]; default: 0; 1403 * 0x0 (CTRL): Contro 1404 * 0x1 (ISOC): Isochronous 1405 * 0x2 (BULK): Bulk 1406 * 0x3 (INTERR): Interrupt 1407 */ 1408 #define USB_H_EPTYPE7 0x00000003 1409 #define USB_H_EPTYPE7_M (USB_H_EPTYPE7_V << USB_H_EPTYPE7_S) 1410 #define USB_H_EPTYPE7_V 0x00000003 1411 #define USB_H_EPTYPE7_S 18 1412 /** USB_H_EC7 : R/W; bitpos: [21]; default: 0; 1413 * Multi Count (MC) / Error Count(EC) 1414 * 0x0 (RESERVED): Reserved. This field yields undefined result 1415 * 0x1 (TRANSONE): 1 transaction 1416 * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe 1417 * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe 1418 */ 1419 #define USB_H_EC7 (BIT(21)) 1420 #define USB_H_EC7_M (USB_H_EC7_V << USB_H_EC7_S) 1421 #define USB_H_EC7_V 0x00000001 1422 #define USB_H_EC7_S 21 1423 /** USB_H_DEVADDR7 : R/W; bitpos: [29:22]; default: 0; 1424 * Device Address . This field selects the specific device serving as the data 1425 * source or sink. 1426 */ 1427 #define USB_H_DEVADDR7 0x0000007F 1428 #define USB_H_DEVADDR7_M (USB_H_DEVADDR7_V << USB_H_DEVADDR7_S) 1429 #define USB_H_DEVADDR7_V 0x0000007F 1430 #define USB_H_DEVADDR7_S 22 1431 /** USB_H_ODDFRM7 : R/W; bitpos: [29]; default: 0; 1432 * Odd Frame 1433 * 1'b0: Even (micro)Frame 1434 * 1'b1: Odd (micro)Frame 1435 */ 1436 #define USB_H_ODDFRM7 (BIT(29)) 1437 #define USB_H_ODDFRM7_M (USB_H_ODDFRM7_V << USB_H_ODDFRM7_S) 1438 #define USB_H_ODDFRM7_V 0x00000001 1439 #define USB_H_ODDFRM7_S 29 1440 /** USB_H_CHDIS7 : R/W; bitpos: [30]; default: 0; 1441 * Channel Disable 1442 * 0x0 : Transmit/Recieve norma 1443 * 0x1 : Stop transmitting/receiving data on channel 1444 */ 1445 #define USB_H_CHDIS7 (BIT(30)) 1446 #define USB_H_CHDIS7_M (USB_H_CHDIS7_V << USB_H_CHDIS7_S) 1447 #define USB_H_CHDIS7_V 0x00000001 1448 #define USB_H_CHDIS7_S 30 1449 /** USB_H_CHENA7 : R/W; bitpos: [31]; default: 0; 1450 * Channel Enable 1451 * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is 1452 * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is 1453 * disabled 1454 * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure 1455 * and data buffer with data is set up and this channel can access the descriptor. If 1456 * Scatter/Gather mode is disabled, indicates that the channel is enabled 1457 */ 1458 #define USB_H_CHENA7 (BIT(31)) 1459 #define USB_H_CHENA7_M (USB_H_CHENA7_V << USB_H_CHENA7_S) 1460 #define USB_H_CHENA7_V 0x00000001 1461 #define USB_H_CHENA7_S 31 1462 1463 1464 /** USB_HCDMA7_REG register 1465 * Host Channel 7 DMA Address Register 1466 */ 1467 #define USB_HCDMA7_REG (SOC_DPORT_USB_BASE + 0x5f4) 1468 /** USB_H_DMAADDR7 : R/W; bitpos: [32:0]; default: 0; 1469 * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: 1470 * [31:9]: DMA Address 1471 * [8:3]: Current Transfer Desc 1472 * [2:0]: Reserved 1473 */ 1474 #define USB_H_DMAADDR7 0xFFFFFFFF 1475 #define USB_H_DMAADDR7_M (USB_H_DMAADDR7_V << USB_H_DMAADDR7_S) 1476 #define USB_H_DMAADDR7_V 0xFFFFFFFF 1477 #define USB_H_DMAADDR7_S 0 1478 1479 1480 /** USB_DCFG_REG register 1481 * Device Configuration Register 1482 */ 1483 #define USB_DCFG_REG (SOC_DPORT_USB_BASE + 0x800) 1484 /** USB_NZSTSOUTHSHK : R/W; bitpos: [2]; default: 0; 1485 * 1'b0: Send the received OUT packet to the application (zero-length or non-zero 1486 * length) and send a handshake based on NAK and STALL bits for the endpoint in the 1487 * Devce Endpoint Control Register 1488 * 1'b1: Send a STALL handshake on a nonzero-length status OUT transaction and do not 1489 * send the received OUT packet to the application 1490 */ 1491 #define USB_NZSTSOUTHSHK (BIT(2)) 1492 #define USB_NZSTSOUTHSHK_M (USB_NZSTSOUTHSHK_V << USB_NZSTSOUTHSHK_S) 1493 #define USB_NZSTSOUTHSHK_V 0x00000001 1494 #define USB_NZSTSOUTHSHK_S 2 1495 /** USB_DEVADDR : R/W; bitpos: [11:4]; default: 0; 1496 * Device Address. 1497 */ 1498 #define USB_DEVADDR 0x0000007F 1499 #define USB_DEVADDR_M (USB_DEVADDR_V << USB_DEVADDR_S) 1500 #define USB_DEVADDR_V 0x0000007F 1501 #define USB_DEVADDR_S 4 1502 /** USB_PERFRLINT : R/W; bitpos: [13:11]; default: 0; 1503 * 0x0 (EOPF80): 80% of the (micro)Frame interval 1504 * 0x1 (EOPF85): 85% of the (micro)Frame interval 1505 * 0x2 (EOPF90): 90% of the (micro)Frame interval 1506 * 0x3 (EOPF95): 95% of the (micro)Frame interval 1507 */ 1508 #define USB_PERFRLINT 0x00000003 1509 #define USB_PERFRLINT_M (USB_PERFRLINT_V << USB_PERFRLINT_S) 1510 #define USB_PERFRLINT_V 0x00000003 1511 #define USB_PERFRLINT_S 11 1512 /** USB_ENDEVOUTNAK : R/W; bitpos: [13]; default: 0; 1513 * 1'b0:The core does not set NAK after Bulk OUT transfer complete 1514 * 1'b1: The core sets NAK after Bulk OUT transfer complete 1515 */ 1516 #define USB_ENDEVOUTNAK (BIT(13)) 1517 #define USB_ENDEVOUTNAK_M (USB_ENDEVOUTNAK_V << USB_ENDEVOUTNAK_S) 1518 #define USB_ENDEVOUTNAK_V 0x00000001 1519 #define USB_ENDEVOUTNAK_S 13 1520 /** USB_XCVRDLY : R/W; bitpos: [14]; default: 0; 1521 * 0x0 : No delay between xcvr_sel and txvalid during Device chirp 1522 * 0x1 : Enable delay between xcvr_sel and txvalid during Device chirp 1523 */ 1524 #define USB_XCVRDLY (BIT(14)) 1525 #define USB_XCVRDLY_M (USB_XCVRDLY_V << USB_XCVRDLY_S) 1526 #define USB_XCVRDLY_V 0x00000001 1527 #define USB_XCVRDLY_S 14 1528 /** USB_ERRATICINTMSK : R/W; bitpos: [15]; default: 0; 1529 * 0x0 : Early suspend interrupt is generated on erratic error 1530 * 0x1: Mask early suspend interrupt on erratic error 1531 */ 1532 #define USB_ERRATICINTMSK (BIT(15)) 1533 #define USB_ERRATICINTMSK_M (USB_ERRATICINTMSK_V << USB_ERRATICINTMSK_S) 1534 #define USB_ERRATICINTMSK_V 0x00000001 1535 #define USB_ERRATICINTMSK_S 15 1536 /** USB_EPMISCNT : R/W; bitpos: [23:18]; default: 4; 1537 * IN Endpoint Mismatch Count. 1538 */ 1539 #define USB_EPMISCNT 0x0000001F 1540 #define USB_EPMISCNT_M (USB_EPMISCNT_V << USB_EPMISCNT_S) 1541 #define USB_EPMISCNT_V 0x0000001F 1542 #define USB_EPMISCNT_S 18 1543 /** USB_DESCDMA : R/W; bitpos: [23]; default: 0; 1544 * 1'b0: Disable Scatter/Gather DMA 1545 * 1'b1: Enable Scatter/Gather DMA 1546 */ 1547 #define USB_DESCDMA (BIT(23)) 1548 #define USB_DESCDMA_M (USB_DESCDMA_V << USB_DESCDMA_S) 1549 #define USB_DESCDMA_V 0x00000001 1550 #define USB_DESCDMA_S 23 1551 /** USB_PERSCHINTVL : R/W; bitpos: [26:24]; default: 0; 1552 * Periodic Scheduling Interval 1553 * 0x0 (MF25): 25% of (micro)Frame 1554 * 0x1 (MF50): 50% of (micro)Frame 1555 * 0x2 (MF75): 75% of (micro)Frame 1556 * 0x3 (RESERVED): Reserved 1557 */ 1558 #define USB_PERSCHINTVL 0x00000003 1559 #define USB_PERSCHINTVL_M (USB_PERSCHINTVL_V << USB_PERSCHINTVL_S) 1560 #define USB_PERSCHINTVL_V 0x00000003 1561 #define USB_PERSCHINTVL_S 24 1562 /** USB_RESVALID : R/W; bitpos: [32:26]; default: 2; 1563 * This field is effective only when DCFG.Ena32KHzSusp is set. It controls the resume 1564 * period when the core resumes from suspend. 1565 * The core counts for ResValid number of clock cycles to detect a valid resume when 1566 * this bit is set 1567 */ 1568 #define USB_RESVALID 0x0000003F 1569 #define USB_RESVALID_M (USB_RESVALID_V << USB_RESVALID_S) 1570 #define USB_RESVALID_V 0x0000003F 1571 #define USB_RESVALID_S 26 1572 1573 1574 /** USB_DCTL_REG register 1575 * Device Control Register 1576 */ 1577 #define USB_DCTL_REG (SOC_DPORT_USB_BASE + 0x804) 1578 /** USB_RMTWKUPSIG : R/W; bitpos: [0]; default: 0; 1579 * 0x0 : Core does not send Remote Wakeup Signaling 1580 * 0x1 : Core sends Remote Wakeup Signalin 1581 */ 1582 #define USB_RMTWKUPSIG (BIT(0)) 1583 #define USB_RMTWKUPSIG_M (USB_RMTWKUPSIG_V << USB_RMTWKUPSIG_S) 1584 #define USB_RMTWKUPSIG_V 0x00000001 1585 #define USB_RMTWKUPSIG_S 0 1586 /** USB_SFTDISCON : R/W; bitpos: [1]; default: 0; 1587 * 1'b0: Normal operation. When this bit is cleared after a soft disconnect, the core 1588 * drives the phy_opmode_o signal on the UTMI+ to 2'b00, which generates a device 1589 * connect event to the USB host. When the device is reconnected, the USB host 1590 * restarts device enumeration 1591 * 1'b1: The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which 1592 * generates a device disconnect event to the USB host 1593 */ 1594 #define USB_SFTDISCON (BIT(1)) 1595 #define USB_SFTDISCON_M (USB_SFTDISCON_V << USB_SFTDISCON_S) 1596 #define USB_SFTDISCON_V 0x00000001 1597 #define USB_SFTDISCON_S 1 1598 /** USB_GNPINNAKSTS : RO; bitpos: [2]; default: 0; 1599 * 0x0 : A handshake is sent out based on the data availability in the transmit FIFO 1600 * 0x1 : A NAK handshake is sent out on all non-periodic IN endpoints, irrespective 1601 * of the data availability in the transmit FIFO 1602 */ 1603 #define USB_GNPINNAKSTS (BIT(2)) 1604 #define USB_GNPINNAKSTS_M (USB_GNPINNAKSTS_V << USB_GNPINNAKSTS_S) 1605 #define USB_GNPINNAKSTS_V 0x00000001 1606 #define USB_GNPINNAKSTS_S 2 1607 /** USB_GOUTNAKSTS : RO; bitpos: [3]; default: 0; 1608 * 0x0 : A handshake is sent based on the FIFO Status and the NAK and STALL bit 1609 * settings 1610 * 0x1 : No data is written to the RxFIFO, irrespective of space availability. Sends 1611 * a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT 1612 * packets are dropped 1613 */ 1614 #define USB_GOUTNAKSTS (BIT(3)) 1615 #define USB_GOUTNAKSTS_M (USB_GOUTNAKSTS_V << USB_GOUTNAKSTS_S) 1616 #define USB_GOUTNAKSTS_V 0x00000001 1617 #define USB_GOUTNAKSTS_S 3 1618 /** USB_TSTCTL : R/W; bitpos: [7:4]; default: 0; 1619 * 0x0: Test mode disabled 1620 * 0x1: Test_J mode 1621 * 0x2 : Test_K mode 1622 * 0x3 : Test_SE0_NAK mode 1623 * 0x4 : Test_Packet mode 1624 * 0x5 : Test_force_Enable 1625 */ 1626 #define USB_TSTCTL 0x00000007 1627 #define USB_TSTCTL_M (USB_TSTCTL_V << USB_TSTCTL_S) 1628 #define USB_TSTCTL_V 0x00000007 1629 #define USB_TSTCTL_S 4 1630 /** USB_SGNPINNAK : WO; bitpos: [7]; default: 0; 1631 * Set Global Non-periodic IN NAK. A write to this field sets the Global Non-periodic 1632 * IN NAK.The application uses this bit to send a NAK handshake on all non-periodic IN 1633 * endpoints. The core can also Set this bit when a timeout condition is detected on a 1634 * non-periodic endpoint in shared FIFO operation. The application must Set this bit 1635 * only after making sure that the Global IN NAK Effective bit in the Core Interrupt 1636 * Register (GINTSTS.GINNakEff) is cleared 1637 */ 1638 #define USB_SGNPINNAK (BIT(7)) 1639 #define USB_SGNPINNAK_M (USB_SGNPINNAK_V << USB_SGNPINNAK_S) 1640 #define USB_SGNPINNAK_V 0x00000001 1641 #define USB_SGNPINNAK_S 7 1642 /** USB_CGNPINNAK : WO; bitpos: [8]; default: 0; 1643 * Clear Global Non-periodic IN NAK. A write to this field clears the Global 1644 * Non-periodic IN NAK. 1645 */ 1646 #define USB_CGNPINNAK (BIT(8)) 1647 #define USB_CGNPINNAK_M (USB_CGNPINNAK_V << USB_CGNPINNAK_S) 1648 #define USB_CGNPINNAK_V 0x00000001 1649 #define USB_CGNPINNAK_S 8 1650 /** USB_SGOUTNAK : WO; bitpos: [9]; default: 0; 1651 * Set Global OUT NAK. A write to this field sets the Global OUT NAK. The application 1652 * uses this bit to send a NAK handshake on all OUT endpoints. The application must 1653 * set the this bit only after making sure that the Global OUT NAK Effective bit in 1654 * the Core Interrupt Register (GINTSTS.GOUTNakEff) is cleared. 1655 */ 1656 #define USB_SGOUTNAK (BIT(9)) 1657 #define USB_SGOUTNAK_M (USB_SGOUTNAK_V << USB_SGOUTNAK_S) 1658 #define USB_SGOUTNAK_V 0x00000001 1659 #define USB_SGOUTNAK_S 9 1660 /** USB_CGOUTNAK : WO; bitpos: [10]; default: 0; 1661 * Clear Global OUT NAK. A write to this field clears the Global OUT NAK. 1662 */ 1663 #define USB_CGOUTNAK (BIT(10)) 1664 #define USB_CGOUTNAK_M (USB_CGOUTNAK_V << USB_CGOUTNAK_S) 1665 #define USB_CGOUTNAK_V 0x00000001 1666 #define USB_CGOUTNAK_S 10 1667 /** USB_PWRONPRGDONE : R/W; bitpos: [11]; default: 0; 1668 * 1'b0: Power-On Programming not done 1669 * 1'b1: Power-On Programming Done 1670 */ 1671 #define USB_PWRONPRGDONE (BIT(11)) 1672 #define USB_PWRONPRGDONE_M (USB_PWRONPRGDONE_V << USB_PWRONPRGDONE_S) 1673 #define USB_PWRONPRGDONE_V 0x00000001 1674 #define USB_PWRONPRGDONE_S 11 1675 /** USB_GMC : R/W; bitpos: [15:13]; default: 1; 1676 * Global Multi Count. applicable only for Scatter/Gather DMA mode 1677 * 0x0 : Invalid 1678 * 0x1 : 1 packet 1679 * 0x2 : 2 packets 1680 * 0x3 : 3 packets 1681 */ 1682 #define USB_GMC 0x00000003 1683 #define USB_GMC_M (USB_GMC_V << USB_GMC_S) 1684 #define USB_GMC_V 0x00000003 1685 #define USB_GMC_S 13 1686 /** USB_IGNRFRMNUM : R/W; bitpos: [15]; default: 0; 1687 * 0: The core transmits the packets only in the frame number in which they are 1688 * intended to be transmitted 1689 * 1: The core ignores the frame number, sending packets immediately as the packets 1690 * are ready 1691 */ 1692 #define USB_IGNRFRMNUM (BIT(15)) 1693 #define USB_IGNRFRMNUM_M (USB_IGNRFRMNUM_V << USB_IGNRFRMNUM_S) 1694 #define USB_IGNRFRMNUM_V 0x00000001 1695 #define USB_IGNRFRMNUM_S 15 1696 /** USB_NAKONBBLE : R/W; bitpos: [16]; default: 0; 1697 * 1'b0: Disable NAK on Babble Error 1698 * 1'b1: NAK on Babble Error 1699 */ 1700 #define USB_NAKONBBLE (BIT(16)) 1701 #define USB_NAKONBBLE_M (USB_NAKONBBLE_V << USB_NAKONBBLE_S) 1702 #define USB_NAKONBBLE_V 0x00000001 1703 #define USB_NAKONBBLE_S 16 1704 /** USB_ENCOUNTONBNA : R/W; bitpos: [17]; default: 0; 1705 * 1'b0: After receiving BNA interrupt,the core disables the endpoint. When the 1706 * endpoint is re-enabled by the application,the core starts processing from the 1707 * DOEPDMA descriptor 1708 * 1'b1: After receiving BNA interrupt, the core disables the endpoint. When the 1709 * endpoint is re-enabled by the application, the core starts processing from the 1710 * descriptor that received the BNA interrupt 1711 */ 1712 #define USB_ENCOUNTONBNA (BIT(17)) 1713 #define USB_ENCOUNTONBNA_M (USB_ENCOUNTONBNA_V << USB_ENCOUNTONBNA_S) 1714 #define USB_ENCOUNTONBNA_V 0x00000001 1715 #define USB_ENCOUNTONBNA_S 17 1716 /** USB_DEEPSLEEPBESLREJECT : R/W; bitpos: [18]; default: 0; 1717 * 1'b0: Deep Sleep BESL Reject feature is disabled 1718 * 1'b1: Deep Sleep BESL Reject feature is enabled 1719 */ 1720 #define USB_DEEPSLEEPBESLREJECT (BIT(18)) 1721 #define USB_DEEPSLEEPBESLREJECT_M (USB_DEEPSLEEPBESLREJECT_V << USB_DEEPSLEEPBESLREJECT_S) 1722 #define USB_DEEPSLEEPBESLREJECT_V 0x00000001 1723 #define USB_DEEPSLEEPBESLREJECT_S 18 1724 1725 1726 /** USB_DVBUSDIS_REG register 1727 * Device VBUS Discharge Time Register 1728 */ 1729 #define USB_DVBUSDIS_REG (SOC_DPORT_USB_BASE + 0x828) 1730 /** USB_DVBUSDIS : R/W; bitpos: [16:0]; default: 6103; 1731 * Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals 1732 * (VBUS discharge time in PHY clocks) / 1, 024. The value you use depends whether the 1733 * PHY is operating at 30MHz (16-bit data width) or 60 MHz (8-bit data width). 1734 * Depending on your VBUS load, this value can need adjustment. 1735 */ 1736 #define USB_DVBUSDIS 0x0000FFFF 1737 #define USB_DVBUSDIS_M (USB_DVBUSDIS_V << USB_DVBUSDIS_S) 1738 #define USB_DVBUSDIS_V 0x0000FFFF 1739 #define USB_DVBUSDIS_S 0 1740 1741 1742 /** USB_DVBUSPULSE_REG register 1743 * Device VBUS Pulsing Time Register 1744 */ 1745 #define USB_DVBUSPULSE_REG (SOC_DPORT_USB_BASE + 0x82c) 1746 /** USB_DVBUSPULSE : R/W; bitpos: [12:0]; default: 1464; 1747 * Specifies the VBUS pulsing time during SRP. This value equals (VBUS pulsing time in 1748 * PHY clocks) / 1, 024 The value you use depends whether the PHY is operating at 1749 * 30MHz (16-bit data width) or 60 MHz (8-bit data width). 1750 */ 1751 #define USB_DVBUSPULSE 0x00000FFF 1752 #define USB_DVBUSPULSE_M (USB_DVBUSPULSE_V << USB_DVBUSPULSE_S) 1753 #define USB_DVBUSPULSE_V 0x00000FFF 1754 #define USB_DVBUSPULSE_S 0 1755 1756 1757 /** USB_DTHRCTL_REG register 1758 * Device Threshold Control Register 1759 */ 1760 #define USB_DTHRCTL_REG (SOC_DPORT_USB_BASE + 0x830) 1761 /** USB_NONISOTHREN : R/W; bitpos: [0]; default: 0; 1762 * Non-ISO IN Endpoints Threshold Enable 1763 * 0x0 : No thresholding 1764 * 0x1 : Enable thresholding for non-isochronous IN endpoints 1765 */ 1766 #define USB_NONISOTHREN (BIT(0)) 1767 #define USB_NONISOTHREN_M (USB_NONISOTHREN_V << USB_NONISOTHREN_S) 1768 #define USB_NONISOTHREN_V 0x00000001 1769 #define USB_NONISOTHREN_S 0 1770 /** USB_ISOTHREN : R/W; bitpos: [1]; default: 0; 1771 * ISO IN Endpoints Threshold Enable 1772 * 0x0 : No thresholding 1773 * 0x1 : Enables thresholding for isochronous IN endpoints 1774 */ 1775 #define USB_ISOTHREN (BIT(1)) 1776 #define USB_ISOTHREN_M (USB_ISOTHREN_V << USB_ISOTHREN_S) 1777 #define USB_ISOTHREN_V 0x00000001 1778 #define USB_ISOTHREN_S 1 1779 /** USB_TXTHRLEN : R/W; bitpos: [11:2]; default: 8; 1780 * This field specifies Transmit thresholding size in DWORDS. This also forms the MAC 1781 * threshold and specifies the amount of data in bytes to be in the corresponding 1782 * endpoint transmit FIFO, before the core can start transmit on the USB. The 1783 * threshold length has to be at least eight DWORDS when the value of AHBThrRatio is 1784 * 2'h00. In case the AHBThrRatio is non zero the application needs to ensure that the 1785 * AHB Threshold value does not go below the recommended eight DWORD. This field 1786 * controls both isochronous and non-isochronous IN endpoint thresholds. The 1787 * recommended value for ThrLen is to be the same as the programmed AHB Burst Length 1788 * (GAHBCFG.HBstLen). 1789 */ 1790 #define USB_TXTHRLEN 0x000001FF 1791 #define USB_TXTHRLEN_M (USB_TXTHRLEN_V << USB_TXTHRLEN_S) 1792 #define USB_TXTHRLEN_V 0x000001FF 1793 #define USB_TXTHRLEN_S 2 1794 /** USB_AHBTHRRATIO : R/W; bitpos: [13:11]; default: 0; 1795 * 2'b00: AHB threshold = MAC threshold 1796 * 2'b01: AHB threshold = MAC threshold/2 1797 * 2'b10: AHB threshold = MAC threshold/4 1798 * 2'b11: AHB threshold = MAC threshold/8 1799 */ 1800 #define USB_AHBTHRRATIO 0x00000003 1801 #define USB_AHBTHRRATIO_M (USB_AHBTHRRATIO_V << USB_AHBTHRRATIO_S) 1802 #define USB_AHBTHRRATIO_V 0x00000003 1803 #define USB_AHBTHRRATIO_S 11 1804 /** USB_RXTHREN : R/W; bitpos: [16]; default: 0; 1805 * 0x0 : Disable thresholding 1806 * 0x1 : Enable thresholding in the receive direction 1807 */ 1808 #define USB_RXTHREN (BIT(16)) 1809 #define USB_RXTHREN_M (USB_RXTHREN_V << USB_RXTHREN_S) 1810 #define USB_RXTHREN_V 0x00000001 1811 #define USB_RXTHREN_S 16 1812 /** USB_RXTHRLEN : R/W; bitpos: [26:17]; default: 1; 1813 * Receive Threshold Length. This field specifies Receive thresholding size in 1814 * DWORDS. This field also specifies the amount of data received on the USB before the 1815 * core can start transmitting on the AHB. The threshold length has to be at least 1816 * eight DWORDS. The recommended value for ThrLen is to be the same as the programmed 1817 * AHB Burst Length(GAHBCFG.HBstLen). 1818 */ 1819 #define USB_RXTHRLEN 0x000001FF 1820 #define USB_RXTHRLEN_M (USB_RXTHRLEN_V << USB_RXTHRLEN_S) 1821 #define USB_RXTHRLEN_V 0x000001FF 1822 #define USB_RXTHRLEN_S 17 1823 /** USB_ARBPRKEN : R/W; bitpos: [27]; default: 1; 1824 * 0x0 : Disable DMA arbiter parking 1825 * 0x1 : Enable DMA arbiter parking for IN endpoints 1826 */ 1827 #define USB_ARBPRKEN (BIT(27)) 1828 #define USB_ARBPRKEN_M (USB_ARBPRKEN_V << USB_ARBPRKEN_S) 1829 #define USB_ARBPRKEN_V 0x00000001 1830 #define USB_ARBPRKEN_S 27 1831 1832 1833 /** USB_DIEPCTL0_REG register 1834 * Device Control IN Endpoint $n Control Register 1835 */ 1836 #define USB_DIEPCTL0_REG (SOC_DPORT_USB_BASE + 0x900) 1837 /** USB_D_MPS0 : R/W; bitpos: [2:0]; default: 0; 1838 * Maximum Packet Size 1839 * 0x0 : 64 bytes 1840 * 0x1 : 32 bytes 1841 * 0x2 : 16 bytes 1842 * 0x3 : 8 bytes 1843 */ 1844 #define USB_D_MPS0 0x00000003 1845 #define USB_D_MPS0_M (USB_D_MPS0_V << USB_D_MPS0_S) 1846 #define USB_D_MPS0_V 0x00000003 1847 #define USB_D_MPS0_S 0 1848 /** USB_D_USBACTEP0 : RO; bitpos: [15]; default: 1; 1849 * USB Active Endpoint 1850 * 0x1 : Control endpoint is always active 1851 */ 1852 #define USB_D_USBACTEP0 (BIT(15)) 1853 #define USB_D_USBACTEP0_M (USB_D_USBACTEP0_V << USB_D_USBACTEP0_S) 1854 #define USB_D_USBACTEP0_V 0x00000001 1855 #define USB_D_USBACTEP0_S 15 1856 /** USB_D_NAKSTS0 : RO; bitpos: [17]; default: 0; 1857 * NAK Status 1858 * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status 1859 * 0x1 : The core is transmitting NAK handshakes on this endpoint 1860 */ 1861 #define USB_D_NAKSTS0 (BIT(17)) 1862 #define USB_D_NAKSTS0_M (USB_D_NAKSTS0_V << USB_D_NAKSTS0_S) 1863 #define USB_D_NAKSTS0_V 0x00000001 1864 #define USB_D_NAKSTS0_S 17 1865 /** USB_D_EPTYPE0 : RO; bitpos: [20:18]; default: 0; 1866 * Endpoint Type 1867 * 0x0 : Endpoint Control 0 1868 */ 1869 #define USB_D_EPTYPE0 0x00000003 1870 #define USB_D_EPTYPE0_M (USB_D_EPTYPE0_V << USB_D_EPTYPE0_S) 1871 #define USB_D_EPTYPE0_V 0x00000003 1872 #define USB_D_EPTYPE0_S 18 1873 /** USB_D_STALL0 : R/W; bitpos: [21]; default: 0; 1874 * The application can only set this bit, and the core clears it 1875 * 0x0 : No Stall 1876 * 0x1 : Stall Handshake 1877 */ 1878 #define USB_D_STALL0 (BIT(21)) 1879 #define USB_D_STALL0_M (USB_D_STALL0_V << USB_D_STALL0_S) 1880 #define USB_D_STALL0_V 0x00000001 1881 #define USB_D_STALL0_S 21 1882 /** USB_D_TXFNUM0 : R/W; bitpos: [26:22]; default: 0; 1883 * TxFIFO Number. 1884 */ 1885 #define USB_D_TXFNUM0 0x0000000F 1886 #define USB_D_TXFNUM0_M (USB_D_TXFNUM0_V << USB_D_TXFNUM0_S) 1887 #define USB_D_TXFNUM0_V 0x0000000F 1888 #define USB_D_TXFNUM0_S 22 1889 /** USB_D_CNAK0 : WO; bitpos: [26]; default: 0; 1890 * A write to this bit clears the NAK bit for the endpoint 1891 * 0x0 : No action 1892 * 0x1 : Clear NAK 1893 */ 1894 #define USB_D_CNAK0 (BIT(26)) 1895 #define USB_D_CNAK0_M (USB_D_CNAK0_V << USB_D_CNAK0_S) 1896 #define USB_D_CNAK0_V 0x00000001 1897 #define USB_D_CNAK0_S 26 1898 /** USB_DI_SNAK0 : WO; bitpos: [27]; default: 0; 1899 * A write to this bit sets the NAK bit for the endpoint 1900 * 0x0 : No action 1901 * 0x1 : Set NAK 1902 */ 1903 #define USB_DI_SNAK0 (BIT(27)) 1904 #define USB_DI_SNAK0_M (USB_DI_SNAK0_V << USB_DI_SNAK0_S) 1905 #define USB_DI_SNAK0_V 0x00000001 1906 #define USB_DI_SNAK0_S 27 1907 /** USB_D_EPDIS0 : R/W; bitpos: [30]; default: 0; 1908 * Endpoint Disable 1909 * 0x0 : No action 1910 * 0x1 : Disabled Endpoint 1911 */ 1912 #define USB_D_EPDIS0 (BIT(30)) 1913 #define USB_D_EPDIS0_M (USB_D_EPDIS0_V << USB_D_EPDIS0_S) 1914 #define USB_D_EPDIS0_V 0x00000001 1915 #define USB_D_EPDIS0_S 30 1916 /** USB_D_EPENA0 : R/W; bitpos: [31]; default: 0; 1917 * Endpoint Enable 1918 * 0x0 : No action 1919 * 0x1 : Enable Endpoint 1920 */ 1921 #define USB_D_EPENA0 (BIT(31)) 1922 #define USB_D_EPENA0_M (USB_D_EPENA0_V << USB_D_EPENA0_S) 1923 #define USB_D_EPENA0_V 0x00000001 1924 #define USB_D_EPENA0_S 31 1925 1926 1927 /** USB_DIEPTSIZ0_REG register 1928 * Device IN Endpoint 0 Transfer Size Register 1929 */ 1930 #define USB_DIEPTSIZ0_REG (SOC_DPORT_USB_BASE + 0x910) 1931 /** USB_D_XFERSIZE0 : R/W; bitpos: [7:0]; default: 0; 1932 * Transfer Size 1933 * IN Endpoints: The core decrements this field every time a packet from the external 1934 * memory is written to the TxFIFO 1935 * OUT Endpoints: The core decrements this field every time a packet is read from the 1936 * RxFIFO and written to the external memory 1937 */ 1938 #define USB_D_XFERSIZE0 0x0000007F 1939 #define USB_D_XFERSIZE0_M (USB_D_XFERSIZE0_V << USB_D_XFERSIZE0_S) 1940 #define USB_D_XFERSIZE0_V 0x0000007F 1941 #define USB_D_XFERSIZE0_S 0 1942 /** USB_D_PKTCNT0 : R/W; bitpos: [21:19]; default: 0; 1943 * Packet Count 1944 * IN Endpoints : This field is decremented every time a packet (maximum size or short 1945 * packet) is read from the TxFIFO 1946 * OUT Endpoints: This field is decremented every time a packet (maximum size or short 1947 * packet) is written to the RxFIFO 1948 */ 1949 #define USB_D_PKTCNT0 0x00000003 1950 #define USB_D_PKTCNT0_M (USB_D_PKTCNT0_V << USB_D_PKTCNT0_S) 1951 #define USB_D_PKTCNT0_V 0x00000003 1952 #define USB_D_PKTCNT0_S 19 1953 1954 1955 /** USB_DIEPDMA0_REG register 1956 * Device IN Endpoint 0 DMA Address Register 1957 */ 1958 #define USB_DIEPDMA0_REG (SOC_DPORT_USB_BASE + 0x914) 1959 /** USB_D_DMAADDR0 : R/W; bitpos: [32:0]; default: 0; 1960 * This field holds the start address of the external memory for storing or fetching 1961 * endpoint data. 1962 */ 1963 #define USB_D_DMAADDR0 0xFFFFFFFF 1964 #define USB_D_DMAADDR0_M (USB_D_DMAADDR0_V << USB_D_DMAADDR0_S) 1965 #define USB_D_DMAADDR0_V 0xFFFFFFFF 1966 #define USB_D_DMAADDR0_S 0 1967 1968 1969 /** USB_DIEPCTL1_REG register 1970 * Device Control IN Endpoint $n Control Register 1971 */ 1972 #define USB_DIEPCTL1_REG (SOC_DPORT_USB_BASE + 0x920) 1973 /** USB_D_MPS1 : R/W; bitpos: [2:0]; default: 0; 1974 * Maximum Packet Size 1975 * 0x0 : 64 bytes 1976 * 0x1 : 32 bytes 1977 * 0x2 : 16 bytes 1978 * 0x3 : 8 bytes 1979 */ 1980 #define USB_D_MPS1 0x00000003 1981 #define USB_D_MPS1_M (USB_D_MPS1_V << USB_D_MPS1_S) 1982 #define USB_D_MPS1_V 0x00000003 1983 #define USB_D_MPS1_S 0 1984 /** USB_D_USBACTEP1 : RO; bitpos: [15]; default: 1; 1985 * USB Active Endpoint 1986 * 0x1 : Control endpoint is always active 1987 */ 1988 #define USB_D_USBACTEP1 (BIT(15)) 1989 #define USB_D_USBACTEP1_M (USB_D_USBACTEP1_V << USB_D_USBACTEP1_S) 1990 #define USB_D_USBACTEP1_V 0x00000001 1991 #define USB_D_USBACTEP1_S 15 1992 /** USB_D_NAKSTS1 : RO; bitpos: [17]; default: 0; 1993 * NAK Status 1994 * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status 1995 * 0x1 : The core is transmitting NAK handshakes on this endpoint 1996 */ 1997 #define USB_D_NAKSTS1 (BIT(17)) 1998 #define USB_D_NAKSTS1_M (USB_D_NAKSTS1_V << USB_D_NAKSTS1_S) 1999 #define USB_D_NAKSTS1_V 0x00000001 2000 #define USB_D_NAKSTS1_S 17 2001 /** USB_D_EPTYPE1 : RO; bitpos: [20:18]; default: 0; 2002 * Endpoint Type 2003 * 0x0 : Endpoint Control 0 2004 */ 2005 #define USB_D_EPTYPE1 0x00000003 2006 #define USB_D_EPTYPE1_M (USB_D_EPTYPE1_V << USB_D_EPTYPE1_S) 2007 #define USB_D_EPTYPE1_V 0x00000003 2008 #define USB_D_EPTYPE1_S 18 2009 /** USB_D_STALL1 : R/W; bitpos: [21]; default: 0; 2010 * The application can only set this bit, and the core clears it 2011 * 0x0 : No Stall 2012 * 0x1 : Stall Handshake 2013 */ 2014 #define USB_D_STALL1 (BIT(21)) 2015 #define USB_D_STALL1_M (USB_D_STALL1_V << USB_D_STALL1_S) 2016 #define USB_D_STALL1_V 0x00000001 2017 #define USB_D_STALL1_S 21 2018 /** USB_D_TXFNUM1 : R/W; bitpos: [26:22]; default: 0; 2019 * TxFIFO Number. 2020 */ 2021 #define USB_D_TXFNUM1 0x0000000F 2022 #define USB_D_TXFNUM1_M (USB_D_TXFNUM1_V << USB_D_TXFNUM1_S) 2023 #define USB_D_TXFNUM1_V 0x0000000F 2024 #define USB_D_TXFNUM1_S 22 2025 /** USB_D_CNAK1 : WO; bitpos: [26]; default: 0; 2026 * A write to this bit clears the NAK bit for the endpoint 2027 * 0x0 : No action 2028 * 0x1 : Clear NAK 2029 */ 2030 #define USB_D_CNAK1 (BIT(26)) 2031 #define USB_D_CNAK1_M (USB_D_CNAK1_V << USB_D_CNAK1_S) 2032 #define USB_D_CNAK1_V 0x00000001 2033 #define USB_D_CNAK1_S 26 2034 /** USB_DI_SNAK1 : WO; bitpos: [27]; default: 0; 2035 * A write to this bit sets the NAK bit for the endpoint 2036 * 0x0 : No action 2037 * 0x1 : Set NAK 2038 */ 2039 #define USB_DI_SNAK1 (BIT(27)) 2040 #define USB_DI_SNAK1_M (USB_DI_SNAK1_V << USB_DI_SNAK1_S) 2041 #define USB_DI_SNAK1_V 0x00000001 2042 #define USB_DI_SNAK1_S 27 2043 /** USB_DI_SETD0PID1 : WO; bitpos: [28]; default: 0; 2044 * Set DATA0 PID 2045 */ 2046 #define USB_DI_SETD0PID1 (BIT(28)) 2047 #define USB_DI_SETD0PID1_M (USB_DI_SETD0PID1_V << USB_DI_SETD0PID1_S) 2048 #define USB_DI_SETD0PID1_V 0x00000001 2049 #define USB_DI_SETD0PID1_S 28 2050 /** USB_DI_SETD1PID1 : WO; bitpos: [29]; default: 0; 2051 * Set DATA1 PID 2052 */ 2053 #define USB_DI_SETD1PID1 (BIT(29)) 2054 #define USB_DI_SETD1PID1_M (USB_DI_SETD1PID1_V << USB_DI_SETD1PID1_S) 2055 #define USB_DI_SETD1PID1_V 0x00000001 2056 #define USB_DI_SETD1PID1_S 29 2057 /** USB_D_EPDIS1 : R/W; bitpos: [30]; default: 0; 2058 * Endpoint Disable 2059 * 0x0 : No action 2060 * 0x1 : Disabled Endpoint 2061 */ 2062 #define USB_D_EPDIS1 (BIT(30)) 2063 #define USB_D_EPDIS1_M (USB_D_EPDIS1_V << USB_D_EPDIS1_S) 2064 #define USB_D_EPDIS1_V 0x00000001 2065 #define USB_D_EPDIS1_S 30 2066 /** USB_D_EPENA1 : R/W; bitpos: [31]; default: 0; 2067 * Endpoint Enable 2068 * 0x0 : No action 2069 * 0x1 : Enable Endpoint 2070 */ 2071 #define USB_D_EPENA1 (BIT(31)) 2072 #define USB_D_EPENA1_M (USB_D_EPENA1_V << USB_D_EPENA1_S) 2073 #define USB_D_EPENA1_V 0x00000001 2074 #define USB_D_EPENA1_S 31 2075 2076 2077 /** USB_DIEPTSIZ1_REG register 2078 * Device IN Endpoint 1 Transfer Size Register 2079 */ 2080 #define USB_DIEPTSIZ1_REG (SOC_DPORT_USB_BASE + 0x930) 2081 /** USB_D_XFERSIZE1 : R/W; bitpos: [7:0]; default: 0; 2082 * Transfer Size 2083 * IN Endpoints: The core decrements this field every time a packet from the external 2084 * memory is written to the TxFIFO 2085 * OUT Endpoints: The core decrements this field every time a packet is read from the 2086 * RxFIFO and written to the external memory 2087 */ 2088 #define USB_D_XFERSIZE1 0x0000007F 2089 #define USB_D_XFERSIZE1_M (USB_D_XFERSIZE1_V << USB_D_XFERSIZE1_S) 2090 #define USB_D_XFERSIZE1_V 0x0000007F 2091 #define USB_D_XFERSIZE1_S 0 2092 /** USB_D_PKTCNT1 : R/W; bitpos: [21:19]; default: 0; 2093 * Packet Count 2094 * IN Endpoints : This field is decremented every time a packet (maximum size or short 2095 * packet) is read from the TxFIFO 2096 * OUT Endpoints: This field is decremented every time a packet (maximum size or short 2097 * packet) is written to the RxFIFO 2098 */ 2099 #define USB_D_PKTCNT1 0x00000003 2100 #define USB_D_PKTCNT1_M (USB_D_PKTCNT1_V << USB_D_PKTCNT1_S) 2101 #define USB_D_PKTCNT1_V 0x00000003 2102 #define USB_D_PKTCNT1_S 19 2103 2104 2105 /** USB_DIEPDMA1_REG register 2106 * Device IN Endpoint 1 DMA Address Register 2107 */ 2108 #define USB_DIEPDMA1_REG (SOC_DPORT_USB_BASE + 0x934) 2109 /** USB_D_DMAADDR1 : R/W; bitpos: [32:0]; default: 0; 2110 * This field holds the start address of the external memory for storing or fetching 2111 * endpoint data. 2112 */ 2113 #define USB_D_DMAADDR1 0xFFFFFFFF 2114 #define USB_D_DMAADDR1_M (USB_D_DMAADDR1_V << USB_D_DMAADDR1_S) 2115 #define USB_D_DMAADDR1_V 0xFFFFFFFF 2116 #define USB_D_DMAADDR1_S 0 2117 2118 2119 /** USB_DIEPCTL2_REG register 2120 * Device Control IN Endpoint 2 Control Register 2121 */ 2122 #define USB_DIEPCTL2_REG (SOC_DPORT_USB_BASE + 0x940) 2123 /** USB_D_MPS2 : R/W; bitpos: [2:0]; default: 0; 2124 * Maximum Packet Size 2125 * 0x0 : 64 bytes 2126 * 0x1 : 32 bytes 2127 * 0x2 : 16 bytes 2128 * 0x3 : 8 bytes 2129 */ 2130 #define USB_D_MPS2 0x00000003 2131 #define USB_D_MPS2_M (USB_D_MPS2_V << USB_D_MPS2_S) 2132 #define USB_D_MPS2_V 0x00000003 2133 #define USB_D_MPS2_S 0 2134 /** USB_D_USBACTEP2 : RO; bitpos: [15]; default: 1; 2135 * USB Active Endpoint 2136 * 0x1 : Control endpoint is always active 2137 */ 2138 #define USB_D_USBACTEP2 (BIT(15)) 2139 #define USB_D_USBACTEP2_M (USB_D_USBACTEP2_V << USB_D_USBACTEP2_S) 2140 #define USB_D_USBACTEP2_V 0x00000001 2141 #define USB_D_USBACTEP2_S 15 2142 /** USB_D_NAKSTS2 : RO; bitpos: [17]; default: 0; 2143 * NAK Status 2144 * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status 2145 * 0x1 : The core is transmitting NAK handshakes on this endpoint 2146 */ 2147 #define USB_D_NAKSTS2 (BIT(17)) 2148 #define USB_D_NAKSTS2_M (USB_D_NAKSTS2_V << USB_D_NAKSTS2_S) 2149 #define USB_D_NAKSTS2_V 0x00000001 2150 #define USB_D_NAKSTS2_S 17 2151 /** USB_D_EPTYPE2 : RO; bitpos: [20:18]; default: 0; 2152 * Endpoint Type 2153 * 0x0 : Endpoint Control 0 2154 */ 2155 #define USB_D_EPTYPE2 0x00000003 2156 #define USB_D_EPTYPE2_M (USB_D_EPTYPE2_V << USB_D_EPTYPE2_S) 2157 #define USB_D_EPTYPE2_V 0x00000003 2158 #define USB_D_EPTYPE2_S 18 2159 /** USB_D_STALL2 : R/W; bitpos: [21]; default: 0; 2160 * The application can only set this bit, and the core clears it 2161 * 0x0 : No Stall 2162 * 0x1 : Stall Handshake 2163 */ 2164 #define USB_D_STALL2 (BIT(21)) 2165 #define USB_D_STALL2_M (USB_D_STALL2_V << USB_D_STALL2_S) 2166 #define USB_D_STALL2_V 0x00000001 2167 #define USB_D_STALL2_S 21 2168 /** USB_D_TXFNUM2 : R/W; bitpos: [26:22]; default: 0; 2169 * TxFIFO Number. 2170 */ 2171 #define USB_D_TXFNUM2 0x0000000F 2172 #define USB_D_TXFNUM2_M (USB_D_TXFNUM2_V << USB_D_TXFNUM2_S) 2173 #define USB_D_TXFNUM2_V 0x0000000F 2174 #define USB_D_TXFNUM2_S 22 2175 /** USB_D_CNAK2 : WO; bitpos: [26]; default: 0; 2176 * A write to this bit clears the NAK bit for the endpoint 2177 * 0x0 : No action 2178 * 0x1 : Clear NAK 2179 */ 2180 #define USB_D_CNAK2 (BIT(26)) 2181 #define USB_D_CNAK2_M (USB_D_CNAK2_V << USB_D_CNAK2_S) 2182 #define USB_D_CNAK2_V 0x00000001 2183 #define USB_D_CNAK2_S 26 2184 /** USB_DI_SNAK2 : WO; bitpos: [27]; default: 0; 2185 * A write to this bit sets the NAK bit for the endpoint 2186 * 0x0 : No action 2187 * 0x1 : Set NAK 2188 */ 2189 #define USB_DI_SNAK2 (BIT(27)) 2190 #define USB_DI_SNAK2_M (USB_DI_SNAK2_V << USB_DI_SNAK2_S) 2191 #define USB_DI_SNAK2_V 0x00000001 2192 #define USB_DI_SNAK2_S 27 2193 /** USB_DI_SETD0PID2 : WO; bitpos: [28]; default: 0; 2194 * Set DATA0 PID 2195 */ 2196 #define USB_DI_SETD0PID2 (BIT(28)) 2197 #define USB_DI_SETD0PID2_M (USB_DI_SETD0PID2_V << USB_DI_SETD0PID2_S) 2198 #define USB_DI_SETD0PID2_V 0x00000001 2199 #define USB_DI_SETD0PID2_S 28 2200 /** USB_DI_SETD1PID2 : WO; bitpos: [29]; default: 0; 2201 * Set DATA1 PID 2202 */ 2203 #define USB_DI_SETD1PID2 (BIT(29)) 2204 #define USB_DI_SETD1PID2_M (USB_DI_SETD1PID2_V << USB_DI_SETD1PID2_S) 2205 #define USB_DI_SETD1PID2_V 0x00000001 2206 #define USB_DI_SETD1PID2_S 29 2207 /** USB_D_EPDIS2 : R/W; bitpos: [30]; default: 0; 2208 * Endpoint Disable 2209 * 0x0 : No action 2210 * 0x1 : Disabled Endpoint 2211 */ 2212 #define USB_D_EPDIS2 (BIT(30)) 2213 #define USB_D_EPDIS2_M (USB_D_EPDIS2_V << USB_D_EPDIS2_S) 2214 #define USB_D_EPDIS2_V 0x00000001 2215 #define USB_D_EPDIS2_S 30 2216 /** USB_D_EPENA2 : R/W; bitpos: [31]; default: 0; 2217 * Endpoint Enable 2218 * 0x0 : No action 2219 * 0x1 : Enable Endpoint 2220 */ 2221 #define USB_D_EPENA2 (BIT(31)) 2222 #define USB_D_EPENA2_M (USB_D_EPENA2_V << USB_D_EPENA2_S) 2223 #define USB_D_EPENA2_V 0x00000001 2224 #define USB_D_EPENA2_S 31 2225 2226 2227 /** USB_DIEPTSIZ2_REG register 2228 * Device IN Endpoint 2 Transfer Size Register 2229 */ 2230 #define USB_DIEPTSIZ2_REG (SOC_DPORT_USB_BASE + 0x950) 2231 /** USB_D_XFERSIZE2 : R/W; bitpos: [7:0]; default: 0; 2232 * Transfer Size 2233 * IN Endpoints: The core decrements this field every time a packet from the external 2234 * memory is written to the TxFIFO 2235 * OUT Endpoints: The core decrements this field every time a packet is read from the 2236 * RxFIFO and written to the external memory 2237 */ 2238 #define USB_D_XFERSIZE2 0x0000007F 2239 #define USB_D_XFERSIZE2_M (USB_D_XFERSIZE2_V << USB_D_XFERSIZE2_S) 2240 #define USB_D_XFERSIZE2_V 0x0000007F 2241 #define USB_D_XFERSIZE2_S 0 2242 /** USB_D_PKTCNT2 : R/W; bitpos: [21:19]; default: 0; 2243 * Packet Count 2244 * IN Endpoints : This field is decremented every time a packet (maximum size or short 2245 * packet) is read from the TxFIFO 2246 * OUT Endpoints: This field is decremented every time a packet (maximum size or short 2247 * packet) is written to the RxFIFO 2248 */ 2249 #define USB_D_PKTCNT2 0x00000003 2250 #define USB_D_PKTCNT2_M (USB_D_PKTCNT2_V << USB_D_PKTCNT2_S) 2251 #define USB_D_PKTCNT2_V 0x00000003 2252 #define USB_D_PKTCNT2_S 19 2253 2254 2255 /** USB_DIEPDMA2_REG register 2256 * Device IN Endpoint 2 DMA Address Register 2257 */ 2258 #define USB_DIEPDMA2_REG (SOC_DPORT_USB_BASE + 0x954) 2259 /** USB_D_DMAADDR2 : R/W; bitpos: [32:0]; default: 0; 2260 * This field holds the start address of the external memory for storing or fetching 2261 * endpoint data. 2262 */ 2263 #define USB_D_DMAADDR2 0xFFFFFFFF 2264 #define USB_D_DMAADDR2_M (USB_D_DMAADDR2_V << USB_D_DMAADDR2_S) 2265 #define USB_D_DMAADDR2_V 0xFFFFFFFF 2266 #define USB_D_DMAADDR2_S 0 2267 2268 2269 /** USB_DIEPCTL3_REG register 2270 * Device Control IN Endpoint $n Control Register 2271 */ 2272 #define USB_DIEPCTL3_REG (SOC_DPORT_USB_BASE + 0x960) 2273 /** USB_DI_MPS3 : R/W; bitpos: [2:0]; default: 0; 2274 * Maximum Packet Size 2275 * 0x0 : 64 bytes 2276 * 0x1 : 32 bytes 2277 * 0x2 : 16 bytes 2278 * 0x3 : 8 bytes 2279 */ 2280 #define USB_DI_MPS3 0x00000003 2281 #define USB_DI_MPS3_M (USB_DI_MPS3_V << USB_DI_MPS3_S) 2282 #define USB_DI_MPS3_V 0x00000003 2283 #define USB_DI_MPS3_S 0 2284 /** USB_DI_USBACTEP3 : RO; bitpos: [15]; default: 1; 2285 * USB Active Endpoint 2286 * 0x1 : Control endpoint is always active 2287 */ 2288 #define USB_DI_USBACTEP3 (BIT(15)) 2289 #define USB_DI_USBACTEP3_M (USB_DI_USBACTEP3_V << USB_DI_USBACTEP3_S) 2290 #define USB_DI_USBACTEP3_V 0x00000001 2291 #define USB_DI_USBACTEP3_S 15 2292 /** USB_DI_NAKSTS3 : RO; bitpos: [17]; default: 0; 2293 * NAK Status 2294 * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status 2295 * 0x1 : The core is transmitting NAK handshakes on this endpoint 2296 */ 2297 #define USB_DI_NAKSTS3 (BIT(17)) 2298 #define USB_DI_NAKSTS3_M (USB_DI_NAKSTS3_V << USB_DI_NAKSTS3_S) 2299 #define USB_DI_NAKSTS3_V 0x00000001 2300 #define USB_DI_NAKSTS3_S 17 2301 /** USB_DI_EPTYPE3 : RO; bitpos: [20:18]; default: 0; 2302 * Endpoint Type 2303 * 0x0 : Endpoint Control 0 2304 */ 2305 #define USB_DI_EPTYPE3 0x00000003 2306 #define USB_DI_EPTYPE3_M (USB_DI_EPTYPE3_V << USB_DI_EPTYPE3_S) 2307 #define USB_DI_EPTYPE3_V 0x00000003 2308 #define USB_DI_EPTYPE3_S 18 2309 /** USB_DI_STALL3 : R/W; bitpos: [21]; default: 0; 2310 * The application can only set this bit, and the core clears it 2311 * 0x0 : No Stall 2312 * 0x1 : Stall Handshake 2313 */ 2314 #define USB_DI_STALL3 (BIT(21)) 2315 #define USB_DI_STALL3_M (USB_DI_STALL3_V << USB_DI_STALL3_S) 2316 #define USB_DI_STALL3_V 0x00000001 2317 #define USB_DI_STALL3_S 21 2318 /** USB_DI_TXFNUM3 : R/W; bitpos: [26:22]; default: 0; 2319 * TxFIFO Number. 2320 */ 2321 #define USB_DI_TXFNUM3 0x0000000F 2322 #define USB_DI_TXFNUM3_M (USB_DI_TXFNUM3_V << USB_DI_TXFNUM3_S) 2323 #define USB_DI_TXFNUM3_V 0x0000000F 2324 #define USB_DI_TXFNUM3_S 22 2325 /** USB_DI_CNAK3 : WO; bitpos: [26]; default: 0; 2326 * A write to this bit clears the NAK bit for the endpoint 2327 * 0x0 : No action 2328 * 0x1 : Clear NAK 2329 */ 2330 #define USB_DI_CNAK3 (BIT(26)) 2331 #define USB_DI_CNAK3_M (USB_DI_CNAK3_V << USB_DI_CNAK3_S) 2332 #define USB_DI_CNAK3_V 0x00000001 2333 #define USB_DI_CNAK3_S 26 2334 /** USB_DI_SNAK3 : WO; bitpos: [27]; default: 0; 2335 * A write to this bit sets the NAK bit for the endpoint 2336 * 0x0 : No action 2337 * 0x1 : Set NAK 2338 */ 2339 #define USB_DI_SNAK3 (BIT(27)) 2340 #define USB_DI_SNAK3_M (USB_DI_SNAK3_V << USB_DI_SNAK3_S) 2341 #define USB_DI_SNAK3_V 0x00000001 2342 #define USB_DI_SNAK3_S 27 2343 /** USB_DI_SETD0PID3 : WO; bitpos: [28]; default: 0; 2344 * Set DATA0 PID 2345 */ 2346 #define USB_DI_SETD0PID3 (BIT(28)) 2347 #define USB_DI_SETD0PID3_M (USB_DI_SETD0PID3_V << USB_DI_SETD0PID3_S) 2348 #define USB_DI_SETD0PID3_V 0x00000001 2349 #define USB_DI_SETD0PID3_S 28 2350 /** USB_DI_SETD1PID3 : WO; bitpos: [29]; default: 0; 2351 * Set DATA1 PID 2352 */ 2353 #define USB_DI_SETD1PID3 (BIT(29)) 2354 #define USB_DI_SETD1PID3_M (USB_DI_SETD1PID3_V << USB_DI_SETD1PID3_S) 2355 #define USB_DI_SETD1PID3_V 0x00000001 2356 #define USB_DI_SETD1PID3_S 29 2357 /** USB_DI_EPDIS3 : R/W; bitpos: [30]; default: 0; 2358 * Endpoint Disable 2359 * 0x0 : No action 2360 * 0x1 : Disabled Endpoint 2361 */ 2362 #define USB_DI_EPDIS3 (BIT(30)) 2363 #define USB_DI_EPDIS3_M (USB_DI_EPDIS3_V << USB_DI_EPDIS3_S) 2364 #define USB_DI_EPDIS3_V 0x00000001 2365 #define USB_DI_EPDIS3_S 30 2366 /** USB_DI_EPENA3 : R/W; bitpos: [31]; default: 0; 2367 * Endpoint Enable 2368 * 0x0 : No action 2369 * 0x1 : Enable Endpoint 2370 */ 2371 #define USB_DI_EPENA3 (BIT(31)) 2372 #define USB_DI_EPENA3_M (USB_DI_EPENA3_V << USB_DI_EPENA3_S) 2373 #define USB_DI_EPENA3_V 0x00000001 2374 #define USB_DI_EPENA3_S 31 2375 2376 2377 /** USB_DIEPTSIZ3_REG register 2378 * Device IN Endpoint 3 Transfer Size Register 2379 */ 2380 #define USB_DIEPTSIZ3_REG (SOC_DPORT_USB_BASE + 0x970) 2381 /** USB_D_XFERSIZE3 : R/W; bitpos: [7:0]; default: 0; 2382 * Transfer Size 2383 * IN Endpoints: The core decrements this field every time a packet from the external 2384 * memory is written to the TxFIFO 2385 * OUT Endpoints: The core decrements this field every time a packet is read from the 2386 * RxFIFO and written to the external memory 2387 */ 2388 #define USB_D_XFERSIZE3 0x0000007F 2389 #define USB_D_XFERSIZE3_M (USB_D_XFERSIZE3_V << USB_D_XFERSIZE3_S) 2390 #define USB_D_XFERSIZE3_V 0x0000007F 2391 #define USB_D_XFERSIZE3_S 0 2392 /** USB_D_PKTCNT3 : R/W; bitpos: [21:19]; default: 0; 2393 * Packet Count 2394 * IN Endpoints : This field is decremented every time a packet (maximum size or short 2395 * packet) is read from the TxFIFO 2396 * OUT Endpoints: This field is decremented every time a packet (maximum size or short 2397 * packet) is written to the RxFIFO 2398 */ 2399 #define USB_D_PKTCNT3 0x00000003 2400 #define USB_D_PKTCNT3_M (USB_D_PKTCNT3_V << USB_D_PKTCNT3_S) 2401 #define USB_D_PKTCNT3_V 0x00000003 2402 #define USB_D_PKTCNT3_S 19 2403 2404 2405 /** USB_DIEPDMA3_REG register 2406 * Device IN Endpoint 3 DMA Address Register 2407 */ 2408 #define USB_DIEPDMA3_REG (SOC_DPORT_USB_BASE + 0x974) 2409 /** USB_D_DMAADDR3 : R/W; bitpos: [32:0]; default: 0; 2410 * This field holds the start address of the external memory for storing or fetching 2411 * endpoint data. 2412 */ 2413 #define USB_D_DMAADDR3 0xFFFFFFFF 2414 #define USB_D_DMAADDR3_M (USB_D_DMAADDR3_V << USB_D_DMAADDR3_S) 2415 #define USB_D_DMAADDR3_V 0xFFFFFFFF 2416 #define USB_D_DMAADDR3_S 0 2417 2418 2419 /** USB_DIEPCTL4_REG register 2420 * Device Control IN Endpoint $n Control Register 2421 */ 2422 #define USB_DIEPCTL4_REG (SOC_DPORT_USB_BASE + 0x980) 2423 /** USB_D_MPS4 : R/W; bitpos: [2:0]; default: 0; 2424 * Maximum Packet Size 2425 * 0x0 : 64 bytes 2426 * 0x1 : 32 bytes 2427 * 0x2 : 16 bytes 2428 * 0x3 : 8 bytes 2429 */ 2430 #define USB_D_MPS4 0x00000003 2431 #define USB_D_MPS4_M (USB_D_MPS4_V << USB_D_MPS4_S) 2432 #define USB_D_MPS4_V 0x00000003 2433 #define USB_D_MPS4_S 0 2434 /** USB_D_USBACTEP4 : RO; bitpos: [15]; default: 1; 2435 * USB Active Endpoint 2436 * 0x1 : Control endpoint is always active 2437 */ 2438 #define USB_D_USBACTEP4 (BIT(15)) 2439 #define USB_D_USBACTEP4_M (USB_D_USBACTEP4_V << USB_D_USBACTEP4_S) 2440 #define USB_D_USBACTEP4_V 0x00000001 2441 #define USB_D_USBACTEP4_S 15 2442 /** USB_D_NAKSTS4 : RO; bitpos: [17]; default: 0; 2443 * NAK Status 2444 * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status 2445 * 0x1 : The core is transmitting NAK handshakes on this endpoint 2446 */ 2447 #define USB_D_NAKSTS4 (BIT(17)) 2448 #define USB_D_NAKSTS4_M (USB_D_NAKSTS4_V << USB_D_NAKSTS4_S) 2449 #define USB_D_NAKSTS4_V 0x00000001 2450 #define USB_D_NAKSTS4_S 17 2451 /** USB_D_EPTYPE4 : RO; bitpos: [20:18]; default: 0; 2452 * Endpoint Type 2453 * 0x0 : Endpoint Control 0 2454 */ 2455 #define USB_D_EPTYPE4 0x00000003 2456 #define USB_D_EPTYPE4_M (USB_D_EPTYPE4_V << USB_D_EPTYPE4_S) 2457 #define USB_D_EPTYPE4_V 0x00000003 2458 #define USB_D_EPTYPE4_S 18 2459 /** USB_D_STALL4 : R/W; bitpos: [21]; default: 0; 2460 * The application can only set this bit, and the core clears it 2461 * 0x0 : No Stall 2462 * 0x1 : Stall Handshake 2463 */ 2464 #define USB_D_STALL4 (BIT(21)) 2465 #define USB_D_STALL4_M (USB_D_STALL4_V << USB_D_STALL4_S) 2466 #define USB_D_STALL4_V 0x00000001 2467 #define USB_D_STALL4_S 21 2468 /** USB_D_TXFNUM4 : R/W; bitpos: [26:22]; default: 0; 2469 * TxFIFO Number. 2470 */ 2471 #define USB_D_TXFNUM4 0x0000000F 2472 #define USB_D_TXFNUM4_M (USB_D_TXFNUM4_V << USB_D_TXFNUM4_S) 2473 #define USB_D_TXFNUM4_V 0x0000000F 2474 #define USB_D_TXFNUM4_S 22 2475 /** USB_D_CNAK4 : WO; bitpos: [26]; default: 0; 2476 * A write to this bit clears the NAK bit for the endpoint 2477 * 0x0 : No action 2478 * 0x1 : Clear NAK 2479 */ 2480 #define USB_D_CNAK4 (BIT(26)) 2481 #define USB_D_CNAK4_M (USB_D_CNAK4_V << USB_D_CNAK4_S) 2482 #define USB_D_CNAK4_V 0x00000001 2483 #define USB_D_CNAK4_S 26 2484 /** USB_DI_SNAK4 : WO; bitpos: [27]; default: 0; 2485 * A write to this bit sets the NAK bit for the endpoint 2486 * 0x0 : No action 2487 * 0x1 : Set NAK 2488 */ 2489 #define USB_DI_SNAK4 (BIT(27)) 2490 #define USB_DI_SNAK4_M (USB_DI_SNAK4_V << USB_DI_SNAK4_S) 2491 #define USB_DI_SNAK4_V 0x00000001 2492 #define USB_DI_SNAK4_S 27 2493 /** USB_DI_SETD0PID4 : WO; bitpos: [28]; default: 0; 2494 * Set DATA0 PID 2495 */ 2496 #define USB_DI_SETD0PID4 (BIT(28)) 2497 #define USB_DI_SETD0PID4_M (USB_DI_SETD0PID4_V << USB_DI_SETD0PID4_S) 2498 #define USB_DI_SETD0PID4_V 0x00000001 2499 #define USB_DI_SETD0PID4_S 28 2500 /** USB_DI_SETD1PID4 : WO; bitpos: [29]; default: 0; 2501 * Set DATA1 PID 2502 */ 2503 #define USB_DI_SETD1PID4 (BIT(29)) 2504 #define USB_DI_SETD1PID4_M (USB_DI_SETD1PID4_V << USB_DI_SETD1PID4_S) 2505 #define USB_DI_SETD1PID4_V 0x00000001 2506 #define USB_DI_SETD1PID4_S 29 2507 /** USB_D_EPDIS4 : R/W; bitpos: [30]; default: 0; 2508 * Endpoint Disable 2509 * 0x0 : No action 2510 * 0x1 : Disabled Endpoint 2511 */ 2512 #define USB_D_EPDIS4 (BIT(30)) 2513 #define USB_D_EPDIS4_M (USB_D_EPDIS4_V << USB_D_EPDIS4_S) 2514 #define USB_D_EPDIS4_V 0x00000001 2515 #define USB_D_EPDIS4_S 30 2516 /** USB_D_EPENA4 : R/W; bitpos: [31]; default: 0; 2517 * Endpoint Enable 2518 * 0x0 : No action 2519 * 0x1 : Enable Endpoint 2520 */ 2521 #define USB_D_EPENA4 (BIT(31)) 2522 #define USB_D_EPENA4_M (USB_D_EPENA4_V << USB_D_EPENA4_S) 2523 #define USB_D_EPENA4_V 0x00000001 2524 #define USB_D_EPENA4_S 31 2525 2526 2527 /** USB_DIEPTSIZ4_REG register 2528 * Device IN Endpoint 4 Transfer Size Register 2529 */ 2530 #define USB_DIEPTSIZ4_REG (SOC_DPORT_USB_BASE + 0x990) 2531 /** USB_D_XFERSIZE4 : R/W; bitpos: [7:0]; default: 0; 2532 * Transfer Size 2533 * IN Endpoints: The core decrements this field every time a packet from the external 2534 * memory is written to the TxFIFO 2535 * OUT Endpoints: The core decrements this field every time a packet is read from the 2536 * RxFIFO and written to the external memory 2537 */ 2538 #define USB_D_XFERSIZE4 0x0000007F 2539 #define USB_D_XFERSIZE4_M (USB_D_XFERSIZE4_V << USB_D_XFERSIZE4_S) 2540 #define USB_D_XFERSIZE4_V 0x0000007F 2541 #define USB_D_XFERSIZE4_S 0 2542 /** USB_D_PKTCNT4 : R/W; bitpos: [21:19]; default: 0; 2543 * Packet Count 2544 * IN Endpoints : This field is decremented every time a packet (maximum size or short 2545 * packet) is read from the TxFIFO 2546 * OUT Endpoints: This field is decremented every time a packet (maximum size or short 2547 * packet) is written to the RxFIFO 2548 */ 2549 #define USB_D_PKTCNT4 0x00000003 2550 #define USB_D_PKTCNT4_M (USB_D_PKTCNT4_V << USB_D_PKTCNT4_S) 2551 #define USB_D_PKTCNT4_V 0x00000003 2552 #define USB_D_PKTCNT4_S 19 2553 2554 2555 /** USB_DIEPDMA4_REG register 2556 * Device IN Endpoint 4 DMA Address Register 2557 */ 2558 #define USB_DIEPDMA4_REG (SOC_DPORT_USB_BASE + 0x994) 2559 /** USB_D_DMAADDR4 : R/W; bitpos: [32:0]; default: 0; 2560 * This field holds the start address of the external memory for storing or fetching 2561 * endpoint data. 2562 */ 2563 #define USB_D_DMAADDR4 0xFFFFFFFF 2564 #define USB_D_DMAADDR4_M (USB_D_DMAADDR4_V << USB_D_DMAADDR4_S) 2565 #define USB_D_DMAADDR4_V 0xFFFFFFFF 2566 #define USB_D_DMAADDR4_S 0 2567 2568 2569 /** USB_DIEPCTL5_REG register 2570 * Device Control IN Endpoint $n Control Register 2571 */ 2572 #define USB_DIEPCTL5_REG (SOC_DPORT_USB_BASE + 0x9a0) 2573 /** USB_DI_MPS5 : R/W; bitpos: [2:0]; default: 0; 2574 * Maximum Packet Size 2575 * 0x0 : 64 bytes 2576 * 0x1 : 32 bytes 2577 * 0x2 : 16 bytes 2578 * 0x3 : 8 bytes 2579 */ 2580 #define USB_DI_MPS5 0x00000003 2581 #define USB_DI_MPS5_M (USB_DI_MPS5_V << USB_DI_MPS5_S) 2582 #define USB_DI_MPS5_V 0x00000003 2583 #define USB_DI_MPS5_S 0 2584 /** USB_DI_USBACTEP5 : RO; bitpos: [15]; default: 1; 2585 * USB Active Endpoint 2586 * 0x1 : Control endpoint is always active 2587 */ 2588 #define USB_DI_USBACTEP5 (BIT(15)) 2589 #define USB_DI_USBACTEP5_M (USB_DI_USBACTEP5_V << USB_DI_USBACTEP5_S) 2590 #define USB_DI_USBACTEP5_V 0x00000001 2591 #define USB_DI_USBACTEP5_S 15 2592 /** USB_DI_NAKSTS5 : RO; bitpos: [17]; default: 0; 2593 * NAK Status 2594 * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status 2595 * 0x1 : The core is transmitting NAK handshakes on this endpoint 2596 */ 2597 #define USB_DI_NAKSTS5 (BIT(17)) 2598 #define USB_DI_NAKSTS5_M (USB_DI_NAKSTS5_V << USB_DI_NAKSTS5_S) 2599 #define USB_DI_NAKSTS5_V 0x00000001 2600 #define USB_DI_NAKSTS5_S 17 2601 /** USB_DI_EPTYPE5 : RO; bitpos: [20:18]; default: 0; 2602 * Endpoint Type 2603 * 0x0 : Endpoint Control 0 2604 */ 2605 #define USB_DI_EPTYPE5 0x00000003 2606 #define USB_DI_EPTYPE5_M (USB_DI_EPTYPE5_V << USB_DI_EPTYPE5_S) 2607 #define USB_DI_EPTYPE5_V 0x00000003 2608 #define USB_DI_EPTYPE5_S 18 2609 /** USB_DI_STALL5 : R/W; bitpos: [21]; default: 0; 2610 * The application can only set this bit, and the core clears it 2611 * 0x0 : No Stall 2612 * 0x1 : Stall Handshake 2613 */ 2614 #define USB_DI_STALL5 (BIT(21)) 2615 #define USB_DI_STALL5_M (USB_DI_STALL5_V << USB_DI_STALL5_S) 2616 #define USB_DI_STALL5_V 0x00000001 2617 #define USB_DI_STALL5_S 21 2618 /** USB_DI_TXFNUM5 : R/W; bitpos: [26:22]; default: 0; 2619 * TxFIFO Number. 2620 */ 2621 #define USB_DI_TXFNUM5 0x0000000F 2622 #define USB_DI_TXFNUM5_M (USB_DI_TXFNUM5_V << USB_DI_TXFNUM5_S) 2623 #define USB_DI_TXFNUM5_V 0x0000000F 2624 #define USB_DI_TXFNUM5_S 22 2625 /** USB_DI_CNAK5 : WO; bitpos: [26]; default: 0; 2626 * A write to this bit clears the NAK bit for the endpoint 2627 * 0x0 : No action 2628 * 0x1 : Clear NAK 2629 */ 2630 #define USB_DI_CNAK5 (BIT(26)) 2631 #define USB_DI_CNAK5_M (USB_DI_CNAK5_V << USB_DI_CNAK5_S) 2632 #define USB_DI_CNAK5_V 0x00000001 2633 #define USB_DI_CNAK5_S 26 2634 /** USB_DI_SNAK5 : WO; bitpos: [27]; default: 0; 2635 * A write to this bit sets the NAK bit for the endpoint 2636 * 0x0 : No action 2637 * 0x1 : Set NAK 2638 */ 2639 #define USB_DI_SNAK5 (BIT(27)) 2640 #define USB_DI_SNAK5_M (USB_DI_SNAK5_V << USB_DI_SNAK5_S) 2641 #define USB_DI_SNAK5_V 0x00000001 2642 #define USB_DI_SNAK5_S 27 2643 /** USB_DI_SETD0PID5 : WO; bitpos: [28]; default: 0; 2644 * Set DATA0 PID 2645 */ 2646 #define USB_DI_SETD0PID5 (BIT(28)) 2647 #define USB_DI_SETD0PID5_M (USB_DI_SETD0PID5_V << USB_DI_SETD0PID5_S) 2648 #define USB_DI_SETD0PID5_V 0x00000001 2649 #define USB_DI_SETD0PID5_S 28 2650 /** USB_DI_SETD1PID5 : WO; bitpos: [29]; default: 0; 2651 * Set DATA1 PID 2652 */ 2653 #define USB_DI_SETD1PID5 (BIT(29)) 2654 #define USB_DI_SETD1PID5_M (USB_DI_SETD1PID5_V << USB_DI_SETD1PID5_S) 2655 #define USB_DI_SETD1PID5_V 0x00000001 2656 #define USB_DI_SETD1PID5_S 29 2657 /** USB_DI_EPDIS5 : R/W; bitpos: [30]; default: 0; 2658 * Endpoint Disable 2659 * 0x0 : No action 2660 * 0x1 : Disabled Endpoint 2661 */ 2662 #define USB_DI_EPDIS5 (BIT(30)) 2663 #define USB_DI_EPDIS5_M (USB_DI_EPDIS5_V << USB_DI_EPDIS5_S) 2664 #define USB_DI_EPDIS5_V 0x00000001 2665 #define USB_DI_EPDIS5_S 30 2666 /** USB_DI_EPENA5 : R/W; bitpos: [31]; default: 0; 2667 * Endpoint Enable 2668 * 0x0 : No action 2669 * 0x1 : Enable Endpoint 2670 */ 2671 #define USB_DI_EPENA5 (BIT(31)) 2672 #define USB_DI_EPENA5_M (USB_DI_EPENA5_V << USB_DI_EPENA5_S) 2673 #define USB_DI_EPENA5_V 0x00000001 2674 #define USB_DI_EPENA5_S 31 2675 2676 2677 /** USB_DIEPTSIZ5_REG register 2678 * Device IN Endpoint 5 Transfer Size Register 2679 */ 2680 #define USB_DIEPTSIZ5_REG (SOC_DPORT_USB_BASE + 0x9b0) 2681 /** USB_D_XFERSIZE5 : R/W; bitpos: [7:0]; default: 0; 2682 * Transfer Size 2683 * IN Endpoints: The core decrements this field every time a packet from the external 2684 * memory is written to the TxFIFO 2685 * OUT Endpoints: The core decrements this field every time a packet is read from the 2686 * RxFIFO and written to the external memory 2687 */ 2688 #define USB_D_XFERSIZE5 0x0000007F 2689 #define USB_D_XFERSIZE5_M (USB_D_XFERSIZE5_V << USB_D_XFERSIZE5_S) 2690 #define USB_D_XFERSIZE5_V 0x0000007F 2691 #define USB_D_XFERSIZE5_S 0 2692 /** USB_D_PKTCNT5 : R/W; bitpos: [21:19]; default: 0; 2693 * Packet Count 2694 * IN Endpoints : This field is decremented every time a packet (maximum size or short 2695 * packet) is read from the TxFIFO 2696 * OUT Endpoints: This field is decremented every time a packet (maximum size or short 2697 * packet) is written to the RxFIFO 2698 */ 2699 #define USB_D_PKTCNT5 0x00000003 2700 #define USB_D_PKTCNT5_M (USB_D_PKTCNT5_V << USB_D_PKTCNT5_S) 2701 #define USB_D_PKTCNT5_V 0x00000003 2702 #define USB_D_PKTCNT5_S 19 2703 2704 2705 /** USB_DIEPDMA5_REG register 2706 * Device IN Endpoint 5 DMA Address Register 2707 */ 2708 #define USB_DIEPDMA5_REG (SOC_DPORT_USB_BASE + 0x9b4) 2709 /** USB_D_DMAADDR5 : R/W; bitpos: [32:0]; default: 0; 2710 * This field holds the start address of the external memory for storing or fetching 2711 * endpoint data. 2712 */ 2713 #define USB_D_DMAADDR5 0xFFFFFFFF 2714 #define USB_D_DMAADDR5_M (USB_D_DMAADDR5_V << USB_D_DMAADDR5_S) 2715 #define USB_D_DMAADDR5_V 0xFFFFFFFF 2716 #define USB_D_DMAADDR5_S 0 2717 2718 2719 /** USB_DIEPCTL6_REG register 2720 * Device Control IN Endpoint $n Control Register 2721 */ 2722 #define USB_DIEPCTL6_REG (SOC_DPORT_USB_BASE + 0x9c0) 2723 /** USB_D_MPS6 : R/W; bitpos: [2:0]; default: 0; 2724 * Maximum Packet Size 2725 * 0x0 : 64 bytes 2726 * 0x1 : 32 bytes 2727 * 0x2 : 16 bytes 2728 * 0x3 : 8 bytes 2729 */ 2730 #define USB_D_MPS6 0x00000003 2731 #define USB_D_MPS6_M (USB_D_MPS6_V << USB_D_MPS6_S) 2732 #define USB_D_MPS6_V 0x00000003 2733 #define USB_D_MPS6_S 0 2734 /** USB_D_USBACTEP6 : RO; bitpos: [15]; default: 1; 2735 * USB Active Endpoint 2736 * 0x1 : Control endpoint is always active 2737 */ 2738 #define USB_D_USBACTEP6 (BIT(15)) 2739 #define USB_D_USBACTEP6_M (USB_D_USBACTEP6_V << USB_D_USBACTEP6_S) 2740 #define USB_D_USBACTEP6_V 0x00000001 2741 #define USB_D_USBACTEP6_S 15 2742 /** USB_D_NAKSTS6 : RO; bitpos: [17]; default: 0; 2743 * NAK Status 2744 * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status 2745 * 0x1 : The core is transmitting NAK handshakes on this endpoint 2746 */ 2747 #define USB_D_NAKSTS6 (BIT(17)) 2748 #define USB_D_NAKSTS6_M (USB_D_NAKSTS6_V << USB_D_NAKSTS6_S) 2749 #define USB_D_NAKSTS6_V 0x00000001 2750 #define USB_D_NAKSTS6_S 17 2751 /** USB_D_EPTYPE6 : RO; bitpos: [20:18]; default: 0; 2752 * Endpoint Type 2753 * 0x0 : Endpoint Control 0 2754 */ 2755 #define USB_D_EPTYPE6 0x00000003 2756 #define USB_D_EPTYPE6_M (USB_D_EPTYPE6_V << USB_D_EPTYPE6_S) 2757 #define USB_D_EPTYPE6_V 0x00000003 2758 #define USB_D_EPTYPE6_S 18 2759 /** USB_D_STALL6 : R/W; bitpos: [21]; default: 0; 2760 * The application can only set this bit, and the core clears it 2761 * 0x0 : No Stall 2762 * 0x1 : Stall Handshake 2763 */ 2764 #define USB_D_STALL6 (BIT(21)) 2765 #define USB_D_STALL6_M (USB_D_STALL6_V << USB_D_STALL6_S) 2766 #define USB_D_STALL6_V 0x00000001 2767 #define USB_D_STALL6_S 21 2768 /** USB_D_TXFNUM6 : R/W; bitpos: [26:22]; default: 0; 2769 * TxFIFO Number. 2770 */ 2771 #define USB_D_TXFNUM6 0x0000000F 2772 #define USB_D_TXFNUM6_M (USB_D_TXFNUM6_V << USB_D_TXFNUM6_S) 2773 #define USB_D_TXFNUM6_V 0x0000000F 2774 #define USB_D_TXFNUM6_S 22 2775 /** USB_D_CNAK6 : WO; bitpos: [26]; default: 0; 2776 * A write to this bit clears the NAK bit for the endpoint 2777 * 0x0 : No action 2778 * 0x1 : Clear NAK 2779 */ 2780 #define USB_D_CNAK6 (BIT(26)) 2781 #define USB_D_CNAK6_M (USB_D_CNAK6_V << USB_D_CNAK6_S) 2782 #define USB_D_CNAK6_V 0x00000001 2783 #define USB_D_CNAK6_S 26 2784 /** USB_DI_SNAK6 : WO; bitpos: [27]; default: 0; 2785 * A write to this bit sets the NAK bit for the endpoint 2786 * 0x0 : No action 2787 * 0x1 : Set NAK 2788 */ 2789 #define USB_DI_SNAK6 (BIT(27)) 2790 #define USB_DI_SNAK6_M (USB_DI_SNAK6_V << USB_DI_SNAK6_S) 2791 #define USB_DI_SNAK6_V 0x00000001 2792 #define USB_DI_SNAK6_S 27 2793 /** USB_DI_SETD0PID6 : WO; bitpos: [28]; default: 0; 2794 * Set DATA0 PID 2795 */ 2796 #define USB_DI_SETD0PID6 (BIT(28)) 2797 #define USB_DI_SETD0PID6_M (USB_DI_SETD0PID6_V << USB_DI_SETD0PID6_S) 2798 #define USB_DI_SETD0PID6_V 0x00000001 2799 #define USB_DI_SETD0PID6_S 28 2800 /** USB_DI_SETD1PID6 : WO; bitpos: [29]; default: 0; 2801 * Set DATA1 PID 2802 */ 2803 #define USB_DI_SETD1PID6 (BIT(29)) 2804 #define USB_DI_SETD1PID6_M (USB_DI_SETD1PID6_V << USB_DI_SETD1PID6_S) 2805 #define USB_DI_SETD1PID6_V 0x00000001 2806 #define USB_DI_SETD1PID6_S 29 2807 /** USB_D_EPDIS6 : R/W; bitpos: [30]; default: 0; 2808 * Endpoint Disable 2809 * 0x0 : No action 2810 * 0x1 : Disabled Endpoint 2811 */ 2812 #define USB_D_EPDIS6 (BIT(30)) 2813 #define USB_D_EPDIS6_M (USB_D_EPDIS6_V << USB_D_EPDIS6_S) 2814 #define USB_D_EPDIS6_V 0x00000001 2815 #define USB_D_EPDIS6_S 30 2816 /** USB_D_EPENA6 : R/W; bitpos: [31]; default: 0; 2817 * Endpoint Enable 2818 * 0x0 : No action 2819 * 0x1 : Enable Endpoint 2820 */ 2821 #define USB_D_EPENA6 (BIT(31)) 2822 #define USB_D_EPENA6_M (USB_D_EPENA6_V << USB_D_EPENA6_S) 2823 #define USB_D_EPENA6_V 0x00000001 2824 #define USB_D_EPENA6_S 31 2825 2826 2827 /** USB_DIEPTSIZ6_REG register 2828 * Device IN Endpoint 6 Transfer Size Register 2829 */ 2830 #define USB_DIEPTSIZ6_REG (SOC_DPORT_USB_BASE + 0x9d0) 2831 /** USB_D_XFERSIZE6 : R/W; bitpos: [7:0]; default: 0; 2832 * Transfer Size 2833 * IN Endpoints: The core decrements this field every time a packet from the external 2834 * memory is written to the TxFIFO 2835 * OUT Endpoints: The core decrements this field every time a packet is read from the 2836 * RxFIFO and written to the external memory 2837 */ 2838 #define USB_D_XFERSIZE6 0x0000007F 2839 #define USB_D_XFERSIZE6_M (USB_D_XFERSIZE6_V << USB_D_XFERSIZE6_S) 2840 #define USB_D_XFERSIZE6_V 0x0000007F 2841 #define USB_D_XFERSIZE6_S 0 2842 /** USB_D_PKTCNT6 : R/W; bitpos: [21:19]; default: 0; 2843 * Packet Count 2844 * IN Endpoints : This field is decremented every time a packet (maximum size or short 2845 * packet) is read from the TxFIFO 2846 * OUT Endpoints: This field is decremented every time a packet (maximum size or short 2847 * packet) is written to the RxFIFO 2848 */ 2849 #define USB_D_PKTCNT6 0x00000003 2850 #define USB_D_PKTCNT6_M (USB_D_PKTCNT6_V << USB_D_PKTCNT6_S) 2851 #define USB_D_PKTCNT6_V 0x00000003 2852 #define USB_D_PKTCNT6_S 19 2853 2854 2855 /** USB_DIEPDMA6_REG register 2856 * Device IN Endpoint 6 DMA Address Register 2857 */ 2858 #define USB_DIEPDMA6_REG (SOC_DPORT_USB_BASE + 0x9d4) 2859 /** USB_D_DMAADDR6 : R/W; bitpos: [32:0]; default: 0; 2860 * This field holds the start address of the external memory for storing or fetching 2861 * endpoint data. 2862 */ 2863 #define USB_D_DMAADDR6 0xFFFFFFFF 2864 #define USB_D_DMAADDR6_M (USB_D_DMAADDR6_V << USB_D_DMAADDR6_S) 2865 #define USB_D_DMAADDR6_V 0xFFFFFFFF 2866 #define USB_D_DMAADDR6_S 0 2867 2868 2869 /** USB_DOEPCTL0_REG register 2870 * Device Control OUT Endpoint $n Control Register 2871 */ 2872 #define USB_DOEPCTL0_REG (SOC_DPORT_USB_BASE + 0xb00) 2873 /** USB_MPS0 : RO; bitpos: [2:0]; default: 0; 2874 * Maximum Packet Size 2875 * 0x0 : 64 bytes 2876 * 0x1 : 32 bytes 2877 * 0x2 : 16 bytes 2878 * 0x3 : 8 bytes 2879 */ 2880 #define USB_MPS0 0x00000003 2881 #define USB_MPS0_M (USB_MPS0_V << USB_MPS0_S) 2882 #define USB_MPS0_V 0x00000003 2883 #define USB_MPS0_S 0 2884 /** USB_USBACTEP0 : RO; bitpos: [15]; default: 1; 2885 * 0x1: USB Active Endpoint 0 2886 */ 2887 #define USB_USBACTEP0 (BIT(15)) 2888 #define USB_USBACTEP0_M (USB_USBACTEP0_V << USB_USBACTEP0_S) 2889 #define USB_USBACTEP0_V 0x00000001 2890 #define USB_USBACTEP0_S 15 2891 /** USB_NAKSTS0 : RO; bitpos: [17]; default: 0; 2892 * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status 2893 * 0x1 :The core is transmitting NAK handshakes on this endpoint 2894 */ 2895 #define USB_NAKSTS0 (BIT(17)) 2896 #define USB_NAKSTS0_M (USB_NAKSTS0_V << USB_NAKSTS0_S) 2897 #define USB_NAKSTS0_V 0x00000001 2898 #define USB_NAKSTS0_S 17 2899 /** USB_EPTYPE0 : RO; bitpos: [20:18]; default: 0; 2900 * Endpoint Type 2901 * 0x0 : Endpoint Control $n 2902 */ 2903 #define USB_EPTYPE0 0x00000003 2904 #define USB_EPTYPE0_M (USB_EPTYPE0_V << USB_EPTYPE0_S) 2905 #define USB_EPTYPE0_V 0x00000003 2906 #define USB_EPTYPE0_S 18 2907 /** USB_SNP0 : R/W; bitpos: [20]; default: 0; 2908 * 0x0 : Reserved 0 2909 * 0x1 : Reserved 1 2910 */ 2911 #define USB_SNP0 (BIT(20)) 2912 #define USB_SNP0_M (USB_SNP0_V << USB_SNP0_S) 2913 #define USB_SNP0_V 0x00000001 2914 #define USB_SNP0_S 20 2915 /** USB_STALL0 : R/W; bitpos: [21]; default: 0; 2916 * The application can only set this bit, and the core clears it, when a SETUP token 2917 * is received for this endpoint 2918 * 0x0 (INACTIVE): No Stall 2919 * 0x1 (ACTIVE): Stall Handshake 2920 */ 2921 #define USB_STALL0 (BIT(21)) 2922 #define USB_STALL0_M (USB_STALL0_V << USB_STALL0_S) 2923 #define USB_STALL0_V 0x00000001 2924 #define USB_STALL0_S 21 2925 /** USB_CNAK0 : WO; bitpos: [26]; default: 0; 2926 * 0x0 : No action 2927 * 0x1 : Clear NAK 2928 */ 2929 #define USB_CNAK0 (BIT(26)) 2930 #define USB_CNAK0_M (USB_CNAK0_V << USB_CNAK0_S) 2931 #define USB_CNAK0_V 0x00000001 2932 #define USB_CNAK0_S 26 2933 /** USB_DO_SNAK0 : WO; bitpos: [27]; default: 0; 2934 * 0x0 : No action 2935 * 0x1 : Set NAK 2936 */ 2937 #define USB_DO_SNAK0 (BIT(27)) 2938 #define USB_DO_SNAK0_M (USB_DO_SNAK0_V << USB_DO_SNAK0_S) 2939 #define USB_DO_SNAK0_V 0x00000001 2940 #define USB_DO_SNAK0_S 27 2941 /** USB_EPDIS0 : RO; bitpos: [30]; default: 0; 2942 * Endpoint Disable 2943 * 0x0 : No Endpoint disable 2944 */ 2945 #define USB_EPDIS0 (BIT(30)) 2946 #define USB_EPDIS0_M (USB_EPDIS0_V << USB_EPDIS0_S) 2947 #define USB_EPDIS0_V 0x00000001 2948 #define USB_EPDIS0_S 30 2949 /** USB_EPENA0 : R/W; bitpos: [31]; default: 0; 2950 * Endpoint Enable 2951 * 0x0 : No action 2952 * 0x1 : Enable Endpoint 2953 */ 2954 #define USB_EPENA0 (BIT(31)) 2955 #define USB_EPENA0_M (USB_EPENA0_V << USB_EPENA0_S) 2956 #define USB_EPENA0_V 0x00000001 2957 #define USB_EPENA0_S 31 2958 2959 2960 /** USB_DOEPTSIZ0_REG register 2961 * Device OUT Endpoint 0 Transfer Size Register 2962 */ 2963 #define USB_DOEPTSIZ0_REG (SOC_DPORT_USB_BASE + 0xb10) 2964 /** USB_XFERSIZE0 : R/W; bitpos: [7:0]; default: 0; 2965 * Transfer Size.Indicates the transfer size in bytes for ENDPOINT0 2966 */ 2967 #define USB_XFERSIZE0 0x0000007F 2968 #define USB_XFERSIZE0_M (USB_XFERSIZE0_V << USB_XFERSIZE0_S) 2969 #define USB_XFERSIZE0_V 0x0000007F 2970 #define USB_XFERSIZE0_S 0 2971 /** USB_PKTCNT0 : R/W; bitpos: [19]; default: 0; 2972 * Packet Count (PktCnt).This field is decremented to zero after a packet is written 2973 * into the RxFIFO. 2974 */ 2975 #define USB_PKTCNT0 (BIT(19)) 2976 #define USB_PKTCNT0_M (USB_PKTCNT0_V << USB_PKTCNT0_S) 2977 #define USB_PKTCNT0_V 0x00000001 2978 #define USB_PKTCNT0_S 19 2979 /** USB_SUPCNT0 : R/W; bitpos: [31:29]; default: 0; 2980 * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP 2981 * data packets the endpoint can receive 2982 * 2'b01: 1 packet 2983 * 2'b10: 2 packets 2984 * 2'b11: 3 packets 2985 */ 2986 #define USB_SUPCNT0 0x00000003 2987 #define USB_SUPCNT0_M (USB_SUPCNT0_V << USB_SUPCNT0_S) 2988 #define USB_SUPCNT0_V 0x00000003 2989 #define USB_SUPCNT0_S 29 2990 2991 2992 /** USB_DOEPDMA0_REG register 2993 * Device OUT Endpoint 0 DMA Address Register 2994 */ 2995 #define USB_DOEPDMA0_REG (SOC_DPORT_USB_BASE + 0xb14) 2996 /** USB_DMAADDR0 : R/W; bitpos: [32:0]; default: 0; 2997 * Holds the start address of the external memory for storing or fetching endpoint 2998 * data. 2999 */ 3000 #define USB_DMAADDR0 0xFFFFFFFF 3001 #define USB_DMAADDR0_M (USB_DMAADDR0_V << USB_DMAADDR0_S) 3002 #define USB_DMAADDR0_V 0xFFFFFFFF 3003 #define USB_DMAADDR0_S 0 3004 3005 3006 /** USB_DOEPDMAB0_REG register 3007 * Device OUT Endpoint 16 Buffer Address Register 3008 */ 3009 #define USB_DOEPDMAB0_REG (SOC_DPORT_USB_BASE + 0xb1c) 3010 /** USB_DMABUFFERADDR0 : R/W; bitpos: [32:0]; default: 0; 3011 * Holds the current buffer address.This register is updated as and when the data 3012 * transfer for the corresponding end point is in progress. This register is present 3013 * only in Scatter/Gather DMA mode. Otherwise this field is reserved. 3014 */ 3015 #define USB_DMABUFFERADDR0 0xFFFFFFFF 3016 #define USB_DMABUFFERADDR0_M (USB_DMABUFFERADDR0_V << USB_DMABUFFERADDR0_S) 3017 #define USB_DMABUFFERADDR0_V 0xFFFFFFFF 3018 #define USB_DMABUFFERADDR0_S 0 3019 3020 3021 /** USB_DOEPCTL1_REG register 3022 * Device Control OUT Endpoint 1 Control Register 3023 */ 3024 #define USB_DOEPCTL1_REG (SOC_DPORT_USB_BASE + 0xb20) 3025 /** USB_MPS1 : RO; bitpos: [11:0]; default: 0; 3026 * Maximum Packet Size in bytes 3027 */ 3028 #define USB_MPS1 0x000007FF 3029 #define USB_MPS1_M (USB_MPS1_V << USB_MPS1_S) 3030 #define USB_MPS1_V 0x000007FF 3031 #define USB_MPS1_S 0 3032 /** USB_USBACTEP1 : RO; bitpos: [15]; default: 1; 3033 * 0x1: USB Active Endpoint 0 3034 */ 3035 #define USB_USBACTEP1 (BIT(15)) 3036 #define USB_USBACTEP1_M (USB_USBACTEP1_V << USB_USBACTEP1_S) 3037 #define USB_USBACTEP1_V 0x00000001 3038 #define USB_USBACTEP1_S 15 3039 /** USB_NAKSTS1 : RO; bitpos: [17]; default: 0; 3040 * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status 3041 * 0x1 :The core is transmitting NAK handshakes on this endpoint 3042 */ 3043 #define USB_NAKSTS1 (BIT(17)) 3044 #define USB_NAKSTS1_M (USB_NAKSTS1_V << USB_NAKSTS1_S) 3045 #define USB_NAKSTS1_V 0x00000001 3046 #define USB_NAKSTS1_S 17 3047 /** USB_EPTYPE1 : RO; bitpos: [20:18]; default: 0; 3048 * Endpoint Type 3049 * 0x0 : Endpoint Control 1 3050 */ 3051 #define USB_EPTYPE1 0x00000003 3052 #define USB_EPTYPE1_M (USB_EPTYPE1_V << USB_EPTYPE1_S) 3053 #define USB_EPTYPE1_V 0x00000003 3054 #define USB_EPTYPE1_S 18 3055 /** USB_SNP1 : R/W; bitpos: [20]; default: 0; 3056 * 0x0 : Reserved 0 3057 * 0x1 : Reserved 1 3058 */ 3059 #define USB_SNP1 (BIT(20)) 3060 #define USB_SNP1_M (USB_SNP1_V << USB_SNP1_S) 3061 #define USB_SNP1_V 0x00000001 3062 #define USB_SNP1_S 20 3063 /** USB_STALL1 : R/W; bitpos: [21]; default: 0; 3064 * The application can only set this bit, and the core clears it, when a SETUP token 3065 * is received for this endpoint 3066 * 0x0 (INACTIVE): No Stall 3067 * 0x1 (ACTIVE): Stall Handshake 3068 */ 3069 #define USB_STALL1 (BIT(21)) 3070 #define USB_STALL1_M (USB_STALL1_V << USB_STALL1_S) 3071 #define USB_STALL1_V 0x00000001 3072 #define USB_STALL1_S 21 3073 /** USB_CNAK1 : WO; bitpos: [26]; default: 0; 3074 * 0x0 : No action 3075 * 0x1 : Clear NAK 3076 */ 3077 #define USB_CNAK1 (BIT(26)) 3078 #define USB_CNAK1_M (USB_CNAK1_V << USB_CNAK1_S) 3079 #define USB_CNAK1_V 0x00000001 3080 #define USB_CNAK1_S 26 3081 /** USB_DO_SNAK1 : WO; bitpos: [27]; default: 0; 3082 * A write to this bit sets the NAK bit for the endpoint 3083 * 0x0 : No action 3084 * 0x1 : Set NAK 3085 */ 3086 #define USB_DO_SNAK1 (BIT(27)) 3087 #define USB_DO_SNAK1_M (USB_DO_SNAK1_V << USB_DO_SNAK1_S) 3088 #define USB_DO_SNAK1_V 0x00000001 3089 #define USB_DO_SNAK1_S 27 3090 /** USB_DO_SETD0PID1 : WO; bitpos: [28]; default: 0; 3091 * Set DATA0 PID 3092 */ 3093 #define USB_DO_SETD0PID1 (BIT(28)) 3094 #define USB_DO_SETD0PID1_M (USB_DO_SETD0PID1_V << USB_DO_SETD0PID1_S) 3095 #define USB_DO_SETD0PID1_V 0x00000001 3096 #define USB_DO_SETD0PID1_S 28 3097 /** USB_DO_SETD1PID1 : WO; bitpos: [29]; default: 0; 3098 * Set DATA1 PID 3099 */ 3100 #define USB_DO_SETD1PID1 (BIT(29)) 3101 #define USB_DO_SETD1PID1_M (USB_DO_SETD1PID1_V << USB_DO_SETD1PID1_S) 3102 #define USB_DO_SETD1PID1_V 0x00000001 3103 #define USB_DO_SETD1PID1_S 29 3104 /** USB_EPDIS1 : RO; bitpos: [30]; default: 0; 3105 * Endpoint Disable 3106 * 0x0 : No Endpoint disable 3107 */ 3108 #define USB_EPDIS1 (BIT(30)) 3109 #define USB_EPDIS1_M (USB_EPDIS1_V << USB_EPDIS1_S) 3110 #define USB_EPDIS1_V 0x00000001 3111 #define USB_EPDIS1_S 30 3112 /** USB_EPENA1 : R/W; bitpos: [31]; default: 0; 3113 * Endpoint Enable 3114 * 0x0 : No action 3115 * 0x1 : Enable Endpoint 3116 */ 3117 #define USB_EPENA1 (BIT(31)) 3118 #define USB_EPENA1_M (USB_EPENA1_V << USB_EPENA1_S) 3119 #define USB_EPENA1_V 0x00000001 3120 #define USB_EPENA1_S 31 3121 3122 3123 /** USB_DOEPTSIZ1_REG register 3124 * Device OUT Endpoint 1 Transfer Size Register 3125 */ 3126 #define USB_DOEPTSIZ1_REG (SOC_DPORT_USB_BASE + 0xb30) 3127 /** USB_XFERSIZE1 : R/W; bitpos: [7:0]; default: 0; 3128 * Transfer Size.Indicates the transfer size in bytes for ENDPOINT1 3129 */ 3130 #define USB_XFERSIZE1 0x0000007F 3131 #define USB_XFERSIZE1_M (USB_XFERSIZE1_V << USB_XFERSIZE1_S) 3132 #define USB_XFERSIZE1_V 0x0000007F 3133 #define USB_XFERSIZE1_S 0 3134 /** USB_PKTCNT1 : R/W; bitpos: [19]; default: 0; 3135 * Packet Count (PktCnt).This field is decremented to zero after a packet is written 3136 * into the RxFIFO. 3137 */ 3138 #define USB_PKTCNT1 (BIT(19)) 3139 #define USB_PKTCNT1_M (USB_PKTCNT1_V << USB_PKTCNT1_S) 3140 #define USB_PKTCNT1_V 0x00000001 3141 #define USB_PKTCNT1_S 19 3142 /** USB_SUPCNT1 : R/W; bitpos: [31:29]; default: 0; 3143 * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP 3144 * data packets the endpoint can receive 3145 * 2'b01: 1 packet 3146 * 2'b10: 2 packets 3147 * 2'b11: 3 packets 3148 */ 3149 #define USB_SUPCNT1 0x00000003 3150 #define USB_SUPCNT1_M (USB_SUPCNT1_V << USB_SUPCNT1_S) 3151 #define USB_SUPCNT1_V 0x00000003 3152 #define USB_SUPCNT1_S 29 3153 3154 3155 /** USB_DOEPDMA1_REG register 3156 * Device OUT Endpoint 1 DMA Address Register 3157 */ 3158 #define USB_DOEPDMA1_REG (SOC_DPORT_USB_BASE + 0xb34) 3159 /** USB_DMAADDR1 : R/W; bitpos: [32:0]; default: 0; 3160 * Holds the start address of the external memory for storing or fetching endpoint 3161 * data. 3162 */ 3163 #define USB_DMAADDR1 0xFFFFFFFF 3164 #define USB_DMAADDR1_M (USB_DMAADDR1_V << USB_DMAADDR1_S) 3165 #define USB_DMAADDR1_V 0xFFFFFFFF 3166 #define USB_DMAADDR1_S 0 3167 3168 3169 /** USB_DOEPDMAB1_REG register 3170 * Device OUT Endpoint 16 Buffer Address Register 3171 */ 3172 #define USB_DOEPDMAB1_REG (SOC_DPORT_USB_BASE + 0xb3c) 3173 /** USB_DMABUFFERADDR1 : R/W; bitpos: [32:0]; default: 0; 3174 * Holds the current buffer address.This register is updated as and when the data 3175 * transfer for the corresponding end point is in progress. This register is present 3176 * only in Scatter/Gather DMA mode. Otherwise this field is reserved. 3177 */ 3178 #define USB_DMABUFFERADDR1 0xFFFFFFFF 3179 #define USB_DMABUFFERADDR1_M (USB_DMABUFFERADDR1_V << USB_DMABUFFERADDR1_S) 3180 #define USB_DMABUFFERADDR1_V 0xFFFFFFFF 3181 #define USB_DMABUFFERADDR1_S 0 3182 3183 3184 /** USB_DOEPCTL2_REG register 3185 * Device Control OUT Endpoint 2 Control Register 3186 */ 3187 #define USB_DOEPCTL2_REG (SOC_DPORT_USB_BASE + 0xb40) 3188 /** USB_MPS2 : RO; bitpos: [11:0]; default: 0; 3189 * Maximum Packet Size in bytes 3190 */ 3191 #define USB_MPS2 0x000007FF 3192 #define USB_MPS2_M (USB_MPS2_V << USB_MPS2_S) 3193 #define USB_MPS2_V 0x000007FF 3194 #define USB_MPS2_S 0 3195 /** USB_USBACTEP2 : RO; bitpos: [15]; default: 1; 3196 * 0x1: USB Active Endpoint 0 3197 */ 3198 #define USB_USBACTEP2 (BIT(15)) 3199 #define USB_USBACTEP2_M (USB_USBACTEP2_V << USB_USBACTEP2_S) 3200 #define USB_USBACTEP2_V 0x00000001 3201 #define USB_USBACTEP2_S 15 3202 /** USB_NAKSTS2 : RO; bitpos: [17]; default: 0; 3203 * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status 3204 * 0x1 :The core is transmitting NAK handshakes on this endpoint 3205 */ 3206 #define USB_NAKSTS2 (BIT(17)) 3207 #define USB_NAKSTS2_M (USB_NAKSTS2_V << USB_NAKSTS2_S) 3208 #define USB_NAKSTS2_V 0x00000001 3209 #define USB_NAKSTS2_S 17 3210 /** USB_EPTYPE2 : RO; bitpos: [20:18]; default: 0; 3211 * Endpoint Type 3212 * 0x0 : Endpoint Control 2 3213 */ 3214 #define USB_EPTYPE2 0x00000003 3215 #define USB_EPTYPE2_M (USB_EPTYPE2_V << USB_EPTYPE2_S) 3216 #define USB_EPTYPE2_V 0x00000003 3217 #define USB_EPTYPE2_S 18 3218 /** USB_SNP2 : R/W; bitpos: [20]; default: 0; 3219 * 0x0 : Reserved 0 3220 * 0x1 : Reserved 1 3221 */ 3222 #define USB_SNP2 (BIT(20)) 3223 #define USB_SNP2_M (USB_SNP2_V << USB_SNP2_S) 3224 #define USB_SNP2_V 0x00000001 3225 #define USB_SNP2_S 20 3226 /** USB_STALL2 : R/W; bitpos: [21]; default: 0; 3227 * The application can only set this bit, and the core clears it, when a SETUP token 3228 * is received for this endpoint 3229 * 0x0 (INACTIVE): No Stall 3230 * 0x1 (ACTIVE): Stall Handshake 3231 */ 3232 #define USB_STALL2 (BIT(21)) 3233 #define USB_STALL2_M (USB_STALL2_V << USB_STALL2_S) 3234 #define USB_STALL2_V 0x00000001 3235 #define USB_STALL2_S 21 3236 /** USB_CNAK2 : WO; bitpos: [26]; default: 0; 3237 * 0x0 : No action 3238 * 0x1 : Clear NAK 3239 */ 3240 #define USB_CNAK2 (BIT(26)) 3241 #define USB_CNAK2_M (USB_CNAK2_V << USB_CNAK2_S) 3242 #define USB_CNAK2_V 0x00000001 3243 #define USB_CNAK2_S 26 3244 /** USB_DO_SNAK2 : WO; bitpos: [27]; default: 0; 3245 * A write to this bit sets the NAK bit for the endpoint 3246 * 0x0 : No action 3247 * 0x1 : Set NAK 3248 */ 3249 #define USB_DO_SNAK2 (BIT(27)) 3250 #define USB_DO_SNAK2_M (USB_DO_SNAK2_V << USB_DO_SNAK2_S) 3251 #define USB_DO_SNAK2_V 0x00000001 3252 #define USB_DO_SNAK2_S 27 3253 /** USB_DO_SETD0PID2 : WO; bitpos: [28]; default: 0; 3254 * Set DATA0 PID 3255 */ 3256 #define USB_DO_SETD0PID2 (BIT(28)) 3257 #define USB_DO_SETD0PID2_M (USB_DO_SETD0PID2_V << USB_DO_SETD0PID2_S) 3258 #define USB_DO_SETD0PID2_V 0x00000001 3259 #define USB_DO_SETD0PID2_S 28 3260 /** USB_DO_SETD1PID2 : WO; bitpos: [29]; default: 0; 3261 * Set DATA1 PID 3262 */ 3263 #define USB_DO_SETD1PID2 (BIT(29)) 3264 #define USB_DO_SETD1PID2_M (USB_DO_SETD1PID2_V << USB_DO_SETD1PID2_S) 3265 #define USB_DO_SETD1PID2_V 0x00000001 3266 #define USB_DO_SETD1PID2_S 29 3267 /** USB_EPDIS2 : RO; bitpos: [30]; default: 0; 3268 * Endpoint Disable 3269 * 0x0 : No Endpoint disable 3270 */ 3271 #define USB_EPDIS2 (BIT(30)) 3272 #define USB_EPDIS2_M (USB_EPDIS2_V << USB_EPDIS2_S) 3273 #define USB_EPDIS2_V 0x00000001 3274 #define USB_EPDIS2_S 30 3275 /** USB_EPENA2 : R/W; bitpos: [31]; default: 0; 3276 * Endpoint Enable 3277 * 0x0 : No action 3278 * 0x1 : Enable Endpoint 3279 */ 3280 #define USB_EPENA2 (BIT(31)) 3281 #define USB_EPENA2_M (USB_EPENA2_V << USB_EPENA2_S) 3282 #define USB_EPENA2_V 0x00000001 3283 #define USB_EPENA2_S 31 3284 3285 3286 /** USB_DOEPTSIZ2_REG register 3287 * Device OUT Endpoint 2 Transfer Size Register 3288 */ 3289 #define USB_DOEPTSIZ2_REG (SOC_DPORT_USB_BASE + 0xb50) 3290 /** USB_XFERSIZE2 : R/W; bitpos: [7:0]; default: 0; 3291 * Transfer Size.Indicates the transfer size in bytes for ENDPOINT2 3292 */ 3293 #define USB_XFERSIZE2 0x0000007F 3294 #define USB_XFERSIZE2_M (USB_XFERSIZE2_V << USB_XFERSIZE2_S) 3295 #define USB_XFERSIZE2_V 0x0000007F 3296 #define USB_XFERSIZE2_S 0 3297 /** USB_PKTCNT2 : R/W; bitpos: [19]; default: 0; 3298 * Packet Count (PktCnt).This field is decremented to zero after a packet is written 3299 * into the RxFIFO. 3300 */ 3301 #define USB_PKTCNT2 (BIT(19)) 3302 #define USB_PKTCNT2_M (USB_PKTCNT2_V << USB_PKTCNT2_S) 3303 #define USB_PKTCNT2_V 0x00000001 3304 #define USB_PKTCNT2_S 19 3305 /** USB_SUPCNT2 : R/W; bitpos: [31:29]; default: 0; 3306 * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP 3307 * data packets the endpoint can receive 3308 * 2'b01: 1 packet 3309 * 2'b10: 2 packets 3310 * 2'b11: 3 packets 3311 */ 3312 #define USB_SUPCNT2 0x00000003 3313 #define USB_SUPCNT2_M (USB_SUPCNT2_V << USB_SUPCNT2_S) 3314 #define USB_SUPCNT2_V 0x00000003 3315 #define USB_SUPCNT2_S 29 3316 3317 3318 /** USB_DOEPDMA2_REG register 3319 * Device OUT Endpoint 2 DMA Address Register 3320 */ 3321 #define USB_DOEPDMA2_REG (SOC_DPORT_USB_BASE + 0xb54) 3322 /** USB_DMAADDR2 : R/W; bitpos: [32:0]; default: 0; 3323 * Holds the start address of the external memory for storing or fetching endpoint 3324 * data. 3325 */ 3326 #define USB_DMAADDR2 0xFFFFFFFF 3327 #define USB_DMAADDR2_M (USB_DMAADDR2_V << USB_DMAADDR2_S) 3328 #define USB_DMAADDR2_V 0xFFFFFFFF 3329 #define USB_DMAADDR2_S 0 3330 3331 3332 /** USB_DOEPDMAB2_REG register 3333 * Device OUT Endpoint 16 Buffer Address Register 3334 */ 3335 #define USB_DOEPDMAB2_REG (SOC_DPORT_USB_BASE + 0xb5c) 3336 /** USB_DMABUFFERADDR2 : R/W; bitpos: [32:0]; default: 0; 3337 * Holds the current buffer address.This register is updated as and when the data 3338 * transfer for the corresponding end point is in progress. This register is present 3339 * only in Scatter/Gather DMA mode. Otherwise this field is reserved. 3340 */ 3341 #define USB_DMABUFFERADDR2 0xFFFFFFFF 3342 #define USB_DMABUFFERADDR2_M (USB_DMABUFFERADDR2_V << USB_DMABUFFERADDR2_S) 3343 #define USB_DMABUFFERADDR2_V 0xFFFFFFFF 3344 #define USB_DMABUFFERADDR2_S 0 3345 3346 3347 /** USB_DOEPCTL3_REG register 3348 * Device Control OUT Endpoint 3 Control Register 3349 */ 3350 #define USB_DOEPCTL3_REG (SOC_DPORT_USB_BASE + 0xb60) 3351 /** USB_MPS3 : RO; bitpos: [11:0]; default: 0; 3352 * Maximum Packet Size in bytes 3353 */ 3354 #define USB_MPS3 0x000007FF 3355 #define USB_MPS3_M (USB_MPS3_V << USB_MPS3_S) 3356 #define USB_MPS3_V 0x000007FF 3357 #define USB_MPS3_S 0 3358 /** USB_USBACTEP3 : RO; bitpos: [15]; default: 1; 3359 * 0x1: USB Active Endpoint 0 3360 */ 3361 #define USB_USBACTEP3 (BIT(15)) 3362 #define USB_USBACTEP3_M (USB_USBACTEP3_V << USB_USBACTEP3_S) 3363 #define USB_USBACTEP3_V 0x00000001 3364 #define USB_USBACTEP3_S 15 3365 /** USB_NAKSTS3 : RO; bitpos: [17]; default: 0; 3366 * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status 3367 * 0x1 :The core is transmitting NAK handshakes on this endpoint 3368 */ 3369 #define USB_NAKSTS3 (BIT(17)) 3370 #define USB_NAKSTS3_M (USB_NAKSTS3_V << USB_NAKSTS3_S) 3371 #define USB_NAKSTS3_V 0x00000001 3372 #define USB_NAKSTS3_S 17 3373 /** USB_EPTYPE3 : RO; bitpos: [20:18]; default: 0; 3374 * Endpoint Type 3375 * 0x0 : Endpoint Control 3 3376 */ 3377 #define USB_EPTYPE3 0x00000003 3378 #define USB_EPTYPE3_M (USB_EPTYPE3_V << USB_EPTYPE3_S) 3379 #define USB_EPTYPE3_V 0x00000003 3380 #define USB_EPTYPE3_S 18 3381 /** USB_SNP3 : R/W; bitpos: [20]; default: 0; 3382 * 0x0 : Reserved 0 3383 * 0x1 : Reserved 1 3384 */ 3385 #define USB_SNP3 (BIT(20)) 3386 #define USB_SNP3_M (USB_SNP3_V << USB_SNP3_S) 3387 #define USB_SNP3_V 0x00000001 3388 #define USB_SNP3_S 20 3389 /** USB_STALL3 : R/W; bitpos: [21]; default: 0; 3390 * The application can only set this bit, and the core clears it, when a SETUP token 3391 * is received for this endpoint 3392 * 0x0 (INACTIVE): No Stall 3393 * 0x1 (ACTIVE): Stall Handshake 3394 */ 3395 #define USB_STALL3 (BIT(21)) 3396 #define USB_STALL3_M (USB_STALL3_V << USB_STALL3_S) 3397 #define USB_STALL3_V 0x00000001 3398 #define USB_STALL3_S 21 3399 /** USB_CNAK3 : WO; bitpos: [26]; default: 0; 3400 * 0x0 : No action 3401 * 0x1 : Clear NAK 3402 */ 3403 #define USB_CNAK3 (BIT(26)) 3404 #define USB_CNAK3_M (USB_CNAK3_V << USB_CNAK3_S) 3405 #define USB_CNAK3_V 0x00000001 3406 #define USB_CNAK3_S 26 3407 /** USB_DO_SNAK3 : WO; bitpos: [27]; default: 0; 3408 * A write to this bit sets the NAK bit for the endpoint 3409 * 0x0 : No action 3410 * 0x1 : Set NAK 3411 */ 3412 #define USB_DO_SNAK3 (BIT(27)) 3413 #define USB_DO_SNAK3_M (USB_DO_SNAK3_V << USB_DO_SNAK3_S) 3414 #define USB_DO_SNAK3_V 0x00000001 3415 #define USB_DO_SNAK3_S 27 3416 /** USB_DO_SETD0PID3 : WO; bitpos: [28]; default: 0; 3417 * Set DATA0 PID 3418 */ 3419 #define USB_DO_SETD0PID3 (BIT(28)) 3420 #define USB_DO_SETD0PID3_M (USB_DO_SETD0PID3_V << USB_DO_SETD0PID3_S) 3421 #define USB_DO_SETD0PID3_V 0x00000001 3422 #define USB_DO_SETD0PID3_S 28 3423 /** USB_DO_SETD1PID3 : WO; bitpos: [29]; default: 0; 3424 * Set DATA1 PID 3425 */ 3426 #define USB_DO_SETD1PID3 (BIT(29)) 3427 #define USB_DO_SETD1PID3_M (USB_DO_SETD1PID3_V << USB_DO_SETD1PID3_S) 3428 #define USB_DO_SETD1PID3_V 0x00000001 3429 #define USB_DO_SETD1PID3_S 29 3430 /** USB_EPDIS3 : RO; bitpos: [30]; default: 0; 3431 * Endpoint Disable 3432 * 0x0 : No Endpoint disable 3433 */ 3434 #define USB_EPDIS3 (BIT(30)) 3435 #define USB_EPDIS3_M (USB_EPDIS3_V << USB_EPDIS3_S) 3436 #define USB_EPDIS3_V 0x00000001 3437 #define USB_EPDIS3_S 30 3438 /** USB_EPENA3 : R/W; bitpos: [31]; default: 0; 3439 * Endpoint Enable 3440 * 0x0 : No action 3441 * 0x1 : Enable Endpoint 3442 */ 3443 #define USB_EPENA3 (BIT(31)) 3444 #define USB_EPENA3_M (USB_EPENA3_V << USB_EPENA3_S) 3445 #define USB_EPENA3_V 0x00000001 3446 #define USB_EPENA3_S 31 3447 3448 3449 /** USB_DOEPTSIZ3_REG register 3450 * Device OUT Endpoint 3 Transfer Size Register 3451 */ 3452 #define USB_DOEPTSIZ3_REG (SOC_DPORT_USB_BASE + 0xb70) 3453 /** USB_XFERSIZE3 : R/W; bitpos: [7:0]; default: 0; 3454 * Transfer Size.Indicates the transfer size in bytes for ENDPOINT3 3455 */ 3456 #define USB_XFERSIZE3 0x0000007F 3457 #define USB_XFERSIZE3_M (USB_XFERSIZE3_V << USB_XFERSIZE3_S) 3458 #define USB_XFERSIZE3_V 0x0000007F 3459 #define USB_XFERSIZE3_S 0 3460 /** USB_PKTCNT3 : R/W; bitpos: [19]; default: 0; 3461 * Packet Count (PktCnt).This field is decremented to zero after a packet is written 3462 * into the RxFIFO. 3463 */ 3464 #define USB_PKTCNT3 (BIT(19)) 3465 #define USB_PKTCNT3_M (USB_PKTCNT3_V << USB_PKTCNT3_S) 3466 #define USB_PKTCNT3_V 0x00000001 3467 #define USB_PKTCNT3_S 19 3468 /** USB_SUPCNT3 : R/W; bitpos: [31:29]; default: 0; 3469 * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP 3470 * data packets the endpoint can receive 3471 * 2'b01: 1 packet 3472 * 2'b10: 2 packets 3473 * 2'b11: 3 packets 3474 */ 3475 #define USB_SUPCNT3 0x00000003 3476 #define USB_SUPCNT3_M (USB_SUPCNT3_V << USB_SUPCNT3_S) 3477 #define USB_SUPCNT3_V 0x00000003 3478 #define USB_SUPCNT3_S 29 3479 3480 3481 /** USB_DOEPDMA3_REG register 3482 * Device OUT Endpoint 3 DMA Address Register 3483 */ 3484 #define USB_DOEPDMA3_REG (SOC_DPORT_USB_BASE + 0xb74) 3485 /** USB_DMAADDR3 : R/W; bitpos: [32:0]; default: 0; 3486 * Holds the start address of the external memory for storing or fetching endpoint 3487 * data. 3488 */ 3489 #define USB_DMAADDR3 0xFFFFFFFF 3490 #define USB_DMAADDR3_M (USB_DMAADDR3_V << USB_DMAADDR3_S) 3491 #define USB_DMAADDR3_V 0xFFFFFFFF 3492 #define USB_DMAADDR3_S 0 3493 3494 3495 /** USB_DOEPDMAB3_REG register 3496 * Device OUT Endpoint 16 Buffer Address Register 3497 */ 3498 #define USB_DOEPDMAB3_REG (SOC_DPORT_USB_BASE + 0xb7c) 3499 /** USB_DMABUFFERADDR3 : R/W; bitpos: [32:0]; default: 0; 3500 * Holds the current buffer address.This register is updated as and when the data 3501 * transfer for the corresponding end point is in progress. This register is present 3502 * only in Scatter/Gather DMA mode. Otherwise this field is reserved. 3503 */ 3504 #define USB_DMABUFFERADDR3 0xFFFFFFFF 3505 #define USB_DMABUFFERADDR3_M (USB_DMABUFFERADDR3_V << USB_DMABUFFERADDR3_S) 3506 #define USB_DMABUFFERADDR3_V 0xFFFFFFFF 3507 #define USB_DMABUFFERADDR3_S 0 3508 3509 3510 /** USB_DOEPCTL4_REG register 3511 * Device Control OUT Endpoint 4 Control Register 3512 */ 3513 #define USB_DOEPCTL4_REG (SOC_DPORT_USB_BASE + 0xb80) 3514 /** USB_MPS4 : RO; bitpos: [11:0]; default: 0; 3515 * Maximum Packet Size in bytes 3516 */ 3517 #define USB_MPS4 0x000007FF 3518 #define USB_MPS4_M (USB_MPS4_V << USB_MPS4_S) 3519 #define USB_MPS4_V 0x000007FF 3520 #define USB_MPS4_S 0 3521 /** USB_USBACTEP4 : RO; bitpos: [15]; default: 1; 3522 * 0x1: USB Active Endpoint 0 3523 */ 3524 #define USB_USBACTEP4 (BIT(15)) 3525 #define USB_USBACTEP4_M (USB_USBACTEP4_V << USB_USBACTEP4_S) 3526 #define USB_USBACTEP4_V 0x00000001 3527 #define USB_USBACTEP4_S 15 3528 /** USB_NAKSTS4 : RO; bitpos: [17]; default: 0; 3529 * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status 3530 * 0x1 :The core is transmitting NAK handshakes on this endpoint 3531 */ 3532 #define USB_NAKSTS4 (BIT(17)) 3533 #define USB_NAKSTS4_M (USB_NAKSTS4_V << USB_NAKSTS4_S) 3534 #define USB_NAKSTS4_V 0x00000001 3535 #define USB_NAKSTS4_S 17 3536 /** USB_EPTYPE4 : RO; bitpos: [20:18]; default: 0; 3537 * Endpoint Type 3538 * 0x0 : Endpoint Control 4 3539 */ 3540 #define USB_EPTYPE4 0x00000003 3541 #define USB_EPTYPE4_M (USB_EPTYPE4_V << USB_EPTYPE4_S) 3542 #define USB_EPTYPE4_V 0x00000003 3543 #define USB_EPTYPE4_S 18 3544 /** USB_SNP4 : R/W; bitpos: [20]; default: 0; 3545 * 0x0 : Reserved 0 3546 * 0x1 : Reserved 1 3547 */ 3548 #define USB_SNP4 (BIT(20)) 3549 #define USB_SNP4_M (USB_SNP4_V << USB_SNP4_S) 3550 #define USB_SNP4_V 0x00000001 3551 #define USB_SNP4_S 20 3552 /** USB_STALL4 : R/W; bitpos: [21]; default: 0; 3553 * The application can only set this bit, and the core clears it, when a SETUP token 3554 * is received for this endpoint 3555 * 0x0 (INACTIVE): No Stall 3556 * 0x1 (ACTIVE): Stall Handshake 3557 */ 3558 #define USB_STALL4 (BIT(21)) 3559 #define USB_STALL4_M (USB_STALL4_V << USB_STALL4_S) 3560 #define USB_STALL4_V 0x00000001 3561 #define USB_STALL4_S 21 3562 /** USB_CNAK4 : WO; bitpos: [26]; default: 0; 3563 * 0x0 : No action 3564 * 0x1 : Clear NAK 3565 */ 3566 #define USB_CNAK4 (BIT(26)) 3567 #define USB_CNAK4_M (USB_CNAK4_V << USB_CNAK4_S) 3568 #define USB_CNAK4_V 0x00000001 3569 #define USB_CNAK4_S 26 3570 /** USB_DO_SNAK4 : WO; bitpos: [27]; default: 0; 3571 * A write to this bit sets the NAK bit for the endpoint 3572 * 0x0 : No action 3573 * 0x1 : Set NAK 3574 */ 3575 #define USB_DO_SNAK4 (BIT(27)) 3576 #define USB_DO_SNAK4_M (USB_DO_SNAK4_V << USB_DO_SNAK4_S) 3577 #define USB_DO_SNAK4_V 0x00000001 3578 #define USB_DO_SNAK4_S 27 3579 /** USB_DO_SETD0PID4 : WO; bitpos: [28]; default: 0; 3580 * Set DATA0 PID 3581 */ 3582 #define USB_DO_SETD0PID4 (BIT(28)) 3583 #define USB_DO_SETD0PID4_M (USB_DO_SETD0PID4_V << USB_DO_SETD0PID4_S) 3584 #define USB_DO_SETD0PID4_V 0x00000001 3585 #define USB_DO_SETD0PID4_S 28 3586 /** USB_DO_SETD1PID4 : WO; bitpos: [29]; default: 0; 3587 * Set DATA1 PID 3588 */ 3589 #define USB_DO_SETD1PID4 (BIT(29)) 3590 #define USB_DO_SETD1PID4_M (USB_DO_SETD1PID4_V << USB_DO_SETD1PID4_S) 3591 #define USB_DO_SETD1PID4_V 0x00000001 3592 #define USB_DO_SETD1PID4_S 29 3593 /** USB_EPDIS4 : RO; bitpos: [30]; default: 0; 3594 * Endpoint Disable 3595 * 0x0 : No Endpoint disable 3596 */ 3597 #define USB_EPDIS4 (BIT(30)) 3598 #define USB_EPDIS4_M (USB_EPDIS4_V << USB_EPDIS4_S) 3599 #define USB_EPDIS4_V 0x00000001 3600 #define USB_EPDIS4_S 30 3601 /** USB_EPENA4 : R/W; bitpos: [31]; default: 0; 3602 * Endpoint Enable 3603 * 0x0 : No action 3604 * 0x1 : Enable Endpoint 3605 */ 3606 #define USB_EPENA4 (BIT(31)) 3607 #define USB_EPENA4_M (USB_EPENA4_V << USB_EPENA4_S) 3608 #define USB_EPENA4_V 0x00000001 3609 #define USB_EPENA4_S 31 3610 3611 3612 /** USB_DOEPTSIZ4_REG register 3613 * Device OUT Endpoint 4 Transfer Size Register 3614 */ 3615 #define USB_DOEPTSIZ4_REG (SOC_DPORT_USB_BASE + 0xb90) 3616 /** USB_XFERSIZE4 : R/W; bitpos: [7:0]; default: 0; 3617 * Transfer Size.Indicates the transfer size in bytes for ENDPOINT4 3618 */ 3619 #define USB_XFERSIZE4 0x0000007F 3620 #define USB_XFERSIZE4_M (USB_XFERSIZE4_V << USB_XFERSIZE4_S) 3621 #define USB_XFERSIZE4_V 0x0000007F 3622 #define USB_XFERSIZE4_S 0 3623 /** USB_PKTCNT4 : R/W; bitpos: [19]; default: 0; 3624 * Packet Count (PktCnt).This field is decremented to zero after a packet is written 3625 * into the RxFIFO. 3626 */ 3627 #define USB_PKTCNT4 (BIT(19)) 3628 #define USB_PKTCNT4_M (USB_PKTCNT4_V << USB_PKTCNT4_S) 3629 #define USB_PKTCNT4_V 0x00000001 3630 #define USB_PKTCNT4_S 19 3631 /** USB_SUPCNT4 : R/W; bitpos: [31:29]; default: 0; 3632 * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP 3633 * data packets the endpoint can receive 3634 * 2'b01: 1 packet 3635 * 2'b10: 2 packets 3636 * 2'b11: 3 packets 3637 */ 3638 #define USB_SUPCNT4 0x00000003 3639 #define USB_SUPCNT4_M (USB_SUPCNT4_V << USB_SUPCNT4_S) 3640 #define USB_SUPCNT4_V 0x00000003 3641 #define USB_SUPCNT4_S 29 3642 3643 3644 /** USB_DOEPDMA4_REG register 3645 * Device OUT Endpoint 4 DMA Address Register 3646 */ 3647 #define USB_DOEPDMA4_REG (SOC_DPORT_USB_BASE + 0xb94) 3648 /** USB_DMAADDR4 : R/W; bitpos: [32:0]; default: 0; 3649 * Holds the start address of the external memory for storing or fetching endpoint 3650 * data. 3651 */ 3652 #define USB_DMAADDR4 0xFFFFFFFF 3653 #define USB_DMAADDR4_M (USB_DMAADDR4_V << USB_DMAADDR4_S) 3654 #define USB_DMAADDR4_V 0xFFFFFFFF 3655 #define USB_DMAADDR4_S 0 3656 3657 3658 /** USB_DOEPDMAB4_REG register 3659 * Device OUT Endpoint 16 Buffer Address Register 3660 */ 3661 #define USB_DOEPDMAB4_REG (SOC_DPORT_USB_BASE + 0xb9c) 3662 /** USB_DMABUFFERADDR4 : R/W; bitpos: [32:0]; default: 0; 3663 * Holds the current buffer address.This register is updated as and when the data 3664 * transfer for the corresponding end point is in progress. This register is present 3665 * only in Scatter/Gather DMA mode. Otherwise this field is reserved. 3666 */ 3667 #define USB_DMABUFFERADDR4 0xFFFFFFFF 3668 #define USB_DMABUFFERADDR4_M (USB_DMABUFFERADDR4_V << USB_DMABUFFERADDR4_S) 3669 #define USB_DMABUFFERADDR4_V 0xFFFFFFFF 3670 #define USB_DMABUFFERADDR4_S 0 3671 3672 3673 /** USB_DOEPCTL5_REG register 3674 * Device Control OUT Endpoint 5 Control Register 3675 */ 3676 #define USB_DOEPCTL5_REG (SOC_DPORT_USB_BASE + 0xba0) 3677 /** USB_MPS5 : RO; bitpos: [11:0]; default: 0; 3678 * Maximum Packet Size in bytes 3679 */ 3680 #define USB_MPS5 0x000007FF 3681 #define USB_MPS5_M (USB_MPS5_V << USB_MPS5_S) 3682 #define USB_MPS5_V 0x000007FF 3683 #define USB_MPS5_S 0 3684 /** USB_USBACTEP5 : RO; bitpos: [15]; default: 1; 3685 * 0x1: USB Active Endpoint 0 3686 */ 3687 #define USB_USBACTEP5 (BIT(15)) 3688 #define USB_USBACTEP5_M (USB_USBACTEP5_V << USB_USBACTEP5_S) 3689 #define USB_USBACTEP5_V 0x00000001 3690 #define USB_USBACTEP5_S 15 3691 /** USB_NAKSTS5 : RO; bitpos: [17]; default: 0; 3692 * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status 3693 * 0x1 :The core is transmitting NAK handshakes on this endpoint 3694 */ 3695 #define USB_NAKSTS5 (BIT(17)) 3696 #define USB_NAKSTS5_M (USB_NAKSTS5_V << USB_NAKSTS5_S) 3697 #define USB_NAKSTS5_V 0x00000001 3698 #define USB_NAKSTS5_S 17 3699 /** USB_EPTYPE5 : RO; bitpos: [20:18]; default: 0; 3700 * Endpoint Type 3701 * 0x0 : Endpoint Control 5 3702 */ 3703 #define USB_EPTYPE5 0x00000003 3704 #define USB_EPTYPE5_M (USB_EPTYPE5_V << USB_EPTYPE5_S) 3705 #define USB_EPTYPE5_V 0x00000003 3706 #define USB_EPTYPE5_S 18 3707 /** USB_SNP5 : R/W; bitpos: [20]; default: 0; 3708 * 0x0 : Reserved 0 3709 * 0x1 : Reserved 1 3710 */ 3711 #define USB_SNP5 (BIT(20)) 3712 #define USB_SNP5_M (USB_SNP5_V << USB_SNP5_S) 3713 #define USB_SNP5_V 0x00000001 3714 #define USB_SNP5_S 20 3715 /** USB_STALL5 : R/W; bitpos: [21]; default: 0; 3716 * The application can only set this bit, and the core clears it, when a SETUP token 3717 * is received for this endpoint 3718 * 0x0 (INACTIVE): No Stall 3719 * 0x1 (ACTIVE): Stall Handshake 3720 */ 3721 #define USB_STALL5 (BIT(21)) 3722 #define USB_STALL5_M (USB_STALL5_V << USB_STALL5_S) 3723 #define USB_STALL5_V 0x00000001 3724 #define USB_STALL5_S 21 3725 /** USB_CNAK5 : WO; bitpos: [26]; default: 0; 3726 * 0x0 : No action 3727 * 0x1 : Clear NAK 3728 */ 3729 #define USB_CNAK5 (BIT(26)) 3730 #define USB_CNAK5_M (USB_CNAK5_V << USB_CNAK5_S) 3731 #define USB_CNAK5_V 0x00000001 3732 #define USB_CNAK5_S 26 3733 /** USB_DO_SNAK5 : WO; bitpos: [27]; default: 0; 3734 * A write to this bit sets the NAK bit for the endpoint 3735 * 0x0 : No action 3736 * 0x1 : Set NAK 3737 */ 3738 #define USB_DO_SNAK5 (BIT(27)) 3739 #define USB_DO_SNAK5_M (USB_DO_SNAK5_V << USB_DO_SNAK5_S) 3740 #define USB_DO_SNAK5_V 0x00000001 3741 #define USB_DO_SNAK5_S 27 3742 /** USB_DO_SETD0PID5 : WO; bitpos: [28]; default: 0; 3743 * Set DATA0 PID 3744 */ 3745 #define USB_DO_SETD0PID5 (BIT(28)) 3746 #define USB_DO_SETD0PID5_M (USB_DO_SETD0PID5_V << USB_DO_SETD0PID5_S) 3747 #define USB_DO_SETD0PID5_V 0x00000001 3748 #define USB_DO_SETD0PID5_S 28 3749 /** USB_DO_SETD1PID5 : WO; bitpos: [29]; default: 0; 3750 * Set DATA1 PID 3751 */ 3752 #define USB_DO_SETD1PID5 (BIT(29)) 3753 #define USB_DO_SETD1PID5_M (USB_DO_SETD1PID5_V << USB_DO_SETD1PID5_S) 3754 #define USB_DO_SETD1PID5_V 0x00000001 3755 #define USB_DO_SETD1PID5_S 29 3756 /** USB_EPDIS5 : RO; bitpos: [30]; default: 0; 3757 * Endpoint Disable 3758 * 0x0 : No Endpoint disable 3759 */ 3760 #define USB_EPDIS5 (BIT(30)) 3761 #define USB_EPDIS5_M (USB_EPDIS5_V << USB_EPDIS5_S) 3762 #define USB_EPDIS5_V 0x00000001 3763 #define USB_EPDIS5_S 30 3764 /** USB_EPENA5 : R/W; bitpos: [31]; default: 0; 3765 * Endpoint Enable 3766 * 0x0 : No action 3767 * 0x1 : Enable Endpoint 3768 */ 3769 #define USB_EPENA5 (BIT(31)) 3770 #define USB_EPENA5_M (USB_EPENA5_V << USB_EPENA5_S) 3771 #define USB_EPENA5_V 0x00000001 3772 #define USB_EPENA5_S 31 3773 3774 3775 /** USB_DOEPTSIZ5_REG register 3776 * Device OUT Endpoint 5 Transfer Size Register 3777 */ 3778 #define USB_DOEPTSIZ5_REG (SOC_DPORT_USB_BASE + 0xbb0) 3779 /** USB_XFERSIZE5 : R/W; bitpos: [7:0]; default: 0; 3780 * Transfer Size.Indicates the transfer size in bytes for ENDPOINT5 3781 */ 3782 #define USB_XFERSIZE5 0x0000007F 3783 #define USB_XFERSIZE5_M (USB_XFERSIZE5_V << USB_XFERSIZE5_S) 3784 #define USB_XFERSIZE5_V 0x0000007F 3785 #define USB_XFERSIZE5_S 0 3786 /** USB_PKTCNT5 : R/W; bitpos: [19]; default: 0; 3787 * Packet Count (PktCnt).This field is decremented to zero after a packet is written 3788 * into the RxFIFO. 3789 */ 3790 #define USB_PKTCNT5 (BIT(19)) 3791 #define USB_PKTCNT5_M (USB_PKTCNT5_V << USB_PKTCNT5_S) 3792 #define USB_PKTCNT5_V 0x00000001 3793 #define USB_PKTCNT5_S 19 3794 /** USB_SUPCNT5 : R/W; bitpos: [31:29]; default: 0; 3795 * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP 3796 * data packets the endpoint can receive 3797 * 2'b01: 1 packet 3798 * 2'b10: 2 packets 3799 * 2'b11: 3 packets 3800 */ 3801 #define USB_SUPCNT5 0x00000003 3802 #define USB_SUPCNT5_M (USB_SUPCNT5_V << USB_SUPCNT5_S) 3803 #define USB_SUPCNT5_V 0x00000003 3804 #define USB_SUPCNT5_S 29 3805 3806 3807 /** USB_DOEPDMA5_REG register 3808 * Device OUT Endpoint 5 DMA Address Register 3809 */ 3810 #define USB_DOEPDMA5_REG (SOC_DPORT_USB_BASE + 0xbb4) 3811 /** USB_DMAADDR5 : R/W; bitpos: [32:0]; default: 0; 3812 * Holds the start address of the external memory for storing or fetching endpoint 3813 * data. 3814 */ 3815 #define USB_DMAADDR5 0xFFFFFFFF 3816 #define USB_DMAADDR5_M (USB_DMAADDR5_V << USB_DMAADDR5_S) 3817 #define USB_DMAADDR5_V 0xFFFFFFFF 3818 #define USB_DMAADDR5_S 0 3819 3820 3821 /** USB_DOEPDMAB5_REG register 3822 * Device OUT Endpoint 16 Buffer Address Register 3823 */ 3824 #define USB_DOEPDMAB5_REG (SOC_DPORT_USB_BASE + 0xbbc) 3825 /** USB_DMABUFFERADDR5 : R/W; bitpos: [32:0]; default: 0; 3826 * Holds the current buffer address.This register is updated as and when the data 3827 * transfer for the corresponding end point is in progress. This register is present 3828 * only in Scatter/Gather DMA mode. Otherwise this field is reserved. 3829 */ 3830 #define USB_DMABUFFERADDR5 0xFFFFFFFF 3831 #define USB_DMABUFFERADDR5_M (USB_DMABUFFERADDR5_V << USB_DMABUFFERADDR5_S) 3832 #define USB_DMABUFFERADDR5_V 0xFFFFFFFF 3833 #define USB_DMABUFFERADDR5_S 0 3834 3835 3836 /** USB_DOEPCTL6_REG register 3837 * Device Control OUT Endpoint 6 Control Register 3838 */ 3839 #define USB_DOEPCTL6_REG (SOC_DPORT_USB_BASE + 0xbc0) 3840 /** USB_MPS6 : RO; bitpos: [11:0]; default: 0; 3841 * Maximum Packet Size in bytes 3842 */ 3843 #define USB_MPS6 0x000007FF 3844 #define USB_MPS6_M (USB_MPS6_V << USB_MPS6_S) 3845 #define USB_MPS6_V 0x000007FF 3846 #define USB_MPS6_S 0 3847 /** USB_USBACTEP6 : RO; bitpos: [15]; default: 1; 3848 * 0x1: USB Active Endpoint 0 3849 */ 3850 #define USB_USBACTEP6 (BIT(15)) 3851 #define USB_USBACTEP6_M (USB_USBACTEP6_V << USB_USBACTEP6_S) 3852 #define USB_USBACTEP6_V 0x00000001 3853 #define USB_USBACTEP6_S 15 3854 /** USB_NAKSTS6 : RO; bitpos: [17]; default: 0; 3855 * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status 3856 * 0x1 :The core is transmitting NAK handshakes on this endpoint 3857 */ 3858 #define USB_NAKSTS6 (BIT(17)) 3859 #define USB_NAKSTS6_M (USB_NAKSTS6_V << USB_NAKSTS6_S) 3860 #define USB_NAKSTS6_V 0x00000001 3861 #define USB_NAKSTS6_S 17 3862 /** USB_EPTYPE6 : RO; bitpos: [20:18]; default: 0; 3863 * Endpoint Type 3864 * 0x0 : Endpoint Control 6 3865 */ 3866 #define USB_EPTYPE6 0x00000003 3867 #define USB_EPTYPE6_M (USB_EPTYPE6_V << USB_EPTYPE6_S) 3868 #define USB_EPTYPE6_V 0x00000003 3869 #define USB_EPTYPE6_S 18 3870 /** USB_SNP6 : R/W; bitpos: [20]; default: 0; 3871 * 0x0 : Reserved 0 3872 * 0x1 : Reserved 1 3873 */ 3874 #define USB_SNP6 (BIT(20)) 3875 #define USB_SNP6_M (USB_SNP6_V << USB_SNP6_S) 3876 #define USB_SNP6_V 0x00000001 3877 #define USB_SNP6_S 20 3878 /** USB_STALL6 : R/W; bitpos: [21]; default: 0; 3879 * The application can only set this bit, and the core clears it, when a SETUP token 3880 * is received for this endpoint 3881 * 0x0 (INACTIVE): No Stall 3882 * 0x1 (ACTIVE): Stall Handshake 3883 */ 3884 #define USB_STALL6 (BIT(21)) 3885 #define USB_STALL6_M (USB_STALL6_V << USB_STALL6_S) 3886 #define USB_STALL6_V 0x00000001 3887 #define USB_STALL6_S 21 3888 /** USB_CNAK6 : WO; bitpos: [26]; default: 0; 3889 * 0x0 : No action 3890 * 0x1 : Clear NAK 3891 */ 3892 #define USB_CNAK6 (BIT(26)) 3893 #define USB_CNAK6_M (USB_CNAK6_V << USB_CNAK6_S) 3894 #define USB_CNAK6_V 0x00000001 3895 #define USB_CNAK6_S 26 3896 /** USB_DO_SNAK6 : WO; bitpos: [27]; default: 0; 3897 * A write to this bit sets the NAK bit for the endpoint 3898 * 0x0 : No action 3899 * 0x1 : Set NAK 3900 */ 3901 #define USB_DO_SNAK6 (BIT(27)) 3902 #define USB_DO_SNAK6_M (USB_DO_SNAK6_V << USB_DO_SNAK6_S) 3903 #define USB_DO_SNAK6_V 0x00000001 3904 #define USB_DO_SNAK6_S 27 3905 /** USB_DO_SETD0PID6 : WO; bitpos: [28]; default: 0; 3906 * Set DATA0 PID 3907 */ 3908 #define USB_DO_SETD0PID6 (BIT(28)) 3909 #define USB_DO_SETD0PID6_M (USB_DO_SETD0PID6_V << USB_DO_SETD0PID6_S) 3910 #define USB_DO_SETD0PID6_V 0x00000001 3911 #define USB_DO_SETD0PID6_S 28 3912 /** USB_DO_SETD1PID6 : WO; bitpos: [29]; default: 0; 3913 * Set DATA1 PID 3914 */ 3915 #define USB_DO_SETD1PID6 (BIT(29)) 3916 #define USB_DO_SETD1PID6_M (USB_DO_SETD1PID6_V << USB_DO_SETD1PID6_S) 3917 #define USB_DO_SETD1PID6_V 0x00000001 3918 #define USB_DO_SETD1PID6_S 29 3919 /** USB_EPDIS6 : RO; bitpos: [30]; default: 0; 3920 * Endpoint Disable 3921 * 0x0 : No Endpoint disable 3922 */ 3923 #define USB_EPDIS6 (BIT(30)) 3924 #define USB_EPDIS6_M (USB_EPDIS6_V << USB_EPDIS6_S) 3925 #define USB_EPDIS6_V 0x00000001 3926 #define USB_EPDIS6_S 30 3927 /** USB_EPENA6 : R/W; bitpos: [31]; default: 0; 3928 * Endpoint Enable 3929 * 0x0 : No action 3930 * 0x1 : Enable Endpoint 3931 */ 3932 #define USB_EPENA6 (BIT(31)) 3933 #define USB_EPENA6_M (USB_EPENA6_V << USB_EPENA6_S) 3934 #define USB_EPENA6_V 0x00000001 3935 #define USB_EPENA6_S 31 3936 3937 3938 /** USB_DOEPTSIZ6_REG register 3939 * Device OUT Endpoint 6 Transfer Size Register 3940 */ 3941 #define USB_DOEPTSIZ6_REG (SOC_DPORT_USB_BASE + 0xbd0) 3942 /** USB_XFERSIZE6 : R/W; bitpos: [7:0]; default: 0; 3943 * Transfer Size.Indicates the transfer size in bytes for ENDPOINT6 3944 */ 3945 #define USB_XFERSIZE6 0x0000007F 3946 #define USB_XFERSIZE6_M (USB_XFERSIZE6_V << USB_XFERSIZE6_S) 3947 #define USB_XFERSIZE6_V 0x0000007F 3948 #define USB_XFERSIZE6_S 0 3949 /** USB_PKTCNT6 : R/W; bitpos: [19]; default: 0; 3950 * Packet Count (PktCnt).This field is decremented to zero after a packet is written 3951 * into the RxFIFO. 3952 */ 3953 #define USB_PKTCNT6 (BIT(19)) 3954 #define USB_PKTCNT6_M (USB_PKTCNT6_V << USB_PKTCNT6_S) 3955 #define USB_PKTCNT6_V 0x00000001 3956 #define USB_PKTCNT6_S 19 3957 /** USB_SUPCNT6 : R/W; bitpos: [31:29]; default: 0; 3958 * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP 3959 * data packets the endpoint can receive 3960 * 2'b01: 1 packet 3961 * 2'b10: 2 packets 3962 * 2'b11: 3 packets 3963 */ 3964 #define USB_SUPCNT6 0x00000003 3965 #define USB_SUPCNT6_M (USB_SUPCNT6_V << USB_SUPCNT6_S) 3966 #define USB_SUPCNT6_V 0x00000003 3967 #define USB_SUPCNT6_S 29 3968 3969 3970 /** USB_DOEPDMA6_REG register 3971 * Device OUT Endpoint 6 DMA Address Register 3972 */ 3973 #define USB_DOEPDMA6_REG (SOC_DPORT_USB_BASE + 0xbd4) 3974 /** USB_DMAADDR6 : R/W; bitpos: [32:0]; default: 0; 3975 * Holds the start address of the external memory for storing or fetching endpoint 3976 * data. 3977 */ 3978 #define USB_DMAADDR6 0xFFFFFFFF 3979 #define USB_DMAADDR6_M (USB_DMAADDR6_V << USB_DMAADDR6_S) 3980 #define USB_DMAADDR6_V 0xFFFFFFFF 3981 #define USB_DMAADDR6_S 0 3982 3983 3984 /** USB_DOEPDMAB6_REG register 3985 * Device OUT Endpoint 16 Buffer Address Register 3986 */ 3987 #define USB_DOEPDMAB6_REG (SOC_DPORT_USB_BASE + 0xbdc) 3988 /** USB_DMABUFFERADDR6 : R/W; bitpos: [32:0]; default: 0; 3989 * Holds the current buffer address.This register is updated as and when the data 3990 * transfer for the corresponding end point is in progress. This register is present 3991 * only in Scatter/Gather DMA mode. Otherwise this field is reserved. 3992 */ 3993 #define USB_DMABUFFERADDR6 0xFFFFFFFF 3994 #define USB_DMABUFFERADDR6_M (USB_DMABUFFERADDR6_V << USB_DMABUFFERADDR6_S) 3995 #define USB_DMABUFFERADDR6_V 0xFFFFFFFF 3996 #define USB_DMABUFFERADDR6_S 0 3997 3998 3999 /** USB_PCGCCTL_REG register 4000 * Power and Clock Gating Control Register 4001 */ 4002 #define USB_PCGCCTL_REG (SOC_DPORT_USB_BASE + 0xe00) 4003 /** USB_STOPPCLK : R/W; bitpos: [0]; default: 0; 4004 * 0x0 : Disable Stop Pclk 4005 * 0x1 : Enable Stop Pclk 4006 */ 4007 #define USB_STOPPCLK (BIT(0)) 4008 #define USB_STOPPCLK_M (USB_STOPPCLK_V << USB_STOPPCLK_S) 4009 #define USB_STOPPCLK_V 0x00000001 4010 #define USB_STOPPCLK_S 0 4011 /** USB_GATEHCLK : R/W; bitpos: [1]; default: 0; 4012 * gate hclk 4013 * 0x0:clears this bit when USB is resumed or a new session starts 4014 * 0x1:set this bit to gate hclk to modules, when the USB is suspended or the session 4015 * is not valid 4016 */ 4017 #define USB_GATEHCLK (BIT(1)) 4018 #define USB_GATEHCLK_M (USB_GATEHCLK_V << USB_GATEHCLK_S) 4019 #define USB_GATEHCLK_V 0x00000001 4020 #define USB_GATEHCLK_S 1 4021 /** USB_PWRCLMP : R/W; bitpos: [2]; default: 0; 4022 * 0x0:Clears this bit to disable the clamping before the power is turned on 4023 * 0x1:In only Partial Power-Down mode, sets this bit to clamp the signals between the 4024 * power-on modules and the power-off modules before the power is turned off 4025 */ 4026 #define USB_PWRCLMP (BIT(2)) 4027 #define USB_PWRCLMP_M (USB_PWRCLMP_V << USB_PWRCLMP_S) 4028 #define USB_PWRCLMP_V 0x00000001 4029 #define USB_PWRCLMP_S 2 4030 /** USB_RSTPDWNMODULE : R/W; bitpos: [3]; default: 0; 4031 * Reset Power-Down Modules. 4032 * 0x0 : Power is turned on 4033 * 0x1 : Power is turned off 4034 */ 4035 #define USB_RSTPDWNMODULE (BIT(3)) 4036 #define USB_RSTPDWNMODULE_M (USB_RSTPDWNMODULE_V << USB_RSTPDWNMODULE_S) 4037 #define USB_RSTPDWNMODULE_V 0x00000001 4038 #define USB_RSTPDWNMODULE_S 3 4039 /** USB_PHYSLEEP : RO; bitpos: [6]; default: 0; 4040 * 0x0 : Phy not in Sleep state 4041 * 0x1 : Phy in Sleep state 4042 */ 4043 #define USB_PHYSLEEP (BIT(6)) 4044 #define USB_PHYSLEEP_M (USB_PHYSLEEP_V << USB_PHYSLEEP_S) 4045 #define USB_PHYSLEEP_V 0x00000001 4046 #define USB_PHYSLEEP_S 6 4047 /** USB_L1SUSPENDED : RO; bitpos: [7]; default: 0; 4048 * L1 Deep Sleep 4049 * 0x0 : Non Deep Sleep 4050 * 0x1 : Deep Sleep 4051 */ 4052 #define USB_L1SUSPENDED (BIT(7)) 4053 #define USB_L1SUSPENDED_M (USB_L1SUSPENDED_V << USB_L1SUSPENDED_S) 4054 #define USB_L1SUSPENDED_V 0x00000001 4055 #define USB_L1SUSPENDED_S 7 4056 /** USB_RESETAFTERSUSP : R/W; bitpos: [8]; default: 0; 4057 * Reset after suspend 4058 * 0x0 : In Host-only mode, host issues Resume after Suspend 4059 * 0x1 : In Host-only mode, host sets this bit before clamp is removed if the host 4060 * needs to issue Reset after Suspend 4061 */ 4062 #define USB_RESETAFTERSUSP (BIT(8)) 4063 #define USB_RESETAFTERSUSP_M (USB_RESETAFTERSUSP_V << USB_RESETAFTERSUSP_S) 4064 #define USB_RESETAFTERSUSP_V 0x00000001 4065 #define USB_RESETAFTERSUSP_S 8 4066 4067 4068 4069 4070 /** Interrupt registers */ 4071 /** USB_GOTGINT_REG register 4072 * OTG Interrupt Register 4073 */ 4074 #define USB_GOTGINT_REG (SOC_DPORT_USB_BASE + 0x4) 4075 /** USB_SESENDDET : R/W1C; bitpos: [2]; default: 0; 4076 * Session End Detected.The controller sets this bit when the utmiotg_bvalid signal is 4077 * deasserted. This bit can be set only by the core and the application should write 1 4078 * to clear it 4079 */ 4080 #define USB_SESENDDET (BIT(2)) 4081 #define USB_SESENDDET_M (USB_SESENDDET_V << USB_SESENDDET_S) 4082 #define USB_SESENDDET_V 0x00000001 4083 #define USB_SESENDDET_S 2 4084 /** USB_SESREQSUCSTSCHNG : R/W1C; bitpos: [8]; default: 0; 4085 * Session Request Success Status Change.The core sets this bit on the success or 4086 * failure of a session request.The application must read the Session Request Success 4087 * bit in the OTG Control and Status register (GOTGCTL_REG.USB_SESREQSCS) to check for 4088 * success or failure. This bit can be set only by the core and the application should 4089 * write 1 to clear it. 4090 */ 4091 #define USB_SESREQSUCSTSCHNG (BIT(8)) 4092 #define USB_SESREQSUCSTSCHNG_M (USB_SESREQSUCSTSCHNG_V << USB_SESREQSUCSTSCHNG_S) 4093 #define USB_SESREQSUCSTSCHNG_V 0x00000001 4094 #define USB_SESREQSUCSTSCHNG_S 8 4095 /** USB_HSTNEGSUCSTSCHNG : R/W1C; bitpos: [9]; default: 0; 4096 * Host Negotiation Success Status Change. The core sets this bit on the success or 4097 * failure of a USB host negotiation request. The application must read the Host 4098 * Negotiation Success bit of the OTG Control and Status register 4099 * (GOTGCTL_REG.USB_HSTNEGSCS) to check for success or failure. This bit can be set 4100 * only by the core and the application should write 1 to clear it 4101 */ 4102 #define USB_HSTNEGSUCSTSCHNG (BIT(9)) 4103 #define USB_HSTNEGSUCSTSCHNG_M (USB_HSTNEGSUCSTSCHNG_V << USB_HSTNEGSUCSTSCHNG_S) 4104 #define USB_HSTNEGSUCSTSCHNG_V 0x00000001 4105 #define USB_HSTNEGSUCSTSCHNG_S 9 4106 /** USB_HSTNEGDET : R/W1C; bitpos: [17]; default: 0; 4107 * Host Negotiation Detected.The core sets this bit when it detects a host negotiation 4108 * request on the USB. This bit can be set only by the core and the application should 4109 * write 1 to clear it. 4110 */ 4111 #define USB_HSTNEGDET (BIT(17)) 4112 #define USB_HSTNEGDET_M (USB_HSTNEGDET_V << USB_HSTNEGDET_S) 4113 #define USB_HSTNEGDET_V 0x00000001 4114 #define USB_HSTNEGDET_S 17 4115 /** USB_ADEVTOUTCHG : R/W1C; bitpos: [18]; default: 0; 4116 * A-Device Timeout Change. The core sets this bit to indicate that the A-device has 4117 * timed out while waiting for the B-device to connect.This bit can be set only by the 4118 * core and the application should write 1 to clear it 4119 */ 4120 #define USB_ADEVTOUTCHG (BIT(18)) 4121 #define USB_ADEVTOUTCHG_M (USB_ADEVTOUTCHG_V << USB_ADEVTOUTCHG_S) 4122 #define USB_ADEVTOUTCHG_V 0x00000001 4123 #define USB_ADEVTOUTCHG_S 18 4124 /** USB_DBNCEDONE : R/W1C; bitpos: [19]; default: 0; 4125 * Debounce Done. The core sets this bit when the debounce is completed after the 4126 * device connect. The application can start driving USB reset after seeing this 4127 * interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is SET in 4128 * the Core USB Configuration register (GUSBCFG.HNPCap or GUSBCFG.SRPCap, 4129 * respectively). This bit can be set only by the core and the application should 4130 * write 1 to clear it 4131 */ 4132 #define USB_DBNCEDONE (BIT(19)) 4133 #define USB_DBNCEDONE_M (USB_DBNCEDONE_V << USB_DBNCEDONE_S) 4134 #define USB_DBNCEDONE_V 0x00000001 4135 #define USB_DBNCEDONE_S 19 4136 4137 4138 /** USB_GINTSTS_REG register 4139 * Interrupt Register 4140 */ 4141 #define USB_GINTSTS_REG (SOC_DPORT_USB_BASE + 0x14) 4142 /** USB_CURMOD_INT : RO; bitpos: [0]; default: 0; 4143 * Current Mode of Operation 4144 * 1'b0: Device mode 4145 * 1'b1: Host mode 4146 */ 4147 #define USB_CURMOD_INT (BIT(0)) 4148 #define USB_CURMOD_INT_M (USB_CURMOD_INT_V << USB_CURMOD_INT_S) 4149 #define USB_CURMOD_INT_V 0x00000001 4150 #define USB_CURMOD_INT_S 0 4151 /** USB_MODEMIS : R/W1C; bitpos: [1]; default: 0; 4152 * Mode Mismatch Interrupt.The core sets this bit when the application is trying to 4153 * access:A Host mode register, when the controller is operating in Device mode 4154 */ 4155 #define USB_MODEMIS (BIT(1)) 4156 #define USB_MODEMIS_M (USB_MODEMIS_V << USB_MODEMIS_S) 4157 #define USB_MODEMIS_V 0x00000001 4158 #define USB_MODEMIS_S 1 4159 /** USB_OTGINT : RO; bitpos: [2]; default: 0; 4160 * OTG Interrupt.The controller sets this bit to indicate an OTG protocol event. The 4161 * application must read the OTG Interrupt Status (GOTGINT_REG) register to determine 4162 * the exact event that caused this interrupt. The application must clear the 4163 * appropriate status bit in the GOTGINT_REG register to clear this bit. 4164 */ 4165 #define USB_OTGINT (BIT(2)) 4166 #define USB_OTGINT_M (USB_OTGINT_V << USB_OTGINT_S) 4167 #define USB_OTGINT_V 0x00000001 4168 #define USB_OTGINT_S 2 4169 /** USB_SOF : R/W1C; bitpos: [3]; default: 0; 4170 * Start of (micro)Frame (Sof) 4171 * In Host mode, the core sets this bit to indicate that an SOF (FS), micro-SOF (HS), 4172 * or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to 4173 * this bit to clear the interrupt 4174 * In Device mode, the controller sets this bit to indicate that an SOF token has been 4175 * received on the USB. The application can read the Device Status register to get the 4176 * current (micro)Frame number. This Interrupt is seen only when the core is operating 4177 * at either HS or FS. This bit can be set only by the core and the application must 4178 * write 1 to clear it 4179 */ 4180 #define USB_SOF (BIT(3)) 4181 #define USB_SOF_M (USB_SOF_V << USB_SOF_S) 4182 #define USB_SOF_V 0x00000001 4183 #define USB_SOF_S 3 4184 /** USB_RXFLVI : RO; bitpos: [4]; default: 0; 4185 * RxFIFO Non-Empty.Indicates that there is at least one packet pending to be read 4186 * from the RxFIFO 4187 * 1'b0: Rx Fifo is empty 4188 * 1'b1: Rx Fifo is not empty 4189 */ 4190 #define USB_RXFLVI (BIT(4)) 4191 #define USB_RXFLVI_M (USB_RXFLVI_V << USB_RXFLVI_S) 4192 #define USB_RXFLVI_V 0x00000001 4193 #define USB_RXFLVI_S 4 4194 /** USB_NPTXFEMP : RO; bitpos: [5]; default: 0; 4195 * Non-periodic TxFIFO Empty.This interrupt is asserted when the Non-periodic TxFIFO 4196 * is either half or completely empty, and there is space for at least one Entry to be 4197 * written to the Non-periodic Transmit Request Queue. The half or completely empty 4198 * status is determined by the Non-periodic TxFIFO Empty Level bit in the Core AHB 4199 * Configuration register (GAHBCFG_REG.USB_NPTXFEMPLVL). 4200 */ 4201 #define USB_NPTXFEMP (BIT(5)) 4202 #define USB_NPTXFEMP_M (USB_NPTXFEMP_V << USB_NPTXFEMP_S) 4203 #define USB_NPTXFEMP_V 0x00000001 4204 #define USB_NPTXFEMP_S 5 4205 /** USB_GINNAKEFF : RO; bitpos: [6]; default: 0; 4206 * Device only.Global IN Non-periodic NAK Effective.Indicates that the Set Global 4207 * Non-periodic IN NAK bit in the Device Control register (DCTL.SGNPInNak) set by the 4208 * application, has taken effect in the core. That is, the core has sampled the Global 4209 * IN NAK bit Set by the application. This bit can be cleared by clearing the Clear 4210 * Global Non-periodic IN NAK bit in the Device Control register (DCTL.CGNPInNak). 4211 * This interrupt does not necessarily mean that a NAK handshake is sent out on the 4212 * USB. The STALL bit takes precedence over the NAK bit. 4213 */ 4214 #define USB_GINNAKEFF (BIT(6)) 4215 #define USB_GINNAKEFF_M (USB_GINNAKEFF_V << USB_GINNAKEFF_S) 4216 #define USB_GINNAKEFF_V 0x00000001 4217 #define USB_GINNAKEFF_S 6 4218 /** USB_GOUTNAKEFF : RO; bitpos: [7]; default: 0; 4219 * Device only.Global OUT NAK Effective.Indicates that the Set Global OUT NAK bit in 4220 * the Device Control register (DCTL_REG.USB_SGOUTNAK), Set by the application, has 4221 * taken effect in the core. This bit can be cleared by writing the Clear Global OUT 4222 * NAK bit in the Device Control register (DCTL_REG.REG_CGOUTNAK). 4223 */ 4224 #define USB_GOUTNAKEFF (BIT(7)) 4225 #define USB_GOUTNAKEFF_M (USB_GOUTNAKEFF_V << USB_GOUTNAKEFF_S) 4226 #define USB_GOUTNAKEFF_V 0x00000001 4227 #define USB_GOUTNAKEFF_S 7 4228 /** USB_ERLYSUSP : R/W1C; bitpos: [10]; default: 0; 4229 * Device only.Early Suspend.The controller sets this bit to indicate that an Idle 4230 * state has been detected on the USB for 3 ms. 4231 */ 4232 #define USB_ERLYSUSP (BIT(10)) 4233 #define USB_ERLYSUSP_M (USB_ERLYSUSP_V << USB_ERLYSUSP_S) 4234 #define USB_ERLYSUSP_V 0x00000001 4235 #define USB_ERLYSUSP_S 10 4236 /** USB_USBSUSP : R/W1C; bitpos: [11]; default: 0; 4237 * Device only.USB Suspend.The controller sets this bit to indicate that a suspend was 4238 * detected on the USB. The controller enters the Suspended state when there is no 4239 * activity on the linestate signal for an extended period of time. 4240 */ 4241 #define USB_USBSUSP (BIT(11)) 4242 #define USB_USBSUSP_M (USB_USBSUSP_V << USB_USBSUSP_S) 4243 #define USB_USBSUSP_V 0x00000001 4244 #define USB_USBSUSP_S 11 4245 /** USB_USBRST : R/W1C; bitpos: [12]; default: 0; 4246 * Device only.USB Reset.The controller sets this bit to indicate that a reset is 4247 * detected on the USB 4248 */ 4249 #define USB_USBRST (BIT(12)) 4250 #define USB_USBRST_M (USB_USBRST_V << USB_USBRST_S) 4251 #define USB_USBRST_V 0x00000001 4252 #define USB_USBRST_S 12 4253 /** USB_ENUMDONE : R/W1C; bitpos: [13]; default: 0; 4254 * Device only.Enumeration Done.The core sets this bit to indicate that speed 4255 * enumeration is complete. The application must read the Device Status (DSTS_REG) 4256 * register to obtain the enumerated speed. 4257 */ 4258 #define USB_ENUMDONE (BIT(13)) 4259 #define USB_ENUMDONE_M (USB_ENUMDONE_V << USB_ENUMDONE_S) 4260 #define USB_ENUMDONE_V 0x00000001 4261 #define USB_ENUMDONE_S 13 4262 /** USB_ISOOUTDROP : R/W1C; bitpos: [14]; default: 0; 4263 * Device only.Isochronous OUT Packet Dropped Interrupt.The controller sets this bit 4264 * when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO 4265 * does not have enough space to accommodate a maximum packet size packet for the 4266 * isochronous OUT endpoint. 4267 */ 4268 #define USB_ISOOUTDROP (BIT(14)) 4269 #define USB_ISOOUTDROP_M (USB_ISOOUTDROP_V << USB_ISOOUTDROP_S) 4270 #define USB_ISOOUTDROP_V 0x00000001 4271 #define USB_ISOOUTDROP_S 14 4272 /** USB_EOPF : R/W1C; bitpos: [15]; default: 0; 4273 * Device only.End of Periodic Frame Interrupt.Indicates that the period specified in 4274 * the Periodic Frame Interval field of the Device Configuration register 4275 * (DCFG_REG.REG_PERFRINT) has been reached in the current microframe. 4276 */ 4277 #define USB_EOPF (BIT(15)) 4278 #define USB_EOPF_M (USB_EOPF_V << USB_EOPF_S) 4279 #define USB_EOPF_V 0x00000001 4280 #define USB_EOPF_S 15 4281 /** USB_EPMIS : R/W1C; bitpos: [17]; default: 0; 4282 * Device only.Endpoint Mismatch Interrupt.This interrupt is valid only in shared FIFO 4283 * operation.Indicates that an IN token has been received for a non-periodic endpoint, 4284 * but the data for another endpoint is present in the top of the Non-periodic 4285 * Transmit FIFO and the IN endpoint mismatch count programmed by the application has 4286 * expired. 4287 */ 4288 #define USB_EPMIS (BIT(17)) 4289 #define USB_EPMIS_M (USB_EPMIS_V << USB_EPMIS_S) 4290 #define USB_EPMIS_V 0x00000001 4291 #define USB_EPMIS_S 17 4292 /** USB_IEPINT : RO; bitpos: [18]; default: 0; 4293 * Device only.IN Endpoints Interrupt.The core sets this bit to indicate that an 4294 * interrupt is pending on one of the IN endpoints of the core (in Device mode). The 4295 * application must read the Device All Endpoints Interrupt (DAINT) register to 4296 * determine the exact number of the IN endpoint on Device IN Endpoint-n Interrupt 4297 * (DIEPINTn) register to determine the exact cause of the interrupt. The application 4298 * must clear the appropriate status bit in the corresponding DIEPINTn register to 4299 * clear this bit. 4300 */ 4301 #define USB_IEPINT (BIT(18)) 4302 #define USB_IEPINT_M (USB_IEPINT_V << USB_IEPINT_S) 4303 #define USB_IEPINT_V 0x00000001 4304 #define USB_IEPINT_S 18 4305 /** USB_OEPINT : RO; bitpos: [19]; default: 0; 4306 * Device only.OUT Endpoints Interrupt.The controller sets this bit to indicate that 4307 * an interrupt is pending on one of the OUT endpoints of the core (in Device mode). 4308 * The application must read the Device All Endpoints Interrupt (DAINT) register to 4309 * determine the exact number of the OUT endpoint on which the interrupt occurred, and 4310 * then read the corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) register to 4311 * determine the exact cause of the interrupt. The application must clear the 4312 * appropriate status bit in the corresponding DOEPINTn register to clear this bit. 4313 */ 4314 #define USB_OEPINT (BIT(19)) 4315 #define USB_OEPINT_M (USB_OEPINT_V << USB_OEPINT_S) 4316 #define USB_OEPINT_V 0x00000001 4317 #define USB_OEPINT_S 19 4318 /** USB_INCOMPISOIN : R/W1C; bitpos: [20]; default: 0; 4319 * Device only.Incomplete Isochronous IN Transfer.The core sets this interrupt to 4320 * indicate that there is at least one isochronous IN endpoint on which the transfer 4321 * is not completed in the current microframe. This interrupt is asserted along with 4322 * the End of Periodic Frame Interrupt (EOPF) bit in this register. 4323 */ 4324 #define USB_INCOMPISOIN (BIT(20)) 4325 #define USB_INCOMPISOIN_M (USB_INCOMPISOIN_V << USB_INCOMPISOIN_S) 4326 #define USB_INCOMPISOIN_V 0x00000001 4327 #define USB_INCOMPISOIN_S 20 4328 /** USB_INCOMPIP : R/W1C; bitpos: [21]; default: 0; 4329 * In Host mode, the core sets this interrupt bit when there are incomplete periodic 4330 * transactions still pending which are scheduled for the current microframe.The 4331 * Device mode, the core sets this interrupt to indicate that thereis at least one 4332 * isochronous OUT endpoint on which the transfer is not completed in the current 4333 * microframe. This interrupt is asserted along with the End of Periodic Frame 4334 * Interrupt (EOPF) bit in this register. 4335 */ 4336 #define USB_INCOMPIP (BIT(21)) 4337 #define USB_INCOMPIP_M (USB_INCOMPIP_V << USB_INCOMPIP_S) 4338 #define USB_INCOMPIP_V 0x00000001 4339 #define USB_INCOMPIP_S 21 4340 /** USB_FETSUSP : R/W1C; bitpos: [22]; default: 0; 4341 * Device only.Data Fetch Suspended.This interrupt is valid only in DMA mode. This 4342 * interrupt indicates that the core has stopped fetching data. For IN endpoints due 4343 * to the unavailability of TxFIFO space or Request Queue space. This interrupt is 4344 * used by the application for an endpoint mismatch algorithm 4345 */ 4346 #define USB_FETSUSP (BIT(22)) 4347 #define USB_FETSUSP_M (USB_FETSUSP_V << USB_FETSUSP_S) 4348 #define USB_FETSUSP_V 0x00000001 4349 #define USB_FETSUSP_S 22 4350 /** USB_RESETDET : R/W1C; bitpos: [23]; default: 0; 4351 * Reset detected Interrupt 4352 * In Device mode, this interrupt is asserted when a reset is detected on the USB in 4353 * partial power-down mode when the device is in Suspend 4354 * In Host mode, this interrupt is not asserted 4355 */ 4356 #define USB_RESETDET (BIT(23)) 4357 #define USB_RESETDET_M (USB_RESETDET_V << USB_RESETDET_S) 4358 #define USB_RESETDET_V 0x00000001 4359 #define USB_RESETDET_S 23 4360 /** USB_PRTLNT : RO; bitpos: [24]; default: 0; 4361 * Host only.Host Port Interrupt.The core sets this bit to indicate a change in port 4362 * status of one of the controller ports in Host mode. The application must read the 4363 * Host Port Control and Status (HPRT) register to determine the exact event that 4364 * caused this interrupt. The application must clear the appropriate status bit in the 4365 * Host Port Control and Status register to clear this bit. 4366 */ 4367 #define USB_PRTLNT (BIT(24)) 4368 #define USB_PRTLNT_M (USB_PRTLNT_V << USB_PRTLNT_S) 4369 #define USB_PRTLNT_V 0x00000001 4370 #define USB_PRTLNT_S 24 4371 /** USB_HCHLNT : RO; bitpos: [25]; default: 0; 4372 * Host only.Host Channels Interrupt.The core sets this bit to indicate that an 4373 * interrupt is pending on one of the channels of the core (in Host mode). The 4374 * application must read the Host All Channels Interrupt (HAINT) register to determine 4375 * the exact number of the channel on which the interrupt occurred,and Then read the 4376 * corresponding Host Channel-n Interrupt (HCINTn) register to determine the exact 4377 * cause of the interrupt.The application must clear the appropriate status bit in the 4378 * HCINTn register to clear this bit. 4379 */ 4380 #define USB_HCHLNT (BIT(25)) 4381 #define USB_HCHLNT_M (USB_HCHLNT_V << USB_HCHLNT_S) 4382 #define USB_HCHLNT_V 0x00000001 4383 #define USB_HCHLNT_S 25 4384 /** USB_PTXFEMP : RO; bitpos: [26]; default: 0; 4385 * Host only.Periodic TxFIFO Empty.This interrupt is asserted when the Periodic 4386 * Transmit FIFO is either half or completely empty and there is space for at least 4387 * one entry to be written in the Periodic Request Queue. The half or completelyempty 4388 * status is determined by the Periodic TxFIFO Empty Level bit in the Core AHB 4389 * Configuration register (GAHBCFG.PTxFEmpLvl) 4390 */ 4391 #define USB_PTXFEMP (BIT(26)) 4392 #define USB_PTXFEMP_M (USB_PTXFEMP_V << USB_PTXFEMP_S) 4393 #define USB_PTXFEMP_V 0x00000001 4394 #define USB_PTXFEMP_S 26 4395 /** USB_CONIDSTSCHNG : R/W1C; bitpos: [28]; default: 0; 4396 * Connector ID Status Change 4397 * 1'b0:Not active 4398 * 1'b1:Connector ID Status Change 4399 */ 4400 #define USB_CONIDSTSCHNG (BIT(28)) 4401 #define USB_CONIDSTSCHNG_M (USB_CONIDSTSCHNG_V << USB_CONIDSTSCHNG_S) 4402 #define USB_CONIDSTSCHNG_V 0x00000001 4403 #define USB_CONIDSTSCHNG_S 28 4404 /** USB_DISCONNINT : R/W1C; bitpos: [29]; default: 0; 4405 * Disconnect Detected Interrupt 4406 * 1'b0:Not active 4407 * 1'b1:Disconnect Detected Interrupt 4408 */ 4409 #define USB_DISCONNINT (BIT(29)) 4410 #define USB_DISCONNINT_M (USB_DISCONNINT_V << USB_DISCONNINT_S) 4411 #define USB_DISCONNINT_V 0x00000001 4412 #define USB_DISCONNINT_S 29 4413 /** USB_SESSREQINT : R/W1C; bitpos: [30]; default: 0; 4414 * 1'b0:Not active 4415 * 1'b1:Session Request New Session Detected 4416 */ 4417 #define USB_SESSREQINT (BIT(30)) 4418 #define USB_SESSREQINT_M (USB_SESSREQINT_V << USB_SESSREQINT_S) 4419 #define USB_SESSREQINT_V 0x00000001 4420 #define USB_SESSREQINT_S 30 4421 /** USB_WKUPINT : R/W1C; bitpos: [31]; default: 0; 4422 * Resume/Remote Wakeup Detected Interrupt 4423 * 1'b0:Not active 4424 * 1'b1:Resume or Remote Wakeup Detected Interrupt 4425 */ 4426 #define USB_WKUPINT (BIT(31)) 4427 #define USB_WKUPINT_M (USB_WKUPINT_V << USB_WKUPINT_S) 4428 #define USB_WKUPINT_V 0x00000001 4429 #define USB_WKUPINT_S 31 4430 4431 4432 /** USB_GINTMSK_REG register 4433 * Interrupt Mask Register 4434 */ 4435 #define USB_GINTMSK_REG (SOC_DPORT_USB_BASE + 0x18) 4436 /** USB_MODEMISMSK : R/W; bitpos: [1]; default: 0; 4437 * 1'b0:Mode Mismatch Interrupt Mask 4438 * 1'b1:No Mode Mismatch Interrupt Mask 4439 */ 4440 #define USB_MODEMISMSK (BIT(1)) 4441 #define USB_MODEMISMSK_M (USB_MODEMISMSK_V << USB_MODEMISMSK_S) 4442 #define USB_MODEMISMSK_V 0x00000001 4443 #define USB_MODEMISMSK_S 1 4444 /** USB_OTGINTMSK : R/W; bitpos: [2]; default: 0; 4445 * 1'b0:OTG Interrupt Mask 4446 * 1'b1:No OTG Interrupt Mask 4447 */ 4448 #define USB_OTGINTMSK (BIT(2)) 4449 #define USB_OTGINTMSK_M (USB_OTGINTMSK_V << USB_OTGINTMSK_S) 4450 #define USB_OTGINTMSK_V 0x00000001 4451 #define USB_OTGINTMSK_S 2 4452 /** USB_SOFMSK : R/W; bitpos: [3]; default: 0; 4453 * 1'b0:Start of (micro)Frame Mask 4454 * 1'b1:No Start of (micro)Frame Mask 4455 */ 4456 #define USB_SOFMSK (BIT(3)) 4457 #define USB_SOFMSK_M (USB_SOFMSK_V << USB_SOFMSK_S) 4458 #define USB_SOFMSK_V 0x00000001 4459 #define USB_SOFMSK_S 3 4460 /** USB_RXFLVIMSK : R/W; bitpos: [4]; default: 0; 4461 * 1'b0:Receive FIFO Non-Empty Mask 4462 * 1'b1:No Receive FIFO Non-Empty Mask 4463 */ 4464 #define USB_RXFLVIMSK (BIT(4)) 4465 #define USB_RXFLVIMSK_M (USB_RXFLVIMSK_V << USB_RXFLVIMSK_S) 4466 #define USB_RXFLVIMSK_V 0x00000001 4467 #define USB_RXFLVIMSK_S 4 4468 /** USB_NPTXFEMPMSK : R/W; bitpos: [5]; default: 0; 4469 * 1'b0:Non-periodic TxFIFO Empty Mask 4470 * 1'b1:No Non-periodic TxFIFO Empty Mask 4471 */ 4472 #define USB_NPTXFEMPMSK (BIT(5)) 4473 #define USB_NPTXFEMPMSK_M (USB_NPTXFEMPMSK_V << USB_NPTXFEMPMSK_S) 4474 #define USB_NPTXFEMPMSK_V 0x00000001 4475 #define USB_NPTXFEMPMSK_S 5 4476 /** USB_GINNAKEFFMSK : R/W; bitpos: [6]; default: 0; 4477 * 1'b0:Global Non-periodic IN NAK Effective Mask 4478 * 1'b1:No Global Non-periodic IN NAK Effective Mask 4479 */ 4480 #define USB_GINNAKEFFMSK (BIT(6)) 4481 #define USB_GINNAKEFFMSK_M (USB_GINNAKEFFMSK_V << USB_GINNAKEFFMSK_S) 4482 #define USB_GINNAKEFFMSK_V 0x00000001 4483 #define USB_GINNAKEFFMSK_S 6 4484 /** USB_GOUTNACKEFFMSK : R/W; bitpos: [7]; default: 0; 4485 * 1'b0:Global OUT NAK Effective Mask 4486 * 1'b1:No Global OUT NAK Effective Mask 4487 */ 4488 #define USB_GOUTNACKEFFMSK (BIT(7)) 4489 #define USB_GOUTNACKEFFMSK_M (USB_GOUTNACKEFFMSK_V << USB_GOUTNACKEFFMSK_S) 4490 #define USB_GOUTNACKEFFMSK_V 0x00000001 4491 #define USB_GOUTNACKEFFMSK_S 7 4492 /** USB_ERLYSUSPMSK : R/W; bitpos: [10]; default: 0; 4493 * 1'b0:Early Suspend Mask 4494 * 1'b1:No Early Suspend Mask 4495 */ 4496 #define USB_ERLYSUSPMSK (BIT(10)) 4497 #define USB_ERLYSUSPMSK_M (USB_ERLYSUSPMSK_V << USB_ERLYSUSPMSK_S) 4498 #define USB_ERLYSUSPMSK_V 0x00000001 4499 #define USB_ERLYSUSPMSK_S 10 4500 /** USB_USBSUSPMSK : R/W; bitpos: [11]; default: 0; 4501 * 1'b0:USB Suspend Mask 4502 * 1'b1:No USB Suspend Mask 4503 */ 4504 #define USB_USBSUSPMSK (BIT(11)) 4505 #define USB_USBSUSPMSK_M (USB_USBSUSPMSK_V << USB_USBSUSPMSK_S) 4506 #define USB_USBSUSPMSK_V 0x00000001 4507 #define USB_USBSUSPMSK_S 11 4508 /** USB_USBRSTMSK : R/W; bitpos: [12]; default: 0; 4509 * 1'b0:USB Reset Mask 4510 * 1'b1:No USB Reset Mask 4511 */ 4512 #define USB_USBRSTMSK (BIT(12)) 4513 #define USB_USBRSTMSK_M (USB_USBRSTMSK_V << USB_USBRSTMSK_S) 4514 #define USB_USBRSTMSK_V 0x00000001 4515 #define USB_USBRSTMSK_S 12 4516 /** USB_ENUMDONEMSK : R/W; bitpos: [13]; default: 0; 4517 * 1'b0: Enumeration Done Mask 4518 * 1'b1: No Enumeration Done Mask 4519 */ 4520 #define USB_ENUMDONEMSK (BIT(13)) 4521 #define USB_ENUMDONEMSK_M (USB_ENUMDONEMSK_V << USB_ENUMDONEMSK_S) 4522 #define USB_ENUMDONEMSK_V 0x00000001 4523 #define USB_ENUMDONEMSK_S 13 4524 /** USB_ISOOUTDROPMSK : R/W; bitpos: [14]; default: 0; 4525 * 1'b0: Isochronous OUT Packet Dropped Interrupt Mask 4526 * 1'b1: No Isochronous OUT Packet Dropped Interrupt Mask 4527 */ 4528 #define USB_ISOOUTDROPMSK (BIT(14)) 4529 #define USB_ISOOUTDROPMSK_M (USB_ISOOUTDROPMSK_V << USB_ISOOUTDROPMSK_S) 4530 #define USB_ISOOUTDROPMSK_V 0x00000001 4531 #define USB_ISOOUTDROPMSK_S 14 4532 /** USB_EOPFMSK : R/W; bitpos: [15]; default: 0; 4533 * 1'b0: End of Periodic Frame Interrupt Mask 4534 * 1'b1: No End of Periodic Frame Interrupt Mask 4535 */ 4536 #define USB_EOPFMSK (BIT(15)) 4537 #define USB_EOPFMSK_M (USB_EOPFMSK_V << USB_EOPFMSK_S) 4538 #define USB_EOPFMSK_V 0x00000001 4539 #define USB_EOPFMSK_S 15 4540 /** USB_EPMISMSK : R/W; bitpos: [17]; default: 0; 4541 * 1'b0: Endpoint Mismatch Interrupt Mask 4542 * 1'b1: No Endpoint Mismatch Interrupt Mask 4543 */ 4544 #define USB_EPMISMSK (BIT(17)) 4545 #define USB_EPMISMSK_M (USB_EPMISMSK_V << USB_EPMISMSK_S) 4546 #define USB_EPMISMSK_V 0x00000001 4547 #define USB_EPMISMSK_S 17 4548 /** USB_IEPINTMSK : R/W; bitpos: [18]; default: 0; 4549 * 1'b0: IN Endpoints Interrupt Mask 4550 * 1'b1: No IN Endpoints Interrupt Mask 4551 */ 4552 #define USB_IEPINTMSK (BIT(18)) 4553 #define USB_IEPINTMSK_M (USB_IEPINTMSK_V << USB_IEPINTMSK_S) 4554 #define USB_IEPINTMSK_V 0x00000001 4555 #define USB_IEPINTMSK_S 18 4556 /** USB_OEPINTMSK : R/W; bitpos: [19]; default: 0; 4557 * 1'b0: OUT Endpoints Interrupt Mask 4558 * 1'b1: No OUT Endpoints Interrupt Mask 4559 */ 4560 #define USB_OEPINTMSK (BIT(19)) 4561 #define USB_OEPINTMSK_M (USB_OEPINTMSK_V << USB_OEPINTMSK_S) 4562 #define USB_OEPINTMSK_V 0x00000001 4563 #define USB_OEPINTMSK_S 19 4564 /** USB_INCOMPISOINMSK : R/W; bitpos: [20]; default: 0; 4565 * 1'b0: Incomplete Isochronous IN Transfer Mask 4566 * 1'b1: No Incomplete Isochronous IN Transfer Mask 4567 */ 4568 #define USB_INCOMPISOINMSK (BIT(20)) 4569 #define USB_INCOMPISOINMSK_M (USB_INCOMPISOINMSK_V << USB_INCOMPISOINMSK_S) 4570 #define USB_INCOMPISOINMSK_V 0x00000001 4571 #define USB_INCOMPISOINMSK_S 20 4572 /** USB_INCOMPIPMSK : R/W; bitpos: [21]; default: 0; 4573 * 1'b0: Host mode: Incomplete Periodic Transfer Mask Device mode: Incomplete 4574 * Isochronous OUT Transfer Mask 4575 * 1'b1: Host mode: No Incomplete Periodic Transfer Mask Device mode: No Incomplete 4576 * Isochronous OUT Transfer Mask 4577 */ 4578 #define USB_INCOMPIPMSK (BIT(21)) 4579 #define USB_INCOMPIPMSK_M (USB_INCOMPIPMSK_V << USB_INCOMPIPMSK_S) 4580 #define USB_INCOMPIPMSK_V 0x00000001 4581 #define USB_INCOMPIPMSK_S 21 4582 /** USB_FETSUSPMSK : R/W; bitpos: [22]; default: 0; 4583 * 1'b0: Data Fetch Suspended Mask 4584 * 1'b1: No Data Fetch Suspended Mask 4585 */ 4586 #define USB_FETSUSPMSK (BIT(22)) 4587 #define USB_FETSUSPMSK_M (USB_FETSUSPMSK_V << USB_FETSUSPMSK_S) 4588 #define USB_FETSUSPMSK_V 0x00000001 4589 #define USB_FETSUSPMSK_S 22 4590 /** USB_RESETDETMSK : R/W; bitpos: [23]; default: 0; 4591 * 1'b0: Reset detected Interrupt Mask 4592 * 1'b1: No Reset detected Interrupt Mask 4593 */ 4594 #define USB_RESETDETMSK (BIT(23)) 4595 #define USB_RESETDETMSK_M (USB_RESETDETMSK_V << USB_RESETDETMSK_S) 4596 #define USB_RESETDETMSK_V 0x00000001 4597 #define USB_RESETDETMSK_S 23 4598 /** USB_PRTLNTMSK : R/W; bitpos: [24]; default: 0; 4599 * 1'b0: Host Port Interrupt Mask 4600 * 1'b1: No Host Port Interrupt Mask 4601 */ 4602 #define USB_PRTLNTMSK (BIT(24)) 4603 #define USB_PRTLNTMSK_M (USB_PRTLNTMSK_V << USB_PRTLNTMSK_S) 4604 #define USB_PRTLNTMSK_V 0x00000001 4605 #define USB_PRTLNTMSK_S 24 4606 /** USB_HCHINTMSK : R/W; bitpos: [25]; default: 0; 4607 * 1'b0: Host Channels Interrupt Mask 4608 * 1'b1: No Host Channels Interrupt Mask 4609 */ 4610 #define USB_HCHINTMSK (BIT(25)) 4611 #define USB_HCHINTMSK_M (USB_HCHINTMSK_V << USB_HCHINTMSK_S) 4612 #define USB_HCHINTMSK_V 0x00000001 4613 #define USB_HCHINTMSK_S 25 4614 /** USB_PTXFEMPMSK : R/W; bitpos: [26]; default: 0; 4615 * 1'b0: Periodic TxFIFO Empty Mask 4616 * 1'b1: No Periodic TxFIFO Empty Mask 4617 */ 4618 #define USB_PTXFEMPMSK (BIT(26)) 4619 #define USB_PTXFEMPMSK_M (USB_PTXFEMPMSK_V << USB_PTXFEMPMSK_S) 4620 #define USB_PTXFEMPMSK_V 0x00000001 4621 #define USB_PTXFEMPMSK_S 26 4622 /** USB_CONIDSTSCHNGMSK : R/W; bitpos: [28]; default: 0; 4623 * 1'b0: Connector ID Status Change Mask 4624 * 1'b1: No Connector ID Status Change Mask 4625 */ 4626 #define USB_CONIDSTSCHNGMSK (BIT(28)) 4627 #define USB_CONIDSTSCHNGMSK_M (USB_CONIDSTSCHNGMSK_V << USB_CONIDSTSCHNGMSK_S) 4628 #define USB_CONIDSTSCHNGMSK_V 0x00000001 4629 #define USB_CONIDSTSCHNGMSK_S 28 4630 /** USB_DISCONNINTMSK : R/W; bitpos: [29]; default: 0; 4631 * 1'b0: Disconnect Detected Interrupt Mask 4632 * 1'b1: No Disconnect Detected Interrupt Mask 4633 */ 4634 #define USB_DISCONNINTMSK (BIT(29)) 4635 #define USB_DISCONNINTMSK_M (USB_DISCONNINTMSK_V << USB_DISCONNINTMSK_S) 4636 #define USB_DISCONNINTMSK_V 0x00000001 4637 #define USB_DISCONNINTMSK_S 29 4638 /** USB_SESSREQINTMSK : R/W; bitpos: [30]; default: 0; 4639 * 1'b0: Session Request or New Session Detected Interrupt Mask 4640 * 1'b1: No Session Request or New Session Detected Interrupt Mask 4641 */ 4642 #define USB_SESSREQINTMSK (BIT(30)) 4643 #define USB_SESSREQINTMSK_M (USB_SESSREQINTMSK_V << USB_SESSREQINTMSK_S) 4644 #define USB_SESSREQINTMSK_V 0x00000001 4645 #define USB_SESSREQINTMSK_S 30 4646 /** USB_WKUPINTMSK : R/W; bitpos: [31]; default: 0; 4647 * 1'b0 : Resume or Remote Wakeup Detected Interrupt Mask 4648 * 1'b1 : Unmask Resume Remote Wakeup Detected Interrupt 4649 */ 4650 #define USB_WKUPINTMSK (BIT(31)) 4651 #define USB_WKUPINTMSK_M (USB_WKUPINTMSK_V << USB_WKUPINTMSK_S) 4652 #define USB_WKUPINTMSK_V 0x00000001 4653 #define USB_WKUPINTMSK_S 31 4654 4655 4656 /** USB_HAINT_REG register 4657 * Host All Channels Interrupt Register 4658 */ 4659 #define USB_HAINT_REG (SOC_DPORT_USB_BASE + 0x414) 4660 /** USB_HAINT : RO; bitpos: [8:0]; default: 0; 4661 * Channel Interrupt for channel no. 4662 */ 4663 #define USB_HAINT 0x000000FF 4664 #define USB_HAINT_M (USB_HAINT_V << USB_HAINT_S) 4665 #define USB_HAINT_V 0x000000FF 4666 #define USB_HAINT_S 0 4667 4668 4669 /** USB_HAINTMSK_REG register 4670 * Host All Channels Interrupt Mask Register 4671 */ 4672 #define USB_HAINTMSK_REG (SOC_DPORT_USB_BASE + 0x418) 4673 /** USB_HAINTMSK : R/W; bitpos: [8:0]; default: 0; 4674 * Channel Interrupt Mask (HAINTMSK_REG) One bit per channel: Bit 0 for channel 0, bit 4675 * 15 for channel 15. 4676 */ 4677 #define USB_HAINTMSK 0x000000FF 4678 #define USB_HAINTMSK_M (USB_HAINTMSK_V << USB_HAINTMSK_S) 4679 #define USB_HAINTMSK_V 0x000000FF 4680 #define USB_HAINTMSK_S 0 4681 4682 4683 /** USB_HCINT0_REG register 4684 * Host Channel 0 Interrupt Register 4685 */ 4686 #define USB_HCINT0_REG (SOC_DPORT_USB_BASE + 0x508) 4687 /** USB_H_XFERCOMPL0 : R/W1C; bitpos: [0]; default: 0; 4688 * 1'b0: Transfer in progress or No Active Transfer 4689 * 1'b1: Transfer completed normally without any errors 4690 */ 4691 #define USB_H_XFERCOMPL0 (BIT(0)) 4692 #define USB_H_XFERCOMPL0_M (USB_H_XFERCOMPL0_V << USB_H_XFERCOMPL0_S) 4693 #define USB_H_XFERCOMPL0_V 0x00000001 4694 #define USB_H_XFERCOMPL0_S 0 4695 /** USB_H_CHHLTD0 : R/W1C; bitpos: [1]; default: 0; 4696 * 1'b0: Channel not halted 4697 * 1'b1: Channel Halted 4698 */ 4699 #define USB_H_CHHLTD0 (BIT(1)) 4700 #define USB_H_CHHLTD0_M (USB_H_CHHLTD0_V << USB_H_CHHLTD0_S) 4701 #define USB_H_CHHLTD0_V 0x00000001 4702 #define USB_H_CHHLTD0_S 1 4703 /** USB_H_AHBERR0 : R/W1C; bitpos: [2]; default: 0; 4704 * 1'b0: No AHB error 4705 * 1'b1: AHB error during AHB read/write 4706 */ 4707 #define USB_H_AHBERR0 (BIT(2)) 4708 #define USB_H_AHBERR0_M (USB_H_AHBERR0_V << USB_H_AHBERR0_S) 4709 #define USB_H_AHBERR0_V 0x00000001 4710 #define USB_H_AHBERR0_S 2 4711 /** USB_H_STALL0 : R/W1C; bitpos: [3]; default: 0; 4712 * 1'b0: No Stall Response Received Interrupt 4713 * 1'b1: Stall Response Received Interrupt 4714 */ 4715 #define USB_H_STALL0 (BIT(3)) 4716 #define USB_H_STALL0_M (USB_H_STALL0_V << USB_H_STALL0_S) 4717 #define USB_H_STALL0_V 0x00000001 4718 #define USB_H_STALL0_S 3 4719 /** USB_H_NACK0 : R/W1C; bitpos: [4]; default: 0; 4720 * 1'b0: No NAK Response Received Interrupt 4721 * 1'b1: NAK Response Received Interrupt 4722 */ 4723 #define USB_H_NACK0 (BIT(4)) 4724 #define USB_H_NACK0_M (USB_H_NACK0_V << USB_H_NACK0_S) 4725 #define USB_H_NACK0_V 0x00000001 4726 #define USB_H_NACK0_S 4 4727 /** USB_H_ACK0 : R/W1C; bitpos: [5]; default: 0; 4728 * 1'b0: No ACK Response Received or Transmitted Interrupt 4729 * 1'b1: ACK Response Received or Transmitted Interrup 4730 */ 4731 #define USB_H_ACK0 (BIT(5)) 4732 #define USB_H_ACK0_M (USB_H_ACK0_V << USB_H_ACK0_S) 4733 #define USB_H_ACK0_V 0x00000001 4734 #define USB_H_ACK0_S 5 4735 /** USB_H_NYET0 : R/W1C; bitpos: [6]; default: 0; 4736 * 1'b0: No NYET Response Received Interrupt 4737 * 1'b1: NYET Response Received Interrupt 4738 */ 4739 #define USB_H_NYET0 (BIT(6)) 4740 #define USB_H_NYET0_M (USB_H_NYET0_V << USB_H_NYET0_S) 4741 #define USB_H_NYET0_V 0x00000001 4742 #define USB_H_NYET0_S 6 4743 /** USB_H_XACTERR0 : R/W1C; bitpos: [7]; default: 0; 4744 * Indicates one of the following errors occurred on the USB: 4745 * CRC check failure 4746 * Timeout 4747 * Bit stuff error 4748 * False EOP 4749 */ 4750 #define USB_H_XACTERR0 (BIT(7)) 4751 #define USB_H_XACTERR0_M (USB_H_XACTERR0_V << USB_H_XACTERR0_S) 4752 #define USB_H_XACTERR0_V 0x00000001 4753 #define USB_H_XACTERR0_S 7 4754 /** USB_H_BBLERR0 : R/W1C; bitpos: [8]; default: 0; 4755 * 1'b0: No Babble Error 4756 * 1'b1: Babble Error 4757 */ 4758 #define USB_H_BBLERR0 (BIT(8)) 4759 #define USB_H_BBLERR0_M (USB_H_BBLERR0_V << USB_H_BBLERR0_S) 4760 #define USB_H_BBLERR0_V 0x00000001 4761 #define USB_H_BBLERR0_S 8 4762 /** USB_H_FRMOVRUN0 : R/W1C; bitpos: [9]; default: 0; 4763 * 1'b0: No Frame Overrun 4764 * 1'b1: Frame Overrun 4765 */ 4766 #define USB_H_FRMOVRUN0 (BIT(9)) 4767 #define USB_H_FRMOVRUN0_M (USB_H_FRMOVRUN0_V << USB_H_FRMOVRUN0_S) 4768 #define USB_H_FRMOVRUN0_V 0x00000001 4769 #define USB_H_FRMOVRUN0_S 9 4770 /** USB_H_DATATGLERR0 : R/W1C; bitpos: [10]; default: 0; 4771 * 1'b0: No Data Toggle Error 4772 * 1'b1: Data Toggle Error 4773 */ 4774 #define USB_H_DATATGLERR0 (BIT(10)) 4775 #define USB_H_DATATGLERR0_M (USB_H_DATATGLERR0_V << USB_H_DATATGLERR0_S) 4776 #define USB_H_DATATGLERR0_V 0x00000001 4777 #define USB_H_DATATGLERR0_S 10 4778 /** USB_H_BNAINTR0 : R/W1C; bitpos: [11]; default: 0; 4779 * 1'b0: No BNA Interrupt 4780 * 1'b1: BNA Interrupt 4781 */ 4782 #define USB_H_BNAINTR0 (BIT(11)) 4783 #define USB_H_BNAINTR0_M (USB_H_BNAINTR0_V << USB_H_BNAINTR0_S) 4784 #define USB_H_BNAINTR0_V 0x00000001 4785 #define USB_H_BNAINTR0_S 11 4786 /** USB_H_XCS_XACT_ERR0 : R/W1C; bitpos: [12]; default: 0; 4787 * 1'b0: No Excessive Transaction Error 4788 * 1'b1: Excessive Transaction Error 4789 */ 4790 #define USB_H_XCS_XACT_ERR0 (BIT(12)) 4791 #define USB_H_XCS_XACT_ERR0_M (USB_H_XCS_XACT_ERR0_V << USB_H_XCS_XACT_ERR0_S) 4792 #define USB_H_XCS_XACT_ERR0_V 0x00000001 4793 #define USB_H_XCS_XACT_ERR0_S 12 4794 /** USB_H_DESC_LST_ROLLINTR0 : R/W1C; bitpos: [13]; default: 0; 4795 * 1'b0: No Descriptor rollover interrupt 4796 * 1'b1: Descriptor rollover interrupt 4797 */ 4798 #define USB_H_DESC_LST_ROLLINTR0 (BIT(13)) 4799 #define USB_H_DESC_LST_ROLLINTR0_M (USB_H_DESC_LST_ROLLINTR0_V << USB_H_DESC_LST_ROLLINTR0_S) 4800 #define USB_H_DESC_LST_ROLLINTR0_V 0x00000001 4801 #define USB_H_DESC_LST_ROLLINTR0_S 13 4802 4803 4804 /** USB_HCINTMSK0_REG register 4805 * Host Channel 0 Interrupt Mask Register 4806 */ 4807 #define USB_HCINTMSK0_REG (SOC_DPORT_USB_BASE + 0x50c) 4808 /** USB_H_XFERCOMPLMSK0 : R/W; bitpos: [0]; default: 0; 4809 * 1'b0: Transfer Completed Mask 4810 * 1'b1: No Transfer Completed Mask 4811 */ 4812 #define USB_H_XFERCOMPLMSK0 (BIT(0)) 4813 #define USB_H_XFERCOMPLMSK0_M (USB_H_XFERCOMPLMSK0_V << USB_H_XFERCOMPLMSK0_S) 4814 #define USB_H_XFERCOMPLMSK0_V 0x00000001 4815 #define USB_H_XFERCOMPLMSK0_S 0 4816 /** USB_H_CHHLTDMSK0 : R/W; bitpos: [1]; default: 0; 4817 * 1'b0: Channel Halted Mask 4818 * 1'b1: No Channel Halted Mask 4819 */ 4820 #define USB_H_CHHLTDMSK0 (BIT(1)) 4821 #define USB_H_CHHLTDMSK0_M (USB_H_CHHLTDMSK0_V << USB_H_CHHLTDMSK0_S) 4822 #define USB_H_CHHLTDMSK0_V 0x00000001 4823 #define USB_H_CHHLTDMSK0_S 1 4824 /** USB_H_AHBERRMSK0 : R/W; bitpos: [2]; default: 0; 4825 * 1'b0: AHB Error Mask 4826 * 1'b1: No AHB Error Mask 4827 */ 4828 #define USB_H_AHBERRMSK0 (BIT(2)) 4829 #define USB_H_AHBERRMSK0_M (USB_H_AHBERRMSK0_V << USB_H_AHBERRMSK0_S) 4830 #define USB_H_AHBERRMSK0_V 0x00000001 4831 #define USB_H_AHBERRMSK0_S 2 4832 /** USB_H_STALLMSK0 : R/W; bitpos: [3]; default: 0; 4833 * 1'b0: Mask STALL Response Received Interrupt 4834 * 1'b1: No STALL Response Received Interrupt Mask 4835 */ 4836 #define USB_H_STALLMSK0 (BIT(3)) 4837 #define USB_H_STALLMSK0_M (USB_H_STALLMSK0_V << USB_H_STALLMSK0_S) 4838 #define USB_H_STALLMSK0_V 0x00000001 4839 #define USB_H_STALLMSK0_S 3 4840 /** USB_H_NAKMSK0 : R/W; bitpos: [4]; default: 0; 4841 * 1'b0: Mask NAK Response Received Interrupt 4842 * 1'b1: No NAK Response Received Interrupt Mask 4843 */ 4844 #define USB_H_NAKMSK0 (BIT(4)) 4845 #define USB_H_NAKMSK0_M (USB_H_NAKMSK0_V << USB_H_NAKMSK0_S) 4846 #define USB_H_NAKMSK0_V 0x00000001 4847 #define USB_H_NAKMSK0_S 4 4848 /** USB_H_ACKMSK0 : R/W; bitpos: [5]; default: 0; 4849 * 1'b0: Mask ACK Response Received/Transmitted Interrupt 4850 * 1'b1: No ACK Response Received/Transmitted Interrupt Mask 4851 */ 4852 #define USB_H_ACKMSK0 (BIT(5)) 4853 #define USB_H_ACKMSK0_M (USB_H_ACKMSK0_V << USB_H_ACKMSK0_S) 4854 #define USB_H_ACKMSK0_V 0x00000001 4855 #define USB_H_ACKMSK0_S 5 4856 /** USB_H_NYETMSK0 : R/W; bitpos: [6]; default: 0; 4857 * 1'b0: Mask NYET Response Received Interrupt 4858 * 1'b1: No NYET Response Received Interrupt Mask 4859 */ 4860 #define USB_H_NYETMSK0 (BIT(6)) 4861 #define USB_H_NYETMSK0_M (USB_H_NYETMSK0_V << USB_H_NYETMSK0_S) 4862 #define USB_H_NYETMSK0_V 0x00000001 4863 #define USB_H_NYETMSK0_S 6 4864 /** USB_H_XACTERRMSK0 : R/W; bitpos: [7]; default: 0; 4865 * 1'b0: Mask Transaction Error 4866 * 1'b1: No Transaction Error Mask 4867 */ 4868 #define USB_H_XACTERRMSK0 (BIT(7)) 4869 #define USB_H_XACTERRMSK0_M (USB_H_XACTERRMSK0_V << USB_H_XACTERRMSK0_S) 4870 #define USB_H_XACTERRMSK0_V 0x00000001 4871 #define USB_H_XACTERRMSK0_S 7 4872 /** USB_H_BBLERRMSK0 : R/W; bitpos: [8]; default: 0; 4873 * Babble Error Mask 4874 * 1'b0: Mask Babble Error 4875 * 1'b1: No Babble Error Mask 4876 */ 4877 #define USB_H_BBLERRMSK0 (BIT(8)) 4878 #define USB_H_BBLERRMSK0_M (USB_H_BBLERRMSK0_V << USB_H_BBLERRMSK0_S) 4879 #define USB_H_BBLERRMSK0_V 0x00000001 4880 #define USB_H_BBLERRMSK0_S 8 4881 /** USB_H_FRMOVRUNMSK0 : R/W; bitpos: [9]; default: 0; 4882 * Frame Overrun Mask 4883 * 0x0 (MASK): Mask Overrun Mask 4884 * 0x1 (NOMASK): No Frame Overrun Mask 4885 */ 4886 #define USB_H_FRMOVRUNMSK0 (BIT(9)) 4887 #define USB_H_FRMOVRUNMSK0_M (USB_H_FRMOVRUNMSK0_V << USB_H_FRMOVRUNMSK0_S) 4888 #define USB_H_FRMOVRUNMSK0_V 0x00000001 4889 #define USB_H_FRMOVRUNMSK0_S 9 4890 /** USB_H_DATATGLERRMSK0 : R/W; bitpos: [10]; default: 0; 4891 * Data Toggle Error Mask n scatter/gather DMA mode for host 4892 * 1'b0: Mask Data Toggle Error 4893 * 1'b1: No Data Toggle Error Mask 4894 */ 4895 #define USB_H_DATATGLERRMSK0 (BIT(10)) 4896 #define USB_H_DATATGLERRMSK0_M (USB_H_DATATGLERRMSK0_V << USB_H_DATATGLERRMSK0_S) 4897 #define USB_H_DATATGLERRMSK0_V 0x00000001 4898 #define USB_H_DATATGLERRMSK0_S 10 4899 /** USB_H_BNAINTRMSK0 : R/W; bitpos: [11]; default: 0; 4900 * BNA (Buffer Not Available) Interrupt mask register 4901 * 1'b0: BNA Interrupt Masked 4902 * 1'b1: BNA Interrupt not masked 4903 */ 4904 #define USB_H_BNAINTRMSK0 (BIT(11)) 4905 #define USB_H_BNAINTRMSK0_M (USB_H_BNAINTRMSK0_V << USB_H_BNAINTRMSK0_S) 4906 #define USB_H_BNAINTRMSK0_V 0x00000001 4907 #define USB_H_BNAINTRMSK0_S 11 4908 /** USB_H_DESC_LST_ROLLINTRMSK0 : R/W; bitpos: [13]; default: 0; 4909 * Descriptor List rollover interrupt Mask 4910 * 1'b0: Descriptor Rollover Interrupt Mask 4911 * 1'b1: Descriptor Rollover Interrupt not masked 4912 */ 4913 #define USB_H_DESC_LST_ROLLINTRMSK0 (BIT(13)) 4914 #define USB_H_DESC_LST_ROLLINTRMSK0_M (USB_H_DESC_LST_ROLLINTRMSK0_V << USB_H_DESC_LST_ROLLINTRMSK0_S) 4915 #define USB_H_DESC_LST_ROLLINTRMSK0_V 0x00000001 4916 #define USB_H_DESC_LST_ROLLINTRMSK0_S 13 4917 4918 4919 /** USB_HCINT1_REG register 4920 * Host Channel 1 Interrupt Register 4921 */ 4922 #define USB_HCINT1_REG (SOC_DPORT_USB_BASE + 0x528) 4923 /** USB_H_XFERCOMPL1 : R/W1C; bitpos: [0]; default: 0; 4924 * 1'b0: Transfer in progress or No Active Transfer 4925 * 1'b1: Transfer completed normally without any errors 4926 */ 4927 #define USB_H_XFERCOMPL1 (BIT(0)) 4928 #define USB_H_XFERCOMPL1_M (USB_H_XFERCOMPL1_V << USB_H_XFERCOMPL1_S) 4929 #define USB_H_XFERCOMPL1_V 0x00000001 4930 #define USB_H_XFERCOMPL1_S 0 4931 /** USB_H_CHHLTD1 : R/W1C; bitpos: [1]; default: 0; 4932 * 1'b0: Channel not halted 4933 * 1'b1: Channel Halted 4934 */ 4935 #define USB_H_CHHLTD1 (BIT(1)) 4936 #define USB_H_CHHLTD1_M (USB_H_CHHLTD1_V << USB_H_CHHLTD1_S) 4937 #define USB_H_CHHLTD1_V 0x00000001 4938 #define USB_H_CHHLTD1_S 1 4939 /** USB_H_AHBERR1 : R/W1C; bitpos: [2]; default: 0; 4940 * 1'b0: No AHB error 4941 * 1'b1: AHB error during AHB read/write 4942 */ 4943 #define USB_H_AHBERR1 (BIT(2)) 4944 #define USB_H_AHBERR1_M (USB_H_AHBERR1_V << USB_H_AHBERR1_S) 4945 #define USB_H_AHBERR1_V 0x00000001 4946 #define USB_H_AHBERR1_S 2 4947 /** USB_H_STALL1 : R/W1C; bitpos: [3]; default: 0; 4948 * 1'b0: No Stall Response Received Interrupt 4949 * 1'b1: Stall Response Received Interrupt 4950 */ 4951 #define USB_H_STALL1 (BIT(3)) 4952 #define USB_H_STALL1_M (USB_H_STALL1_V << USB_H_STALL1_S) 4953 #define USB_H_STALL1_V 0x00000001 4954 #define USB_H_STALL1_S 3 4955 /** USB_H_NACK1 : R/W1C; bitpos: [4]; default: 0; 4956 * 1'b0: No NAK Response Received Interrupt 4957 * 1'b1: NAK Response Received Interrupt 4958 */ 4959 #define USB_H_NACK1 (BIT(4)) 4960 #define USB_H_NACK1_M (USB_H_NACK1_V << USB_H_NACK1_S) 4961 #define USB_H_NACK1_V 0x00000001 4962 #define USB_H_NACK1_S 4 4963 /** USB_H_ACK1 : R/W1C; bitpos: [5]; default: 0; 4964 * 1'b0: No ACK Response Received or Transmitted Interrupt 4965 * 1'b1: ACK Response Received or Transmitted Interrup 4966 */ 4967 #define USB_H_ACK1 (BIT(5)) 4968 #define USB_H_ACK1_M (USB_H_ACK1_V << USB_H_ACK1_S) 4969 #define USB_H_ACK1_V 0x00000001 4970 #define USB_H_ACK1_S 5 4971 /** USB_H_NYET1 : R/W1C; bitpos: [6]; default: 0; 4972 * 1'b0: No NYET Response Received Interrupt 4973 * 1'b1: NYET Response Received Interrupt 4974 */ 4975 #define USB_H_NYET1 (BIT(6)) 4976 #define USB_H_NYET1_M (USB_H_NYET1_V << USB_H_NYET1_S) 4977 #define USB_H_NYET1_V 0x00000001 4978 #define USB_H_NYET1_S 6 4979 /** USB_H_XACTERR1 : R/W1C; bitpos: [7]; default: 0; 4980 * Indicates one of the following errors occurred on the USB: 4981 * CRC check failure 4982 * Timeout 4983 * Bit stuff error 4984 * False EOP 4985 */ 4986 #define USB_H_XACTERR1 (BIT(7)) 4987 #define USB_H_XACTERR1_M (USB_H_XACTERR1_V << USB_H_XACTERR1_S) 4988 #define USB_H_XACTERR1_V 0x00000001 4989 #define USB_H_XACTERR1_S 7 4990 /** USB_H_BBLERR1 : R/W1C; bitpos: [8]; default: 0; 4991 * 1'b0: No Babble Error 4992 * 1'b1: Babble Error 4993 */ 4994 #define USB_H_BBLERR1 (BIT(8)) 4995 #define USB_H_BBLERR1_M (USB_H_BBLERR1_V << USB_H_BBLERR1_S) 4996 #define USB_H_BBLERR1_V 0x00000001 4997 #define USB_H_BBLERR1_S 8 4998 /** USB_H_FRMOVRUN1 : R/W1C; bitpos: [9]; default: 0; 4999 * 1'b0: No Frame Overrun 5000 * 1'b1: Frame Overrun 5001 */ 5002 #define USB_H_FRMOVRUN1 (BIT(9)) 5003 #define USB_H_FRMOVRUN1_M (USB_H_FRMOVRUN1_V << USB_H_FRMOVRUN1_S) 5004 #define USB_H_FRMOVRUN1_V 0x00000001 5005 #define USB_H_FRMOVRUN1_S 9 5006 /** USB_H_DATATGLERR1 : R/W1C; bitpos: [10]; default: 0; 5007 * 1'b0: No Data Toggle Error 5008 * 1'b1: Data Toggle Error 5009 */ 5010 #define USB_H_DATATGLERR1 (BIT(10)) 5011 #define USB_H_DATATGLERR1_M (USB_H_DATATGLERR1_V << USB_H_DATATGLERR1_S) 5012 #define USB_H_DATATGLERR1_V 0x00000001 5013 #define USB_H_DATATGLERR1_S 10 5014 /** USB_H_BNAINTR1 : R/W1C; bitpos: [11]; default: 0; 5015 * 1'b0: No BNA Interrupt 5016 * 1'b1: BNA Interrupt 5017 */ 5018 #define USB_H_BNAINTR1 (BIT(11)) 5019 #define USB_H_BNAINTR1_M (USB_H_BNAINTR1_V << USB_H_BNAINTR1_S) 5020 #define USB_H_BNAINTR1_V 0x00000001 5021 #define USB_H_BNAINTR1_S 11 5022 /** USB_H_XCS_XACT_ERR1 : R/W1C; bitpos: [12]; default: 0; 5023 * 1'b0: No Excessive Transaction Error 5024 * 1'b1: Excessive Transaction Error 5025 */ 5026 #define USB_H_XCS_XACT_ERR1 (BIT(12)) 5027 #define USB_H_XCS_XACT_ERR1_M (USB_H_XCS_XACT_ERR1_V << USB_H_XCS_XACT_ERR1_S) 5028 #define USB_H_XCS_XACT_ERR1_V 0x00000001 5029 #define USB_H_XCS_XACT_ERR1_S 12 5030 /** USB_H_DESC_LST_ROLLINTR1 : R/W1C; bitpos: [13]; default: 0; 5031 * 1'b0: No Descriptor rollover interrupt 5032 * 1'b1: Descriptor rollover interrupt 5033 */ 5034 #define USB_H_DESC_LST_ROLLINTR1 (BIT(13)) 5035 #define USB_H_DESC_LST_ROLLINTR1_M (USB_H_DESC_LST_ROLLINTR1_V << USB_H_DESC_LST_ROLLINTR1_S) 5036 #define USB_H_DESC_LST_ROLLINTR1_V 0x00000001 5037 #define USB_H_DESC_LST_ROLLINTR1_S 13 5038 5039 5040 /** USB_HCINTMSK1_REG register 5041 * Host Channel 1 Interrupt Mask Register 5042 */ 5043 #define USB_HCINTMSK1_REG (SOC_DPORT_USB_BASE + 0x52c) 5044 /** USB_H_XFERCOMPLMSK1 : R/W; bitpos: [0]; default: 0; 5045 * 1'b0: Transfer Completed Mask 5046 * 1'b1: No Transfer Completed Mask 5047 */ 5048 #define USB_H_XFERCOMPLMSK1 (BIT(0)) 5049 #define USB_H_XFERCOMPLMSK1_M (USB_H_XFERCOMPLMSK1_V << USB_H_XFERCOMPLMSK1_S) 5050 #define USB_H_XFERCOMPLMSK1_V 0x00000001 5051 #define USB_H_XFERCOMPLMSK1_S 0 5052 /** USB_H_CHHLTDMSK1 : R/W; bitpos: [1]; default: 0; 5053 * 1'b0: Channel Halted Mask 5054 * 1'b1: No Channel Halted Mask 5055 */ 5056 #define USB_H_CHHLTDMSK1 (BIT(1)) 5057 #define USB_H_CHHLTDMSK1_M (USB_H_CHHLTDMSK1_V << USB_H_CHHLTDMSK1_S) 5058 #define USB_H_CHHLTDMSK1_V 0x00000001 5059 #define USB_H_CHHLTDMSK1_S 1 5060 /** USB_H_AHBERRMSK1 : R/W; bitpos: [2]; default: 0; 5061 * 1'b0: AHB Error Mask 5062 * 1'b1: No AHB Error Mask 5063 */ 5064 #define USB_H_AHBERRMSK1 (BIT(2)) 5065 #define USB_H_AHBERRMSK1_M (USB_H_AHBERRMSK1_V << USB_H_AHBERRMSK1_S) 5066 #define USB_H_AHBERRMSK1_V 0x00000001 5067 #define USB_H_AHBERRMSK1_S 2 5068 /** USB_H_STALLMSK1 : R/W; bitpos: [3]; default: 0; 5069 * 1'b0: Mask STALL Response Received Interrupt 5070 * 1'b1: No STALL Response Received Interrupt Mask 5071 */ 5072 #define USB_H_STALLMSK1 (BIT(3)) 5073 #define USB_H_STALLMSK1_M (USB_H_STALLMSK1_V << USB_H_STALLMSK1_S) 5074 #define USB_H_STALLMSK1_V 0x00000001 5075 #define USB_H_STALLMSK1_S 3 5076 /** USB_H_NAKMSK1 : R/W; bitpos: [4]; default: 0; 5077 * 1'b0: Mask NAK Response Received Interrupt 5078 * 1'b1: No NAK Response Received Interrupt Mask 5079 */ 5080 #define USB_H_NAKMSK1 (BIT(4)) 5081 #define USB_H_NAKMSK1_M (USB_H_NAKMSK1_V << USB_H_NAKMSK1_S) 5082 #define USB_H_NAKMSK1_V 0x00000001 5083 #define USB_H_NAKMSK1_S 4 5084 /** USB_H_ACKMSK1 : R/W; bitpos: [5]; default: 0; 5085 * 1'b0: Mask ACK Response Received/Transmitted Interrupt 5086 * 1'b1: No ACK Response Received/Transmitted Interrupt Mask 5087 */ 5088 #define USB_H_ACKMSK1 (BIT(5)) 5089 #define USB_H_ACKMSK1_M (USB_H_ACKMSK1_V << USB_H_ACKMSK1_S) 5090 #define USB_H_ACKMSK1_V 0x00000001 5091 #define USB_H_ACKMSK1_S 5 5092 /** USB_H_NYETMSK1 : R/W; bitpos: [6]; default: 0; 5093 * 1'b0: Mask NYET Response Received Interrupt 5094 * 1'b1: No NYET Response Received Interrupt Mask 5095 */ 5096 #define USB_H_NYETMSK1 (BIT(6)) 5097 #define USB_H_NYETMSK1_M (USB_H_NYETMSK1_V << USB_H_NYETMSK1_S) 5098 #define USB_H_NYETMSK1_V 0x00000001 5099 #define USB_H_NYETMSK1_S 6 5100 /** USB_H_XACTERRMSK1 : R/W; bitpos: [7]; default: 0; 5101 * 1'b0: Mask Transaction Error 5102 * 1'b1: No Transaction Error Mask 5103 */ 5104 #define USB_H_XACTERRMSK1 (BIT(7)) 5105 #define USB_H_XACTERRMSK1_M (USB_H_XACTERRMSK1_V << USB_H_XACTERRMSK1_S) 5106 #define USB_H_XACTERRMSK1_V 0x00000001 5107 #define USB_H_XACTERRMSK1_S 7 5108 /** USB_H_BBLERRMSK1 : R/W; bitpos: [8]; default: 0; 5109 * Babble Error Mask 5110 * 1'b0: Mask Babble Error 5111 * 1'b1: No Babble Error Mask 5112 */ 5113 #define USB_H_BBLERRMSK1 (BIT(8)) 5114 #define USB_H_BBLERRMSK1_M (USB_H_BBLERRMSK1_V << USB_H_BBLERRMSK1_S) 5115 #define USB_H_BBLERRMSK1_V 0x00000001 5116 #define USB_H_BBLERRMSK1_S 8 5117 /** USB_H_FRMOVRUNMSK1 : R/W; bitpos: [9]; default: 0; 5118 * Frame Overrun Mask 5119 * 0x0 (MASK): Mask Overrun Mask 5120 * 0x1 (NOMASK): No Frame Overrun Mask 5121 */ 5122 #define USB_H_FRMOVRUNMSK1 (BIT(9)) 5123 #define USB_H_FRMOVRUNMSK1_M (USB_H_FRMOVRUNMSK1_V << USB_H_FRMOVRUNMSK1_S) 5124 #define USB_H_FRMOVRUNMSK1_V 0x00000001 5125 #define USB_H_FRMOVRUNMSK1_S 9 5126 /** USB_H_DATATGLERRMSK1 : R/W; bitpos: [10]; default: 0; 5127 * Data Toggle Error Mask n scatter/gather DMA mode for host 5128 * 1'b0: Mask Data Toggle Error 5129 * 1'b1: No Data Toggle Error Mask 5130 */ 5131 #define USB_H_DATATGLERRMSK1 (BIT(10)) 5132 #define USB_H_DATATGLERRMSK1_M (USB_H_DATATGLERRMSK1_V << USB_H_DATATGLERRMSK1_S) 5133 #define USB_H_DATATGLERRMSK1_V 0x00000001 5134 #define USB_H_DATATGLERRMSK1_S 10 5135 /** USB_H_BNAINTRMSK1 : R/W; bitpos: [11]; default: 0; 5136 * BNA (Buffer Not Available) Interrupt mask register 5137 * 1'b0: BNA Interrupt Masked 5138 * 1'b1: BNA Interrupt not masked 5139 */ 5140 #define USB_H_BNAINTRMSK1 (BIT(11)) 5141 #define USB_H_BNAINTRMSK1_M (USB_H_BNAINTRMSK1_V << USB_H_BNAINTRMSK1_S) 5142 #define USB_H_BNAINTRMSK1_V 0x00000001 5143 #define USB_H_BNAINTRMSK1_S 11 5144 /** USB_H_DESC_LST_ROLLINTRMSK1 : R/W; bitpos: [13]; default: 0; 5145 * Descriptor List rollover interrupt Mask 5146 * 1'b0: Descriptor Rollover Interrupt Mask 5147 * 1'b1: Descriptor Rollover Interrupt not masked 5148 */ 5149 #define USB_H_DESC_LST_ROLLINTRMSK1 (BIT(13)) 5150 #define USB_H_DESC_LST_ROLLINTRMSK1_M (USB_H_DESC_LST_ROLLINTRMSK1_V << USB_H_DESC_LST_ROLLINTRMSK1_S) 5151 #define USB_H_DESC_LST_ROLLINTRMSK1_V 0x00000001 5152 #define USB_H_DESC_LST_ROLLINTRMSK1_S 13 5153 5154 5155 /** USB_HCINT2_REG register 5156 * Host Channel 2 Interrupt Register 5157 */ 5158 #define USB_HCINT2_REG (SOC_DPORT_USB_BASE + 0x548) 5159 /** USB_H_XFERCOMPL2 : R/W1C; bitpos: [0]; default: 0; 5160 * 1'b0: Transfer in progress or No Active Transfer 5161 * 1'b1: Transfer completed normally without any errors 5162 */ 5163 #define USB_H_XFERCOMPL2 (BIT(0)) 5164 #define USB_H_XFERCOMPL2_M (USB_H_XFERCOMPL2_V << USB_H_XFERCOMPL2_S) 5165 #define USB_H_XFERCOMPL2_V 0x00000001 5166 #define USB_H_XFERCOMPL2_S 0 5167 /** USB_H_CHHLTD2 : R/W1C; bitpos: [1]; default: 0; 5168 * 1'b0: Channel not halted 5169 * 1'b1: Channel Halted 5170 */ 5171 #define USB_H_CHHLTD2 (BIT(1)) 5172 #define USB_H_CHHLTD2_M (USB_H_CHHLTD2_V << USB_H_CHHLTD2_S) 5173 #define USB_H_CHHLTD2_V 0x00000001 5174 #define USB_H_CHHLTD2_S 1 5175 /** USB_H_AHBERR2 : R/W1C; bitpos: [2]; default: 0; 5176 * 1'b0: No AHB error 5177 * 1'b1: AHB error during AHB read/write 5178 */ 5179 #define USB_H_AHBERR2 (BIT(2)) 5180 #define USB_H_AHBERR2_M (USB_H_AHBERR2_V << USB_H_AHBERR2_S) 5181 #define USB_H_AHBERR2_V 0x00000001 5182 #define USB_H_AHBERR2_S 2 5183 /** USB_H_STALL2 : R/W1C; bitpos: [3]; default: 0; 5184 * 1'b0: No Stall Response Received Interrupt 5185 * 1'b1: Stall Response Received Interrupt 5186 */ 5187 #define USB_H_STALL2 (BIT(3)) 5188 #define USB_H_STALL2_M (USB_H_STALL2_V << USB_H_STALL2_S) 5189 #define USB_H_STALL2_V 0x00000001 5190 #define USB_H_STALL2_S 3 5191 /** USB_H_NACK2 : R/W1C; bitpos: [4]; default: 0; 5192 * 1'b0: No NAK Response Received Interrupt 5193 * 1'b1: NAK Response Received Interrupt 5194 */ 5195 #define USB_H_NACK2 (BIT(4)) 5196 #define USB_H_NACK2_M (USB_H_NACK2_V << USB_H_NACK2_S) 5197 #define USB_H_NACK2_V 0x00000001 5198 #define USB_H_NACK2_S 4 5199 /** USB_H_ACK2 : R/W1C; bitpos: [5]; default: 0; 5200 * 1'b0: No ACK Response Received or Transmitted Interrupt 5201 * 1'b1: ACK Response Received or Transmitted Interrup 5202 */ 5203 #define USB_H_ACK2 (BIT(5)) 5204 #define USB_H_ACK2_M (USB_H_ACK2_V << USB_H_ACK2_S) 5205 #define USB_H_ACK2_V 0x00000001 5206 #define USB_H_ACK2_S 5 5207 /** USB_H_NYET2 : R/W1C; bitpos: [6]; default: 0; 5208 * 1'b0: No NYET Response Received Interrupt 5209 * 1'b1: NYET Response Received Interrupt 5210 */ 5211 #define USB_H_NYET2 (BIT(6)) 5212 #define USB_H_NYET2_M (USB_H_NYET2_V << USB_H_NYET2_S) 5213 #define USB_H_NYET2_V 0x00000001 5214 #define USB_H_NYET2_S 6 5215 /** USB_H_XACTERR2 : R/W1C; bitpos: [7]; default: 0; 5216 * Indicates one of the following errors occurred on the USB: 5217 * CRC check failure 5218 * Timeout 5219 * Bit stuff error 5220 * False EOP 5221 */ 5222 #define USB_H_XACTERR2 (BIT(7)) 5223 #define USB_H_XACTERR2_M (USB_H_XACTERR2_V << USB_H_XACTERR2_S) 5224 #define USB_H_XACTERR2_V 0x00000001 5225 #define USB_H_XACTERR2_S 7 5226 /** USB_H_BBLERR2 : R/W1C; bitpos: [8]; default: 0; 5227 * 1'b0: No Babble Error 5228 * 1'b1: Babble Error 5229 */ 5230 #define USB_H_BBLERR2 (BIT(8)) 5231 #define USB_H_BBLERR2_M (USB_H_BBLERR2_V << USB_H_BBLERR2_S) 5232 #define USB_H_BBLERR2_V 0x00000001 5233 #define USB_H_BBLERR2_S 8 5234 /** USB_H_FRMOVRUN2 : R/W1C; bitpos: [9]; default: 0; 5235 * 1'b0: No Frame Overrun 5236 * 1'b1: Frame Overrun 5237 */ 5238 #define USB_H_FRMOVRUN2 (BIT(9)) 5239 #define USB_H_FRMOVRUN2_M (USB_H_FRMOVRUN2_V << USB_H_FRMOVRUN2_S) 5240 #define USB_H_FRMOVRUN2_V 0x00000001 5241 #define USB_H_FRMOVRUN2_S 9 5242 /** USB_H_DATATGLERR2 : R/W1C; bitpos: [10]; default: 0; 5243 * 1'b0: No Data Toggle Error 5244 * 1'b1: Data Toggle Error 5245 */ 5246 #define USB_H_DATATGLERR2 (BIT(10)) 5247 #define USB_H_DATATGLERR2_M (USB_H_DATATGLERR2_V << USB_H_DATATGLERR2_S) 5248 #define USB_H_DATATGLERR2_V 0x00000001 5249 #define USB_H_DATATGLERR2_S 10 5250 /** USB_H_BNAINTR2 : R/W1C; bitpos: [11]; default: 0; 5251 * 1'b0: No BNA Interrupt 5252 * 1'b1: BNA Interrupt 5253 */ 5254 #define USB_H_BNAINTR2 (BIT(11)) 5255 #define USB_H_BNAINTR2_M (USB_H_BNAINTR2_V << USB_H_BNAINTR2_S) 5256 #define USB_H_BNAINTR2_V 0x00000001 5257 #define USB_H_BNAINTR2_S 11 5258 /** USB_H_XCS_XACT_ERR2 : R/W1C; bitpos: [12]; default: 0; 5259 * 1'b0: No Excessive Transaction Error 5260 * 1'b1: Excessive Transaction Error 5261 */ 5262 #define USB_H_XCS_XACT_ERR2 (BIT(12)) 5263 #define USB_H_XCS_XACT_ERR2_M (USB_H_XCS_XACT_ERR2_V << USB_H_XCS_XACT_ERR2_S) 5264 #define USB_H_XCS_XACT_ERR2_V 0x00000001 5265 #define USB_H_XCS_XACT_ERR2_S 12 5266 /** USB_H_DESC_LST_ROLLINTR2 : R/W1C; bitpos: [13]; default: 0; 5267 * 1'b0: No Descriptor rollover interrupt 5268 * 1'b1: Descriptor rollover interrupt 5269 */ 5270 #define USB_H_DESC_LST_ROLLINTR2 (BIT(13)) 5271 #define USB_H_DESC_LST_ROLLINTR2_M (USB_H_DESC_LST_ROLLINTR2_V << USB_H_DESC_LST_ROLLINTR2_S) 5272 #define USB_H_DESC_LST_ROLLINTR2_V 0x00000001 5273 #define USB_H_DESC_LST_ROLLINTR2_S 13 5274 5275 5276 /** USB_HCINTMSK2_REG register 5277 * Host Channel 2 Interrupt Mask Register 5278 */ 5279 #define USB_HCINTMSK2_REG (SOC_DPORT_USB_BASE + 0x54c) 5280 /** USB_H_XFERCOMPLMSK2 : R/W; bitpos: [0]; default: 0; 5281 * 1'b0: Transfer Completed Mask 5282 * 1'b1: No Transfer Completed Mask 5283 */ 5284 #define USB_H_XFERCOMPLMSK2 (BIT(0)) 5285 #define USB_H_XFERCOMPLMSK2_M (USB_H_XFERCOMPLMSK2_V << USB_H_XFERCOMPLMSK2_S) 5286 #define USB_H_XFERCOMPLMSK2_V 0x00000001 5287 #define USB_H_XFERCOMPLMSK2_S 0 5288 /** USB_H_CHHLTDMSK2 : R/W; bitpos: [1]; default: 0; 5289 * 1'b0: Channel Halted Mask 5290 * 1'b1: No Channel Halted Mask 5291 */ 5292 #define USB_H_CHHLTDMSK2 (BIT(1)) 5293 #define USB_H_CHHLTDMSK2_M (USB_H_CHHLTDMSK2_V << USB_H_CHHLTDMSK2_S) 5294 #define USB_H_CHHLTDMSK2_V 0x00000001 5295 #define USB_H_CHHLTDMSK2_S 1 5296 /** USB_H_AHBERRMSK2 : R/W; bitpos: [2]; default: 0; 5297 * 1'b0: AHB Error Mask 5298 * 1'b1: No AHB Error Mask 5299 */ 5300 #define USB_H_AHBERRMSK2 (BIT(2)) 5301 #define USB_H_AHBERRMSK2_M (USB_H_AHBERRMSK2_V << USB_H_AHBERRMSK2_S) 5302 #define USB_H_AHBERRMSK2_V 0x00000001 5303 #define USB_H_AHBERRMSK2_S 2 5304 /** USB_H_STALLMSK2 : R/W; bitpos: [3]; default: 0; 5305 * 1'b0: Mask STALL Response Received Interrupt 5306 * 1'b1: No STALL Response Received Interrupt Mask 5307 */ 5308 #define USB_H_STALLMSK2 (BIT(3)) 5309 #define USB_H_STALLMSK2_M (USB_H_STALLMSK2_V << USB_H_STALLMSK2_S) 5310 #define USB_H_STALLMSK2_V 0x00000001 5311 #define USB_H_STALLMSK2_S 3 5312 /** USB_H_NAKMSK2 : R/W; bitpos: [4]; default: 0; 5313 * 1'b0: Mask NAK Response Received Interrupt 5314 * 1'b1: No NAK Response Received Interrupt Mask 5315 */ 5316 #define USB_H_NAKMSK2 (BIT(4)) 5317 #define USB_H_NAKMSK2_M (USB_H_NAKMSK2_V << USB_H_NAKMSK2_S) 5318 #define USB_H_NAKMSK2_V 0x00000001 5319 #define USB_H_NAKMSK2_S 4 5320 /** USB_H_ACKMSK2 : R/W; bitpos: [5]; default: 0; 5321 * 1'b0: Mask ACK Response Received/Transmitted Interrupt 5322 * 1'b1: No ACK Response Received/Transmitted Interrupt Mask 5323 */ 5324 #define USB_H_ACKMSK2 (BIT(5)) 5325 #define USB_H_ACKMSK2_M (USB_H_ACKMSK2_V << USB_H_ACKMSK2_S) 5326 #define USB_H_ACKMSK2_V 0x00000001 5327 #define USB_H_ACKMSK2_S 5 5328 /** USB_H_NYETMSK2 : R/W; bitpos: [6]; default: 0; 5329 * 1'b0: Mask NYET Response Received Interrupt 5330 * 1'b1: No NYET Response Received Interrupt Mask 5331 */ 5332 #define USB_H_NYETMSK2 (BIT(6)) 5333 #define USB_H_NYETMSK2_M (USB_H_NYETMSK2_V << USB_H_NYETMSK2_S) 5334 #define USB_H_NYETMSK2_V 0x00000001 5335 #define USB_H_NYETMSK2_S 6 5336 /** USB_H_XACTERRMSK2 : R/W; bitpos: [7]; default: 0; 5337 * 1'b0: Mask Transaction Error 5338 * 1'b1: No Transaction Error Mask 5339 */ 5340 #define USB_H_XACTERRMSK2 (BIT(7)) 5341 #define USB_H_XACTERRMSK2_M (USB_H_XACTERRMSK2_V << USB_H_XACTERRMSK2_S) 5342 #define USB_H_XACTERRMSK2_V 0x00000001 5343 #define USB_H_XACTERRMSK2_S 7 5344 /** USB_H_BBLERRMSK2 : R/W; bitpos: [8]; default: 0; 5345 * Babble Error Mask 5346 * 1'b0: Mask Babble Error 5347 * 1'b1: No Babble Error Mask 5348 */ 5349 #define USB_H_BBLERRMSK2 (BIT(8)) 5350 #define USB_H_BBLERRMSK2_M (USB_H_BBLERRMSK2_V << USB_H_BBLERRMSK2_S) 5351 #define USB_H_BBLERRMSK2_V 0x00000001 5352 #define USB_H_BBLERRMSK2_S 8 5353 /** USB_H_FRMOVRUNMSK2 : R/W; bitpos: [9]; default: 0; 5354 * Frame Overrun Mask 5355 * 0x0 (MASK): Mask Overrun Mask 5356 * 0x1 (NOMASK): No Frame Overrun Mask 5357 */ 5358 #define USB_H_FRMOVRUNMSK2 (BIT(9)) 5359 #define USB_H_FRMOVRUNMSK2_M (USB_H_FRMOVRUNMSK2_V << USB_H_FRMOVRUNMSK2_S) 5360 #define USB_H_FRMOVRUNMSK2_V 0x00000001 5361 #define USB_H_FRMOVRUNMSK2_S 9 5362 /** USB_H_DATATGLERRMSK2 : R/W; bitpos: [10]; default: 0; 5363 * Data Toggle Error Mask n scatter/gather DMA mode for host 5364 * 1'b0: Mask Data Toggle Error 5365 * 1'b1: No Data Toggle Error Mask 5366 */ 5367 #define USB_H_DATATGLERRMSK2 (BIT(10)) 5368 #define USB_H_DATATGLERRMSK2_M (USB_H_DATATGLERRMSK2_V << USB_H_DATATGLERRMSK2_S) 5369 #define USB_H_DATATGLERRMSK2_V 0x00000001 5370 #define USB_H_DATATGLERRMSK2_S 10 5371 /** USB_H_BNAINTRMSK2 : R/W; bitpos: [11]; default: 0; 5372 * BNA (Buffer Not Available) Interrupt mask register 5373 * 1'b0: BNA Interrupt Masked 5374 * 1'b1: BNA Interrupt not masked 5375 */ 5376 #define USB_H_BNAINTRMSK2 (BIT(11)) 5377 #define USB_H_BNAINTRMSK2_M (USB_H_BNAINTRMSK2_V << USB_H_BNAINTRMSK2_S) 5378 #define USB_H_BNAINTRMSK2_V 0x00000001 5379 #define USB_H_BNAINTRMSK2_S 11 5380 /** USB_H_DESC_LST_ROLLINTRMSK2 : R/W; bitpos: [13]; default: 0; 5381 * Descriptor List rollover interrupt Mask 5382 * 1'b0: Descriptor Rollover Interrupt Mask 5383 * 1'b1: Descriptor Rollover Interrupt not masked 5384 */ 5385 #define USB_H_DESC_LST_ROLLINTRMSK2 (BIT(13)) 5386 #define USB_H_DESC_LST_ROLLINTRMSK2_M (USB_H_DESC_LST_ROLLINTRMSK2_V << USB_H_DESC_LST_ROLLINTRMSK2_S) 5387 #define USB_H_DESC_LST_ROLLINTRMSK2_V 0x00000001 5388 #define USB_H_DESC_LST_ROLLINTRMSK2_S 13 5389 5390 5391 /** USB_HCINT3_REG register 5392 * Host Channel 3 Interrupt Register 5393 */ 5394 #define USB_HCINT3_REG (SOC_DPORT_USB_BASE + 0x568) 5395 /** USB_H_XFERCOMPL3 : R/W1C; bitpos: [0]; default: 0; 5396 * 1'b0: Transfer in progress or No Active Transfer 5397 * 1'b1: Transfer completed normally without any errors 5398 */ 5399 #define USB_H_XFERCOMPL3 (BIT(0)) 5400 #define USB_H_XFERCOMPL3_M (USB_H_XFERCOMPL3_V << USB_H_XFERCOMPL3_S) 5401 #define USB_H_XFERCOMPL3_V 0x00000001 5402 #define USB_H_XFERCOMPL3_S 0 5403 /** USB_H_CHHLTD3 : R/W1C; bitpos: [1]; default: 0; 5404 * 1'b0: Channel not halted 5405 * 1'b1: Channel Halted 5406 */ 5407 #define USB_H_CHHLTD3 (BIT(1)) 5408 #define USB_H_CHHLTD3_M (USB_H_CHHLTD3_V << USB_H_CHHLTD3_S) 5409 #define USB_H_CHHLTD3_V 0x00000001 5410 #define USB_H_CHHLTD3_S 1 5411 /** USB_H_AHBERR3 : R/W1C; bitpos: [2]; default: 0; 5412 * 1'b0: No AHB error 5413 * 1'b1: AHB error during AHB read/write 5414 */ 5415 #define USB_H_AHBERR3 (BIT(2)) 5416 #define USB_H_AHBERR3_M (USB_H_AHBERR3_V << USB_H_AHBERR3_S) 5417 #define USB_H_AHBERR3_V 0x00000001 5418 #define USB_H_AHBERR3_S 2 5419 /** USB_H_STALL3 : R/W1C; bitpos: [3]; default: 0; 5420 * 1'b0: No Stall Response Received Interrupt 5421 * 1'b1: Stall Response Received Interrupt 5422 */ 5423 #define USB_H_STALL3 (BIT(3)) 5424 #define USB_H_STALL3_M (USB_H_STALL3_V << USB_H_STALL3_S) 5425 #define USB_H_STALL3_V 0x00000001 5426 #define USB_H_STALL3_S 3 5427 /** USB_H_NACK3 : R/W1C; bitpos: [4]; default: 0; 5428 * 1'b0: No NAK Response Received Interrupt 5429 * 1'b1: NAK Response Received Interrupt 5430 */ 5431 #define USB_H_NACK3 (BIT(4)) 5432 #define USB_H_NACK3_M (USB_H_NACK3_V << USB_H_NACK3_S) 5433 #define USB_H_NACK3_V 0x00000001 5434 #define USB_H_NACK3_S 4 5435 /** USB_H_ACK3 : R/W1C; bitpos: [5]; default: 0; 5436 * 1'b0: No ACK Response Received or Transmitted Interrupt 5437 * 1'b1: ACK Response Received or Transmitted Interrup 5438 */ 5439 #define USB_H_ACK3 (BIT(5)) 5440 #define USB_H_ACK3_M (USB_H_ACK3_V << USB_H_ACK3_S) 5441 #define USB_H_ACK3_V 0x00000001 5442 #define USB_H_ACK3_S 5 5443 /** USB_H_NYET3 : R/W1C; bitpos: [6]; default: 0; 5444 * 1'b0: No NYET Response Received Interrupt 5445 * 1'b1: NYET Response Received Interrupt 5446 */ 5447 #define USB_H_NYET3 (BIT(6)) 5448 #define USB_H_NYET3_M (USB_H_NYET3_V << USB_H_NYET3_S) 5449 #define USB_H_NYET3_V 0x00000001 5450 #define USB_H_NYET3_S 6 5451 /** USB_H_XACTERR3 : R/W1C; bitpos: [7]; default: 0; 5452 * Indicates one of the following errors occurred on the USB: 5453 * CRC check failure 5454 * Timeout 5455 * Bit stuff error 5456 * False EOP 5457 */ 5458 #define USB_H_XACTERR3 (BIT(7)) 5459 #define USB_H_XACTERR3_M (USB_H_XACTERR3_V << USB_H_XACTERR3_S) 5460 #define USB_H_XACTERR3_V 0x00000001 5461 #define USB_H_XACTERR3_S 7 5462 /** USB_H_BBLERR3 : R/W1C; bitpos: [8]; default: 0; 5463 * 1'b0: No Babble Error 5464 * 1'b1: Babble Error 5465 */ 5466 #define USB_H_BBLERR3 (BIT(8)) 5467 #define USB_H_BBLERR3_M (USB_H_BBLERR3_V << USB_H_BBLERR3_S) 5468 #define USB_H_BBLERR3_V 0x00000001 5469 #define USB_H_BBLERR3_S 8 5470 /** USB_H_FRMOVRUN3 : R/W1C; bitpos: [9]; default: 0; 5471 * 1'b0: No Frame Overrun 5472 * 1'b1: Frame Overrun 5473 */ 5474 #define USB_H_FRMOVRUN3 (BIT(9)) 5475 #define USB_H_FRMOVRUN3_M (USB_H_FRMOVRUN3_V << USB_H_FRMOVRUN3_S) 5476 #define USB_H_FRMOVRUN3_V 0x00000001 5477 #define USB_H_FRMOVRUN3_S 9 5478 /** USB_H_DATATGLERR3 : R/W1C; bitpos: [10]; default: 0; 5479 * 1'b0: No Data Toggle Error 5480 * 1'b1: Data Toggle Error 5481 */ 5482 #define USB_H_DATATGLERR3 (BIT(10)) 5483 #define USB_H_DATATGLERR3_M (USB_H_DATATGLERR3_V << USB_H_DATATGLERR3_S) 5484 #define USB_H_DATATGLERR3_V 0x00000001 5485 #define USB_H_DATATGLERR3_S 10 5486 /** USB_H_BNAINTR3 : R/W1C; bitpos: [11]; default: 0; 5487 * 1'b0: No BNA Interrupt 5488 * 1'b1: BNA Interrupt 5489 */ 5490 #define USB_H_BNAINTR3 (BIT(11)) 5491 #define USB_H_BNAINTR3_M (USB_H_BNAINTR3_V << USB_H_BNAINTR3_S) 5492 #define USB_H_BNAINTR3_V 0x00000001 5493 #define USB_H_BNAINTR3_S 11 5494 /** USB_H_XCS_XACT_ERR3 : R/W1C; bitpos: [12]; default: 0; 5495 * 1'b0: No Excessive Transaction Error 5496 * 1'b1: Excessive Transaction Error 5497 */ 5498 #define USB_H_XCS_XACT_ERR3 (BIT(12)) 5499 #define USB_H_XCS_XACT_ERR3_M (USB_H_XCS_XACT_ERR3_V << USB_H_XCS_XACT_ERR3_S) 5500 #define USB_H_XCS_XACT_ERR3_V 0x00000001 5501 #define USB_H_XCS_XACT_ERR3_S 12 5502 /** USB_H_DESC_LST_ROLLINTR3 : R/W1C; bitpos: [13]; default: 0; 5503 * 1'b0: No Descriptor rollover interrupt 5504 * 1'b1: Descriptor rollover interrupt 5505 */ 5506 #define USB_H_DESC_LST_ROLLINTR3 (BIT(13)) 5507 #define USB_H_DESC_LST_ROLLINTR3_M (USB_H_DESC_LST_ROLLINTR3_V << USB_H_DESC_LST_ROLLINTR3_S) 5508 #define USB_H_DESC_LST_ROLLINTR3_V 0x00000001 5509 #define USB_H_DESC_LST_ROLLINTR3_S 13 5510 5511 5512 /** USB_HCINTMSK3_REG register 5513 * Host Channel 3 Interrupt Mask Register 5514 */ 5515 #define USB_HCINTMSK3_REG (SOC_DPORT_USB_BASE + 0x56c) 5516 /** USB_H_XFERCOMPLMSK3 : R/W; bitpos: [0]; default: 0; 5517 * 1'b0: Transfer Completed Mask 5518 * 1'b1: No Transfer Completed Mask 5519 */ 5520 #define USB_H_XFERCOMPLMSK3 (BIT(0)) 5521 #define USB_H_XFERCOMPLMSK3_M (USB_H_XFERCOMPLMSK3_V << USB_H_XFERCOMPLMSK3_S) 5522 #define USB_H_XFERCOMPLMSK3_V 0x00000001 5523 #define USB_H_XFERCOMPLMSK3_S 0 5524 /** USB_H_CHHLTDMSK3 : R/W; bitpos: [1]; default: 0; 5525 * 1'b0: Channel Halted Mask 5526 * 1'b1: No Channel Halted Mask 5527 */ 5528 #define USB_H_CHHLTDMSK3 (BIT(1)) 5529 #define USB_H_CHHLTDMSK3_M (USB_H_CHHLTDMSK3_V << USB_H_CHHLTDMSK3_S) 5530 #define USB_H_CHHLTDMSK3_V 0x00000001 5531 #define USB_H_CHHLTDMSK3_S 1 5532 /** USB_H_AHBERRMSK3 : R/W; bitpos: [2]; default: 0; 5533 * 1'b0: AHB Error Mask 5534 * 1'b1: No AHB Error Mask 5535 */ 5536 #define USB_H_AHBERRMSK3 (BIT(2)) 5537 #define USB_H_AHBERRMSK3_M (USB_H_AHBERRMSK3_V << USB_H_AHBERRMSK3_S) 5538 #define USB_H_AHBERRMSK3_V 0x00000001 5539 #define USB_H_AHBERRMSK3_S 2 5540 /** USB_H_STALLMSK3 : R/W; bitpos: [3]; default: 0; 5541 * 1'b0: Mask STALL Response Received Interrupt 5542 * 1'b1: No STALL Response Received Interrupt Mask 5543 */ 5544 #define USB_H_STALLMSK3 (BIT(3)) 5545 #define USB_H_STALLMSK3_M (USB_H_STALLMSK3_V << USB_H_STALLMSK3_S) 5546 #define USB_H_STALLMSK3_V 0x00000001 5547 #define USB_H_STALLMSK3_S 3 5548 /** USB_H_NAKMSK3 : R/W; bitpos: [4]; default: 0; 5549 * 1'b0: Mask NAK Response Received Interrupt 5550 * 1'b1: No NAK Response Received Interrupt Mask 5551 */ 5552 #define USB_H_NAKMSK3 (BIT(4)) 5553 #define USB_H_NAKMSK3_M (USB_H_NAKMSK3_V << USB_H_NAKMSK3_S) 5554 #define USB_H_NAKMSK3_V 0x00000001 5555 #define USB_H_NAKMSK3_S 4 5556 /** USB_H_ACKMSK3 : R/W; bitpos: [5]; default: 0; 5557 * 1'b0: Mask ACK Response Received/Transmitted Interrupt 5558 * 1'b1: No ACK Response Received/Transmitted Interrupt Mask 5559 */ 5560 #define USB_H_ACKMSK3 (BIT(5)) 5561 #define USB_H_ACKMSK3_M (USB_H_ACKMSK3_V << USB_H_ACKMSK3_S) 5562 #define USB_H_ACKMSK3_V 0x00000001 5563 #define USB_H_ACKMSK3_S 5 5564 /** USB_H_NYETMSK3 : R/W; bitpos: [6]; default: 0; 5565 * 1'b0: Mask NYET Response Received Interrupt 5566 * 1'b1: No NYET Response Received Interrupt Mask 5567 */ 5568 #define USB_H_NYETMSK3 (BIT(6)) 5569 #define USB_H_NYETMSK3_M (USB_H_NYETMSK3_V << USB_H_NYETMSK3_S) 5570 #define USB_H_NYETMSK3_V 0x00000001 5571 #define USB_H_NYETMSK3_S 6 5572 /** USB_H_XACTERRMSK3 : R/W; bitpos: [7]; default: 0; 5573 * 1'b0: Mask Transaction Error 5574 * 1'b1: No Transaction Error Mask 5575 */ 5576 #define USB_H_XACTERRMSK3 (BIT(7)) 5577 #define USB_H_XACTERRMSK3_M (USB_H_XACTERRMSK3_V << USB_H_XACTERRMSK3_S) 5578 #define USB_H_XACTERRMSK3_V 0x00000001 5579 #define USB_H_XACTERRMSK3_S 7 5580 /** USB_H_BBLERRMSK3 : R/W; bitpos: [8]; default: 0; 5581 * Babble Error Mask 5582 * 1'b0: Mask Babble Error 5583 * 1'b1: No Babble Error Mask 5584 */ 5585 #define USB_H_BBLERRMSK3 (BIT(8)) 5586 #define USB_H_BBLERRMSK3_M (USB_H_BBLERRMSK3_V << USB_H_BBLERRMSK3_S) 5587 #define USB_H_BBLERRMSK3_V 0x00000001 5588 #define USB_H_BBLERRMSK3_S 8 5589 /** USB_H_FRMOVRUNMSK3 : R/W; bitpos: [9]; default: 0; 5590 * Frame Overrun Mask 5591 * 0x0 (MASK): Mask Overrun Mask 5592 * 0x1 (NOMASK): No Frame Overrun Mask 5593 */ 5594 #define USB_H_FRMOVRUNMSK3 (BIT(9)) 5595 #define USB_H_FRMOVRUNMSK3_M (USB_H_FRMOVRUNMSK3_V << USB_H_FRMOVRUNMSK3_S) 5596 #define USB_H_FRMOVRUNMSK3_V 0x00000001 5597 #define USB_H_FRMOVRUNMSK3_S 9 5598 /** USB_H_DATATGLERRMSK3 : R/W; bitpos: [10]; default: 0; 5599 * Data Toggle Error Mask n scatter/gather DMA mode for host 5600 * 1'b0: Mask Data Toggle Error 5601 * 1'b1: No Data Toggle Error Mask 5602 */ 5603 #define USB_H_DATATGLERRMSK3 (BIT(10)) 5604 #define USB_H_DATATGLERRMSK3_M (USB_H_DATATGLERRMSK3_V << USB_H_DATATGLERRMSK3_S) 5605 #define USB_H_DATATGLERRMSK3_V 0x00000001 5606 #define USB_H_DATATGLERRMSK3_S 10 5607 /** USB_H_BNAINTRMSK3 : R/W; bitpos: [11]; default: 0; 5608 * BNA (Buffer Not Available) Interrupt mask register 5609 * 1'b0: BNA Interrupt Masked 5610 * 1'b1: BNA Interrupt not masked 5611 */ 5612 #define USB_H_BNAINTRMSK3 (BIT(11)) 5613 #define USB_H_BNAINTRMSK3_M (USB_H_BNAINTRMSK3_V << USB_H_BNAINTRMSK3_S) 5614 #define USB_H_BNAINTRMSK3_V 0x00000001 5615 #define USB_H_BNAINTRMSK3_S 11 5616 /** USB_H_DESC_LST_ROLLINTRMSK3 : R/W; bitpos: [13]; default: 0; 5617 * Descriptor List rollover interrupt Mask 5618 * 1'b0: Descriptor Rollover Interrupt Mask 5619 * 1'b1: Descriptor Rollover Interrupt not masked 5620 */ 5621 #define USB_H_DESC_LST_ROLLINTRMSK3 (BIT(13)) 5622 #define USB_H_DESC_LST_ROLLINTRMSK3_M (USB_H_DESC_LST_ROLLINTRMSK3_V << USB_H_DESC_LST_ROLLINTRMSK3_S) 5623 #define USB_H_DESC_LST_ROLLINTRMSK3_V 0x00000001 5624 #define USB_H_DESC_LST_ROLLINTRMSK3_S 13 5625 5626 5627 /** USB_HCINT4_REG register 5628 * Host Channel 4 Interrupt Register 5629 */ 5630 #define USB_HCINT4_REG (SOC_DPORT_USB_BASE + 0x588) 5631 /** USB_H_XFERCOMPL4 : R/W1C; bitpos: [0]; default: 0; 5632 * 1'b0: Transfer in progress or No Active Transfer 5633 * 1'b1: Transfer completed normally without any errors 5634 */ 5635 #define USB_H_XFERCOMPL4 (BIT(0)) 5636 #define USB_H_XFERCOMPL4_M (USB_H_XFERCOMPL4_V << USB_H_XFERCOMPL4_S) 5637 #define USB_H_XFERCOMPL4_V 0x00000001 5638 #define USB_H_XFERCOMPL4_S 0 5639 /** USB_H_CHHLTD4 : R/W1C; bitpos: [1]; default: 0; 5640 * 1'b0: Channel not halted 5641 * 1'b1: Channel Halted 5642 */ 5643 #define USB_H_CHHLTD4 (BIT(1)) 5644 #define USB_H_CHHLTD4_M (USB_H_CHHLTD4_V << USB_H_CHHLTD4_S) 5645 #define USB_H_CHHLTD4_V 0x00000001 5646 #define USB_H_CHHLTD4_S 1 5647 /** USB_H_AHBERR4 : R/W1C; bitpos: [2]; default: 0; 5648 * 1'b0: No AHB error 5649 * 1'b1: AHB error during AHB read/write 5650 */ 5651 #define USB_H_AHBERR4 (BIT(2)) 5652 #define USB_H_AHBERR4_M (USB_H_AHBERR4_V << USB_H_AHBERR4_S) 5653 #define USB_H_AHBERR4_V 0x00000001 5654 #define USB_H_AHBERR4_S 2 5655 /** USB_H_STALL4 : R/W1C; bitpos: [3]; default: 0; 5656 * 1'b0: No Stall Response Received Interrupt 5657 * 1'b1: Stall Response Received Interrupt 5658 */ 5659 #define USB_H_STALL4 (BIT(3)) 5660 #define USB_H_STALL4_M (USB_H_STALL4_V << USB_H_STALL4_S) 5661 #define USB_H_STALL4_V 0x00000001 5662 #define USB_H_STALL4_S 3 5663 /** USB_H_NACK4 : R/W1C; bitpos: [4]; default: 0; 5664 * 1'b0: No NAK Response Received Interrupt 5665 * 1'b1: NAK Response Received Interrupt 5666 */ 5667 #define USB_H_NACK4 (BIT(4)) 5668 #define USB_H_NACK4_M (USB_H_NACK4_V << USB_H_NACK4_S) 5669 #define USB_H_NACK4_V 0x00000001 5670 #define USB_H_NACK4_S 4 5671 /** USB_H_ACK4 : R/W1C; bitpos: [5]; default: 0; 5672 * 1'b0: No ACK Response Received or Transmitted Interrupt 5673 * 1'b1: ACK Response Received or Transmitted Interrup 5674 */ 5675 #define USB_H_ACK4 (BIT(5)) 5676 #define USB_H_ACK4_M (USB_H_ACK4_V << USB_H_ACK4_S) 5677 #define USB_H_ACK4_V 0x00000001 5678 #define USB_H_ACK4_S 5 5679 /** USB_H_NYET4 : R/W1C; bitpos: [6]; default: 0; 5680 * 1'b0: No NYET Response Received Interrupt 5681 * 1'b1: NYET Response Received Interrupt 5682 */ 5683 #define USB_H_NYET4 (BIT(6)) 5684 #define USB_H_NYET4_M (USB_H_NYET4_V << USB_H_NYET4_S) 5685 #define USB_H_NYET4_V 0x00000001 5686 #define USB_H_NYET4_S 6 5687 /** USB_H_XACTERR4 : R/W1C; bitpos: [7]; default: 0; 5688 * Indicates one of the following errors occurred on the USB: 5689 * CRC check failure 5690 * Timeout 5691 * Bit stuff error 5692 * False EOP 5693 */ 5694 #define USB_H_XACTERR4 (BIT(7)) 5695 #define USB_H_XACTERR4_M (USB_H_XACTERR4_V << USB_H_XACTERR4_S) 5696 #define USB_H_XACTERR4_V 0x00000001 5697 #define USB_H_XACTERR4_S 7 5698 /** USB_H_BBLERR4 : R/W1C; bitpos: [8]; default: 0; 5699 * 1'b0: No Babble Error 5700 * 1'b1: Babble Error 5701 */ 5702 #define USB_H_BBLERR4 (BIT(8)) 5703 #define USB_H_BBLERR4_M (USB_H_BBLERR4_V << USB_H_BBLERR4_S) 5704 #define USB_H_BBLERR4_V 0x00000001 5705 #define USB_H_BBLERR4_S 8 5706 /** USB_H_FRMOVRUN4 : R/W1C; bitpos: [9]; default: 0; 5707 * 1'b0: No Frame Overrun 5708 * 1'b1: Frame Overrun 5709 */ 5710 #define USB_H_FRMOVRUN4 (BIT(9)) 5711 #define USB_H_FRMOVRUN4_M (USB_H_FRMOVRUN4_V << USB_H_FRMOVRUN4_S) 5712 #define USB_H_FRMOVRUN4_V 0x00000001 5713 #define USB_H_FRMOVRUN4_S 9 5714 /** USB_H_DATATGLERR4 : R/W1C; bitpos: [10]; default: 0; 5715 * 1'b0: No Data Toggle Error 5716 * 1'b1: Data Toggle Error 5717 */ 5718 #define USB_H_DATATGLERR4 (BIT(10)) 5719 #define USB_H_DATATGLERR4_M (USB_H_DATATGLERR4_V << USB_H_DATATGLERR4_S) 5720 #define USB_H_DATATGLERR4_V 0x00000001 5721 #define USB_H_DATATGLERR4_S 10 5722 /** USB_H_BNAINTR4 : R/W1C; bitpos: [11]; default: 0; 5723 * 1'b0: No BNA Interrupt 5724 * 1'b1: BNA Interrupt 5725 */ 5726 #define USB_H_BNAINTR4 (BIT(11)) 5727 #define USB_H_BNAINTR4_M (USB_H_BNAINTR4_V << USB_H_BNAINTR4_S) 5728 #define USB_H_BNAINTR4_V 0x00000001 5729 #define USB_H_BNAINTR4_S 11 5730 /** USB_H_XCS_XACT_ERR4 : R/W1C; bitpos: [12]; default: 0; 5731 * 1'b0: No Excessive Transaction Error 5732 * 1'b1: Excessive Transaction Error 5733 */ 5734 #define USB_H_XCS_XACT_ERR4 (BIT(12)) 5735 #define USB_H_XCS_XACT_ERR4_M (USB_H_XCS_XACT_ERR4_V << USB_H_XCS_XACT_ERR4_S) 5736 #define USB_H_XCS_XACT_ERR4_V 0x00000001 5737 #define USB_H_XCS_XACT_ERR4_S 12 5738 /** USB_H_DESC_LST_ROLLINTR4 : R/W1C; bitpos: [13]; default: 0; 5739 * 1'b0: No Descriptor rollover interrupt 5740 * 1'b1: Descriptor rollover interrupt 5741 */ 5742 #define USB_H_DESC_LST_ROLLINTR4 (BIT(13)) 5743 #define USB_H_DESC_LST_ROLLINTR4_M (USB_H_DESC_LST_ROLLINTR4_V << USB_H_DESC_LST_ROLLINTR4_S) 5744 #define USB_H_DESC_LST_ROLLINTR4_V 0x00000001 5745 #define USB_H_DESC_LST_ROLLINTR4_S 13 5746 5747 5748 /** USB_HCINTMSK4_REG register 5749 * Host Channel 4 Interrupt Mask Register 5750 */ 5751 #define USB_HCINTMSK4_REG (SOC_DPORT_USB_BASE + 0x58c) 5752 /** USB_H_XFERCOMPLMSK4 : R/W; bitpos: [0]; default: 0; 5753 * 1'b0: Transfer Completed Mask 5754 * 1'b1: No Transfer Completed Mask 5755 */ 5756 #define USB_H_XFERCOMPLMSK4 (BIT(0)) 5757 #define USB_H_XFERCOMPLMSK4_M (USB_H_XFERCOMPLMSK4_V << USB_H_XFERCOMPLMSK4_S) 5758 #define USB_H_XFERCOMPLMSK4_V 0x00000001 5759 #define USB_H_XFERCOMPLMSK4_S 0 5760 /** USB_H_CHHLTDMSK4 : R/W; bitpos: [1]; default: 0; 5761 * 1'b0: Channel Halted Mask 5762 * 1'b1: No Channel Halted Mask 5763 */ 5764 #define USB_H_CHHLTDMSK4 (BIT(1)) 5765 #define USB_H_CHHLTDMSK4_M (USB_H_CHHLTDMSK4_V << USB_H_CHHLTDMSK4_S) 5766 #define USB_H_CHHLTDMSK4_V 0x00000001 5767 #define USB_H_CHHLTDMSK4_S 1 5768 /** USB_H_AHBERRMSK4 : R/W; bitpos: [2]; default: 0; 5769 * 1'b0: AHB Error Mask 5770 * 1'b1: No AHB Error Mask 5771 */ 5772 #define USB_H_AHBERRMSK4 (BIT(2)) 5773 #define USB_H_AHBERRMSK4_M (USB_H_AHBERRMSK4_V << USB_H_AHBERRMSK4_S) 5774 #define USB_H_AHBERRMSK4_V 0x00000001 5775 #define USB_H_AHBERRMSK4_S 2 5776 /** USB_H_STALLMSK4 : R/W; bitpos: [3]; default: 0; 5777 * 1'b0: Mask STALL Response Received Interrupt 5778 * 1'b1: No STALL Response Received Interrupt Mask 5779 */ 5780 #define USB_H_STALLMSK4 (BIT(3)) 5781 #define USB_H_STALLMSK4_M (USB_H_STALLMSK4_V << USB_H_STALLMSK4_S) 5782 #define USB_H_STALLMSK4_V 0x00000001 5783 #define USB_H_STALLMSK4_S 3 5784 /** USB_H_NAKMSK4 : R/W; bitpos: [4]; default: 0; 5785 * 1'b0: Mask NAK Response Received Interrupt 5786 * 1'b1: No NAK Response Received Interrupt Mask 5787 */ 5788 #define USB_H_NAKMSK4 (BIT(4)) 5789 #define USB_H_NAKMSK4_M (USB_H_NAKMSK4_V << USB_H_NAKMSK4_S) 5790 #define USB_H_NAKMSK4_V 0x00000001 5791 #define USB_H_NAKMSK4_S 4 5792 /** USB_H_ACKMSK4 : R/W; bitpos: [5]; default: 0; 5793 * 1'b0: Mask ACK Response Received/Transmitted Interrupt 5794 * 1'b1: No ACK Response Received/Transmitted Interrupt Mask 5795 */ 5796 #define USB_H_ACKMSK4 (BIT(5)) 5797 #define USB_H_ACKMSK4_M (USB_H_ACKMSK4_V << USB_H_ACKMSK4_S) 5798 #define USB_H_ACKMSK4_V 0x00000001 5799 #define USB_H_ACKMSK4_S 5 5800 /** USB_H_NYETMSK4 : R/W; bitpos: [6]; default: 0; 5801 * 1'b0: Mask NYET Response Received Interrupt 5802 * 1'b1: No NYET Response Received Interrupt Mask 5803 */ 5804 #define USB_H_NYETMSK4 (BIT(6)) 5805 #define USB_H_NYETMSK4_M (USB_H_NYETMSK4_V << USB_H_NYETMSK4_S) 5806 #define USB_H_NYETMSK4_V 0x00000001 5807 #define USB_H_NYETMSK4_S 6 5808 /** USB_H_XACTERRMSK4 : R/W; bitpos: [7]; default: 0; 5809 * 1'b0: Mask Transaction Error 5810 * 1'b1: No Transaction Error Mask 5811 */ 5812 #define USB_H_XACTERRMSK4 (BIT(7)) 5813 #define USB_H_XACTERRMSK4_M (USB_H_XACTERRMSK4_V << USB_H_XACTERRMSK4_S) 5814 #define USB_H_XACTERRMSK4_V 0x00000001 5815 #define USB_H_XACTERRMSK4_S 7 5816 /** USB_H_BBLERRMSK4 : R/W; bitpos: [8]; default: 0; 5817 * Babble Error Mask 5818 * 1'b0: Mask Babble Error 5819 * 1'b1: No Babble Error Mask 5820 */ 5821 #define USB_H_BBLERRMSK4 (BIT(8)) 5822 #define USB_H_BBLERRMSK4_M (USB_H_BBLERRMSK4_V << USB_H_BBLERRMSK4_S) 5823 #define USB_H_BBLERRMSK4_V 0x00000001 5824 #define USB_H_BBLERRMSK4_S 8 5825 /** USB_H_FRMOVRUNMSK4 : R/W; bitpos: [9]; default: 0; 5826 * Frame Overrun Mask 5827 * 0x0 (MASK): Mask Overrun Mask 5828 * 0x1 (NOMASK): No Frame Overrun Mask 5829 */ 5830 #define USB_H_FRMOVRUNMSK4 (BIT(9)) 5831 #define USB_H_FRMOVRUNMSK4_M (USB_H_FRMOVRUNMSK4_V << USB_H_FRMOVRUNMSK4_S) 5832 #define USB_H_FRMOVRUNMSK4_V 0x00000001 5833 #define USB_H_FRMOVRUNMSK4_S 9 5834 /** USB_H_DATATGLERRMSK4 : R/W; bitpos: [10]; default: 0; 5835 * Data Toggle Error Mask n scatter/gather DMA mode for host 5836 * 1'b0: Mask Data Toggle Error 5837 * 1'b1: No Data Toggle Error Mask 5838 */ 5839 #define USB_H_DATATGLERRMSK4 (BIT(10)) 5840 #define USB_H_DATATGLERRMSK4_M (USB_H_DATATGLERRMSK4_V << USB_H_DATATGLERRMSK4_S) 5841 #define USB_H_DATATGLERRMSK4_V 0x00000001 5842 #define USB_H_DATATGLERRMSK4_S 10 5843 /** USB_H_BNAINTRMSK4 : R/W; bitpos: [11]; default: 0; 5844 * BNA (Buffer Not Available) Interrupt mask register 5845 * 1'b0: BNA Interrupt Masked 5846 * 1'b1: BNA Interrupt not masked 5847 */ 5848 #define USB_H_BNAINTRMSK4 (BIT(11)) 5849 #define USB_H_BNAINTRMSK4_M (USB_H_BNAINTRMSK4_V << USB_H_BNAINTRMSK4_S) 5850 #define USB_H_BNAINTRMSK4_V 0x00000001 5851 #define USB_H_BNAINTRMSK4_S 11 5852 /** USB_H_DESC_LST_ROLLINTRMSK4 : R/W; bitpos: [13]; default: 0; 5853 * Descriptor List rollover interrupt Mask 5854 * 1'b0: Descriptor Rollover Interrupt Mask 5855 * 1'b1: Descriptor Rollover Interrupt not masked 5856 */ 5857 #define USB_H_DESC_LST_ROLLINTRMSK4 (BIT(13)) 5858 #define USB_H_DESC_LST_ROLLINTRMSK4_M (USB_H_DESC_LST_ROLLINTRMSK4_V << USB_H_DESC_LST_ROLLINTRMSK4_S) 5859 #define USB_H_DESC_LST_ROLLINTRMSK4_V 0x00000001 5860 #define USB_H_DESC_LST_ROLLINTRMSK4_S 13 5861 5862 5863 /** USB_HCINT5_REG register 5864 * Host Channel 5 Interrupt Register 5865 */ 5866 #define USB_HCINT5_REG (SOC_DPORT_USB_BASE + 0x5a8) 5867 /** USB_H_XFERCOMPL5 : R/W1C; bitpos: [0]; default: 0; 5868 * 1'b0: Transfer in progress or No Active Transfer 5869 * 1'b1: Transfer completed normally without any errors 5870 */ 5871 #define USB_H_XFERCOMPL5 (BIT(0)) 5872 #define USB_H_XFERCOMPL5_M (USB_H_XFERCOMPL5_V << USB_H_XFERCOMPL5_S) 5873 #define USB_H_XFERCOMPL5_V 0x00000001 5874 #define USB_H_XFERCOMPL5_S 0 5875 /** USB_H_CHHLTD5 : R/W1C; bitpos: [1]; default: 0; 5876 * 1'b0: Channel not halted 5877 * 1'b1: Channel Halted 5878 */ 5879 #define USB_H_CHHLTD5 (BIT(1)) 5880 #define USB_H_CHHLTD5_M (USB_H_CHHLTD5_V << USB_H_CHHLTD5_S) 5881 #define USB_H_CHHLTD5_V 0x00000001 5882 #define USB_H_CHHLTD5_S 1 5883 /** USB_H_AHBERR5 : R/W1C; bitpos: [2]; default: 0; 5884 * 1'b0: No AHB error 5885 * 1'b1: AHB error during AHB read/write 5886 */ 5887 #define USB_H_AHBERR5 (BIT(2)) 5888 #define USB_H_AHBERR5_M (USB_H_AHBERR5_V << USB_H_AHBERR5_S) 5889 #define USB_H_AHBERR5_V 0x00000001 5890 #define USB_H_AHBERR5_S 2 5891 /** USB_H_STALL5 : R/W1C; bitpos: [3]; default: 0; 5892 * 1'b0: No Stall Response Received Interrupt 5893 * 1'b1: Stall Response Received Interrupt 5894 */ 5895 #define USB_H_STALL5 (BIT(3)) 5896 #define USB_H_STALL5_M (USB_H_STALL5_V << USB_H_STALL5_S) 5897 #define USB_H_STALL5_V 0x00000001 5898 #define USB_H_STALL5_S 3 5899 /** USB_H_NACK5 : R/W1C; bitpos: [4]; default: 0; 5900 * 1'b0: No NAK Response Received Interrupt 5901 * 1'b1: NAK Response Received Interrupt 5902 */ 5903 #define USB_H_NACK5 (BIT(4)) 5904 #define USB_H_NACK5_M (USB_H_NACK5_V << USB_H_NACK5_S) 5905 #define USB_H_NACK5_V 0x00000001 5906 #define USB_H_NACK5_S 4 5907 /** USB_H_ACK5 : R/W1C; bitpos: [5]; default: 0; 5908 * 1'b0: No ACK Response Received or Transmitted Interrupt 5909 * 1'b1: ACK Response Received or Transmitted Interrup 5910 */ 5911 #define USB_H_ACK5 (BIT(5)) 5912 #define USB_H_ACK5_M (USB_H_ACK5_V << USB_H_ACK5_S) 5913 #define USB_H_ACK5_V 0x00000001 5914 #define USB_H_ACK5_S 5 5915 /** USB_H_NYET5 : R/W1C; bitpos: [6]; default: 0; 5916 * 1'b0: No NYET Response Received Interrupt 5917 * 1'b1: NYET Response Received Interrupt 5918 */ 5919 #define USB_H_NYET5 (BIT(6)) 5920 #define USB_H_NYET5_M (USB_H_NYET5_V << USB_H_NYET5_S) 5921 #define USB_H_NYET5_V 0x00000001 5922 #define USB_H_NYET5_S 6 5923 /** USB_H_XACTERR5 : R/W1C; bitpos: [7]; default: 0; 5924 * Indicates one of the following errors occurred on the USB: 5925 * CRC check failure 5926 * Timeout 5927 * Bit stuff error 5928 * False EOP 5929 */ 5930 #define USB_H_XACTERR5 (BIT(7)) 5931 #define USB_H_XACTERR5_M (USB_H_XACTERR5_V << USB_H_XACTERR5_S) 5932 #define USB_H_XACTERR5_V 0x00000001 5933 #define USB_H_XACTERR5_S 7 5934 /** USB_H_BBLERR5 : R/W1C; bitpos: [8]; default: 0; 5935 * 1'b0: No Babble Error 5936 * 1'b1: Babble Error 5937 */ 5938 #define USB_H_BBLERR5 (BIT(8)) 5939 #define USB_H_BBLERR5_M (USB_H_BBLERR5_V << USB_H_BBLERR5_S) 5940 #define USB_H_BBLERR5_V 0x00000001 5941 #define USB_H_BBLERR5_S 8 5942 /** USB_H_FRMOVRUN5 : R/W1C; bitpos: [9]; default: 0; 5943 * 1'b0: No Frame Overrun 5944 * 1'b1: Frame Overrun 5945 */ 5946 #define USB_H_FRMOVRUN5 (BIT(9)) 5947 #define USB_H_FRMOVRUN5_M (USB_H_FRMOVRUN5_V << USB_H_FRMOVRUN5_S) 5948 #define USB_H_FRMOVRUN5_V 0x00000001 5949 #define USB_H_FRMOVRUN5_S 9 5950 /** USB_H_DATATGLERR5 : R/W1C; bitpos: [10]; default: 0; 5951 * 1'b0: No Data Toggle Error 5952 * 1'b1: Data Toggle Error 5953 */ 5954 #define USB_H_DATATGLERR5 (BIT(10)) 5955 #define USB_H_DATATGLERR5_M (USB_H_DATATGLERR5_V << USB_H_DATATGLERR5_S) 5956 #define USB_H_DATATGLERR5_V 0x00000001 5957 #define USB_H_DATATGLERR5_S 10 5958 /** USB_H_BNAINTR5 : R/W1C; bitpos: [11]; default: 0; 5959 * 1'b0: No BNA Interrupt 5960 * 1'b1: BNA Interrupt 5961 */ 5962 #define USB_H_BNAINTR5 (BIT(11)) 5963 #define USB_H_BNAINTR5_M (USB_H_BNAINTR5_V << USB_H_BNAINTR5_S) 5964 #define USB_H_BNAINTR5_V 0x00000001 5965 #define USB_H_BNAINTR5_S 11 5966 /** USB_H_XCS_XACT_ERR5 : R/W1C; bitpos: [12]; default: 0; 5967 * 1'b0: No Excessive Transaction Error 5968 * 1'b1: Excessive Transaction Error 5969 */ 5970 #define USB_H_XCS_XACT_ERR5 (BIT(12)) 5971 #define USB_H_XCS_XACT_ERR5_M (USB_H_XCS_XACT_ERR5_V << USB_H_XCS_XACT_ERR5_S) 5972 #define USB_H_XCS_XACT_ERR5_V 0x00000001 5973 #define USB_H_XCS_XACT_ERR5_S 12 5974 /** USB_H_DESC_LST_ROLLINTR5 : R/W1C; bitpos: [13]; default: 0; 5975 * 1'b0: No Descriptor rollover interrupt 5976 * 1'b1: Descriptor rollover interrupt 5977 */ 5978 #define USB_H_DESC_LST_ROLLINTR5 (BIT(13)) 5979 #define USB_H_DESC_LST_ROLLINTR5_M (USB_H_DESC_LST_ROLLINTR5_V << USB_H_DESC_LST_ROLLINTR5_S) 5980 #define USB_H_DESC_LST_ROLLINTR5_V 0x00000001 5981 #define USB_H_DESC_LST_ROLLINTR5_S 13 5982 5983 5984 /** USB_HCINTMSK5_REG register 5985 * Host Channel 5 Interrupt Mask Register 5986 */ 5987 #define USB_HCINTMSK5_REG (SOC_DPORT_USB_BASE + 0x5ac) 5988 /** USB_H_XFERCOMPLMSK5 : R/W; bitpos: [0]; default: 0; 5989 * 1'b0: Transfer Completed Mask 5990 * 1'b1: No Transfer Completed Mask 5991 */ 5992 #define USB_H_XFERCOMPLMSK5 (BIT(0)) 5993 #define USB_H_XFERCOMPLMSK5_M (USB_H_XFERCOMPLMSK5_V << USB_H_XFERCOMPLMSK5_S) 5994 #define USB_H_XFERCOMPLMSK5_V 0x00000001 5995 #define USB_H_XFERCOMPLMSK5_S 0 5996 /** USB_H_CHHLTDMSK5 : R/W; bitpos: [1]; default: 0; 5997 * 1'b0: Channel Halted Mask 5998 * 1'b1: No Channel Halted Mask 5999 */ 6000 #define USB_H_CHHLTDMSK5 (BIT(1)) 6001 #define USB_H_CHHLTDMSK5_M (USB_H_CHHLTDMSK5_V << USB_H_CHHLTDMSK5_S) 6002 #define USB_H_CHHLTDMSK5_V 0x00000001 6003 #define USB_H_CHHLTDMSK5_S 1 6004 /** USB_H_AHBERRMSK5 : R/W; bitpos: [2]; default: 0; 6005 * 1'b0: AHB Error Mask 6006 * 1'b1: No AHB Error Mask 6007 */ 6008 #define USB_H_AHBERRMSK5 (BIT(2)) 6009 #define USB_H_AHBERRMSK5_M (USB_H_AHBERRMSK5_V << USB_H_AHBERRMSK5_S) 6010 #define USB_H_AHBERRMSK5_V 0x00000001 6011 #define USB_H_AHBERRMSK5_S 2 6012 /** USB_H_STALLMSK5 : R/W; bitpos: [3]; default: 0; 6013 * 1'b0: Mask STALL Response Received Interrupt 6014 * 1'b1: No STALL Response Received Interrupt Mask 6015 */ 6016 #define USB_H_STALLMSK5 (BIT(3)) 6017 #define USB_H_STALLMSK5_M (USB_H_STALLMSK5_V << USB_H_STALLMSK5_S) 6018 #define USB_H_STALLMSK5_V 0x00000001 6019 #define USB_H_STALLMSK5_S 3 6020 /** USB_H_NAKMSK5 : R/W; bitpos: [4]; default: 0; 6021 * 1'b0: Mask NAK Response Received Interrupt 6022 * 1'b1: No NAK Response Received Interrupt Mask 6023 */ 6024 #define USB_H_NAKMSK5 (BIT(4)) 6025 #define USB_H_NAKMSK5_M (USB_H_NAKMSK5_V << USB_H_NAKMSK5_S) 6026 #define USB_H_NAKMSK5_V 0x00000001 6027 #define USB_H_NAKMSK5_S 4 6028 /** USB_H_ACKMSK5 : R/W; bitpos: [5]; default: 0; 6029 * 1'b0: Mask ACK Response Received/Transmitted Interrupt 6030 * 1'b1: No ACK Response Received/Transmitted Interrupt Mask 6031 */ 6032 #define USB_H_ACKMSK5 (BIT(5)) 6033 #define USB_H_ACKMSK5_M (USB_H_ACKMSK5_V << USB_H_ACKMSK5_S) 6034 #define USB_H_ACKMSK5_V 0x00000001 6035 #define USB_H_ACKMSK5_S 5 6036 /** USB_H_NYETMSK5 : R/W; bitpos: [6]; default: 0; 6037 * 1'b0: Mask NYET Response Received Interrupt 6038 * 1'b1: No NYET Response Received Interrupt Mask 6039 */ 6040 #define USB_H_NYETMSK5 (BIT(6)) 6041 #define USB_H_NYETMSK5_M (USB_H_NYETMSK5_V << USB_H_NYETMSK5_S) 6042 #define USB_H_NYETMSK5_V 0x00000001 6043 #define USB_H_NYETMSK5_S 6 6044 /** USB_H_XACTERRMSK5 : R/W; bitpos: [7]; default: 0; 6045 * 1'b0: Mask Transaction Error 6046 * 1'b1: No Transaction Error Mask 6047 */ 6048 #define USB_H_XACTERRMSK5 (BIT(7)) 6049 #define USB_H_XACTERRMSK5_M (USB_H_XACTERRMSK5_V << USB_H_XACTERRMSK5_S) 6050 #define USB_H_XACTERRMSK5_V 0x00000001 6051 #define USB_H_XACTERRMSK5_S 7 6052 /** USB_H_BBLERRMSK5 : R/W; bitpos: [8]; default: 0; 6053 * Babble Error Mask 6054 * 1'b0: Mask Babble Error 6055 * 1'b1: No Babble Error Mask 6056 */ 6057 #define USB_H_BBLERRMSK5 (BIT(8)) 6058 #define USB_H_BBLERRMSK5_M (USB_H_BBLERRMSK5_V << USB_H_BBLERRMSK5_S) 6059 #define USB_H_BBLERRMSK5_V 0x00000001 6060 #define USB_H_BBLERRMSK5_S 8 6061 /** USB_H_FRMOVRUNMSK5 : R/W; bitpos: [9]; default: 0; 6062 * Frame Overrun Mask 6063 * 0x0 (MASK): Mask Overrun Mask 6064 * 0x1 (NOMASK): No Frame Overrun Mask 6065 */ 6066 #define USB_H_FRMOVRUNMSK5 (BIT(9)) 6067 #define USB_H_FRMOVRUNMSK5_M (USB_H_FRMOVRUNMSK5_V << USB_H_FRMOVRUNMSK5_S) 6068 #define USB_H_FRMOVRUNMSK5_V 0x00000001 6069 #define USB_H_FRMOVRUNMSK5_S 9 6070 /** USB_H_DATATGLERRMSK5 : R/W; bitpos: [10]; default: 0; 6071 * Data Toggle Error Mask n scatter/gather DMA mode for host 6072 * 1'b0: Mask Data Toggle Error 6073 * 1'b1: No Data Toggle Error Mask 6074 */ 6075 #define USB_H_DATATGLERRMSK5 (BIT(10)) 6076 #define USB_H_DATATGLERRMSK5_M (USB_H_DATATGLERRMSK5_V << USB_H_DATATGLERRMSK5_S) 6077 #define USB_H_DATATGLERRMSK5_V 0x00000001 6078 #define USB_H_DATATGLERRMSK5_S 10 6079 /** USB_H_BNAINTRMSK5 : R/W; bitpos: [11]; default: 0; 6080 * BNA (Buffer Not Available) Interrupt mask register 6081 * 1'b0: BNA Interrupt Masked 6082 * 1'b1: BNA Interrupt not masked 6083 */ 6084 #define USB_H_BNAINTRMSK5 (BIT(11)) 6085 #define USB_H_BNAINTRMSK5_M (USB_H_BNAINTRMSK5_V << USB_H_BNAINTRMSK5_S) 6086 #define USB_H_BNAINTRMSK5_V 0x00000001 6087 #define USB_H_BNAINTRMSK5_S 11 6088 /** USB_H_DESC_LST_ROLLINTRMSK5 : R/W; bitpos: [13]; default: 0; 6089 * Descriptor List rollover interrupt Mask 6090 * 1'b0: Descriptor Rollover Interrupt Mask 6091 * 1'b1: Descriptor Rollover Interrupt not masked 6092 */ 6093 #define USB_H_DESC_LST_ROLLINTRMSK5 (BIT(13)) 6094 #define USB_H_DESC_LST_ROLLINTRMSK5_M (USB_H_DESC_LST_ROLLINTRMSK5_V << USB_H_DESC_LST_ROLLINTRMSK5_S) 6095 #define USB_H_DESC_LST_ROLLINTRMSK5_V 0x00000001 6096 #define USB_H_DESC_LST_ROLLINTRMSK5_S 13 6097 6098 6099 /** USB_HCINT6_REG register 6100 * Host Channel 6 Interrupt Register 6101 */ 6102 #define USB_HCINT6_REG (SOC_DPORT_USB_BASE + 0x5c8) 6103 /** USB_H_XFERCOMPL6 : R/W1C; bitpos: [0]; default: 0; 6104 * 1'b0: Transfer in progress or No Active Transfer 6105 * 1'b1: Transfer completed normally without any errors 6106 */ 6107 #define USB_H_XFERCOMPL6 (BIT(0)) 6108 #define USB_H_XFERCOMPL6_M (USB_H_XFERCOMPL6_V << USB_H_XFERCOMPL6_S) 6109 #define USB_H_XFERCOMPL6_V 0x00000001 6110 #define USB_H_XFERCOMPL6_S 0 6111 /** USB_H_CHHLTD6 : R/W1C; bitpos: [1]; default: 0; 6112 * 1'b0: Channel not halted 6113 * 1'b1: Channel Halted 6114 */ 6115 #define USB_H_CHHLTD6 (BIT(1)) 6116 #define USB_H_CHHLTD6_M (USB_H_CHHLTD6_V << USB_H_CHHLTD6_S) 6117 #define USB_H_CHHLTD6_V 0x00000001 6118 #define USB_H_CHHLTD6_S 1 6119 /** USB_H_AHBERR6 : R/W1C; bitpos: [2]; default: 0; 6120 * 1'b0: No AHB error 6121 * 1'b1: AHB error during AHB read/write 6122 */ 6123 #define USB_H_AHBERR6 (BIT(2)) 6124 #define USB_H_AHBERR6_M (USB_H_AHBERR6_V << USB_H_AHBERR6_S) 6125 #define USB_H_AHBERR6_V 0x00000001 6126 #define USB_H_AHBERR6_S 2 6127 /** USB_H_STALL6 : R/W1C; bitpos: [3]; default: 0; 6128 * 1'b0: No Stall Response Received Interrupt 6129 * 1'b1: Stall Response Received Interrupt 6130 */ 6131 #define USB_H_STALL6 (BIT(3)) 6132 #define USB_H_STALL6_M (USB_H_STALL6_V << USB_H_STALL6_S) 6133 #define USB_H_STALL6_V 0x00000001 6134 #define USB_H_STALL6_S 3 6135 /** USB_H_NACK6 : R/W1C; bitpos: [4]; default: 0; 6136 * 1'b0: No NAK Response Received Interrupt 6137 * 1'b1: NAK Response Received Interrupt 6138 */ 6139 #define USB_H_NACK6 (BIT(4)) 6140 #define USB_H_NACK6_M (USB_H_NACK6_V << USB_H_NACK6_S) 6141 #define USB_H_NACK6_V 0x00000001 6142 #define USB_H_NACK6_S 4 6143 /** USB_H_ACK6 : R/W1C; bitpos: [5]; default: 0; 6144 * 1'b0: No ACK Response Received or Transmitted Interrupt 6145 * 1'b1: ACK Response Received or Transmitted Interrup 6146 */ 6147 #define USB_H_ACK6 (BIT(5)) 6148 #define USB_H_ACK6_M (USB_H_ACK6_V << USB_H_ACK6_S) 6149 #define USB_H_ACK6_V 0x00000001 6150 #define USB_H_ACK6_S 5 6151 /** USB_H_NYET6 : R/W1C; bitpos: [6]; default: 0; 6152 * 1'b0: No NYET Response Received Interrupt 6153 * 1'b1: NYET Response Received Interrupt 6154 */ 6155 #define USB_H_NYET6 (BIT(6)) 6156 #define USB_H_NYET6_M (USB_H_NYET6_V << USB_H_NYET6_S) 6157 #define USB_H_NYET6_V 0x00000001 6158 #define USB_H_NYET6_S 6 6159 /** USB_H_XACTERR6 : R/W1C; bitpos: [7]; default: 0; 6160 * Indicates one of the following errors occurred on the USB: 6161 * CRC check failure 6162 * Timeout 6163 * Bit stuff error 6164 * False EOP 6165 */ 6166 #define USB_H_XACTERR6 (BIT(7)) 6167 #define USB_H_XACTERR6_M (USB_H_XACTERR6_V << USB_H_XACTERR6_S) 6168 #define USB_H_XACTERR6_V 0x00000001 6169 #define USB_H_XACTERR6_S 7 6170 /** USB_H_BBLERR6 : R/W1C; bitpos: [8]; default: 0; 6171 * 1'b0: No Babble Error 6172 * 1'b1: Babble Error 6173 */ 6174 #define USB_H_BBLERR6 (BIT(8)) 6175 #define USB_H_BBLERR6_M (USB_H_BBLERR6_V << USB_H_BBLERR6_S) 6176 #define USB_H_BBLERR6_V 0x00000001 6177 #define USB_H_BBLERR6_S 8 6178 /** USB_H_FRMOVRUN6 : R/W1C; bitpos: [9]; default: 0; 6179 * 1'b0: No Frame Overrun 6180 * 1'b1: Frame Overrun 6181 */ 6182 #define USB_H_FRMOVRUN6 (BIT(9)) 6183 #define USB_H_FRMOVRUN6_M (USB_H_FRMOVRUN6_V << USB_H_FRMOVRUN6_S) 6184 #define USB_H_FRMOVRUN6_V 0x00000001 6185 #define USB_H_FRMOVRUN6_S 9 6186 /** USB_H_DATATGLERR6 : R/W1C; bitpos: [10]; default: 0; 6187 * 1'b0: No Data Toggle Error 6188 * 1'b1: Data Toggle Error 6189 */ 6190 #define USB_H_DATATGLERR6 (BIT(10)) 6191 #define USB_H_DATATGLERR6_M (USB_H_DATATGLERR6_V << USB_H_DATATGLERR6_S) 6192 #define USB_H_DATATGLERR6_V 0x00000001 6193 #define USB_H_DATATGLERR6_S 10 6194 /** USB_H_BNAINTR6 : R/W1C; bitpos: [11]; default: 0; 6195 * 1'b0: No BNA Interrupt 6196 * 1'b1: BNA Interrupt 6197 */ 6198 #define USB_H_BNAINTR6 (BIT(11)) 6199 #define USB_H_BNAINTR6_M (USB_H_BNAINTR6_V << USB_H_BNAINTR6_S) 6200 #define USB_H_BNAINTR6_V 0x00000001 6201 #define USB_H_BNAINTR6_S 11 6202 /** USB_H_XCS_XACT_ERR6 : R/W1C; bitpos: [12]; default: 0; 6203 * 1'b0: No Excessive Transaction Error 6204 * 1'b1: Excessive Transaction Error 6205 */ 6206 #define USB_H_XCS_XACT_ERR6 (BIT(12)) 6207 #define USB_H_XCS_XACT_ERR6_M (USB_H_XCS_XACT_ERR6_V << USB_H_XCS_XACT_ERR6_S) 6208 #define USB_H_XCS_XACT_ERR6_V 0x00000001 6209 #define USB_H_XCS_XACT_ERR6_S 12 6210 /** USB_H_DESC_LST_ROLLINTR6 : R/W1C; bitpos: [13]; default: 0; 6211 * 1'b0: No Descriptor rollover interrupt 6212 * 1'b1: Descriptor rollover interrupt 6213 */ 6214 #define USB_H_DESC_LST_ROLLINTR6 (BIT(13)) 6215 #define USB_H_DESC_LST_ROLLINTR6_M (USB_H_DESC_LST_ROLLINTR6_V << USB_H_DESC_LST_ROLLINTR6_S) 6216 #define USB_H_DESC_LST_ROLLINTR6_V 0x00000001 6217 #define USB_H_DESC_LST_ROLLINTR6_S 13 6218 6219 6220 /** USB_HCINTMSK6_REG register 6221 * Host Channel 6 Interrupt Mask Register 6222 */ 6223 #define USB_HCINTMSK6_REG (SOC_DPORT_USB_BASE + 0x5cc) 6224 /** USB_H_XFERCOMPLMSK6 : R/W; bitpos: [0]; default: 0; 6225 * 1'b0: Transfer Completed Mask 6226 * 1'b1: No Transfer Completed Mask 6227 */ 6228 #define USB_H_XFERCOMPLMSK6 (BIT(0)) 6229 #define USB_H_XFERCOMPLMSK6_M (USB_H_XFERCOMPLMSK6_V << USB_H_XFERCOMPLMSK6_S) 6230 #define USB_H_XFERCOMPLMSK6_V 0x00000001 6231 #define USB_H_XFERCOMPLMSK6_S 0 6232 /** USB_H_CHHLTDMSK6 : R/W; bitpos: [1]; default: 0; 6233 * 1'b0: Channel Halted Mask 6234 * 1'b1: No Channel Halted Mask 6235 */ 6236 #define USB_H_CHHLTDMSK6 (BIT(1)) 6237 #define USB_H_CHHLTDMSK6_M (USB_H_CHHLTDMSK6_V << USB_H_CHHLTDMSK6_S) 6238 #define USB_H_CHHLTDMSK6_V 0x00000001 6239 #define USB_H_CHHLTDMSK6_S 1 6240 /** USB_H_AHBERRMSK6 : R/W; bitpos: [2]; default: 0; 6241 * 1'b0: AHB Error Mask 6242 * 1'b1: No AHB Error Mask 6243 */ 6244 #define USB_H_AHBERRMSK6 (BIT(2)) 6245 #define USB_H_AHBERRMSK6_M (USB_H_AHBERRMSK6_V << USB_H_AHBERRMSK6_S) 6246 #define USB_H_AHBERRMSK6_V 0x00000001 6247 #define USB_H_AHBERRMSK6_S 2 6248 /** USB_H_STALLMSK6 : R/W; bitpos: [3]; default: 0; 6249 * 1'b0: Mask STALL Response Received Interrupt 6250 * 1'b1: No STALL Response Received Interrupt Mask 6251 */ 6252 #define USB_H_STALLMSK6 (BIT(3)) 6253 #define USB_H_STALLMSK6_M (USB_H_STALLMSK6_V << USB_H_STALLMSK6_S) 6254 #define USB_H_STALLMSK6_V 0x00000001 6255 #define USB_H_STALLMSK6_S 3 6256 /** USB_H_NAKMSK6 : R/W; bitpos: [4]; default: 0; 6257 * 1'b0: Mask NAK Response Received Interrupt 6258 * 1'b1: No NAK Response Received Interrupt Mask 6259 */ 6260 #define USB_H_NAKMSK6 (BIT(4)) 6261 #define USB_H_NAKMSK6_M (USB_H_NAKMSK6_V << USB_H_NAKMSK6_S) 6262 #define USB_H_NAKMSK6_V 0x00000001 6263 #define USB_H_NAKMSK6_S 4 6264 /** USB_H_ACKMSK6 : R/W; bitpos: [5]; default: 0; 6265 * 1'b0: Mask ACK Response Received/Transmitted Interrupt 6266 * 1'b1: No ACK Response Received/Transmitted Interrupt Mask 6267 */ 6268 #define USB_H_ACKMSK6 (BIT(5)) 6269 #define USB_H_ACKMSK6_M (USB_H_ACKMSK6_V << USB_H_ACKMSK6_S) 6270 #define USB_H_ACKMSK6_V 0x00000001 6271 #define USB_H_ACKMSK6_S 5 6272 /** USB_H_NYETMSK6 : R/W; bitpos: [6]; default: 0; 6273 * 1'b0: Mask NYET Response Received Interrupt 6274 * 1'b1: No NYET Response Received Interrupt Mask 6275 */ 6276 #define USB_H_NYETMSK6 (BIT(6)) 6277 #define USB_H_NYETMSK6_M (USB_H_NYETMSK6_V << USB_H_NYETMSK6_S) 6278 #define USB_H_NYETMSK6_V 0x00000001 6279 #define USB_H_NYETMSK6_S 6 6280 /** USB_H_XACTERRMSK6 : R/W; bitpos: [7]; default: 0; 6281 * 1'b0: Mask Transaction Error 6282 * 1'b1: No Transaction Error Mask 6283 */ 6284 #define USB_H_XACTERRMSK6 (BIT(7)) 6285 #define USB_H_XACTERRMSK6_M (USB_H_XACTERRMSK6_V << USB_H_XACTERRMSK6_S) 6286 #define USB_H_XACTERRMSK6_V 0x00000001 6287 #define USB_H_XACTERRMSK6_S 7 6288 /** USB_H_BBLERRMSK6 : R/W; bitpos: [8]; default: 0; 6289 * Babble Error Mask 6290 * 1'b0: Mask Babble Error 6291 * 1'b1: No Babble Error Mask 6292 */ 6293 #define USB_H_BBLERRMSK6 (BIT(8)) 6294 #define USB_H_BBLERRMSK6_M (USB_H_BBLERRMSK6_V << USB_H_BBLERRMSK6_S) 6295 #define USB_H_BBLERRMSK6_V 0x00000001 6296 #define USB_H_BBLERRMSK6_S 8 6297 /** USB_H_FRMOVRUNMSK6 : R/W; bitpos: [9]; default: 0; 6298 * Frame Overrun Mask 6299 * 0x0 (MASK): Mask Overrun Mask 6300 * 0x1 (NOMASK): No Frame Overrun Mask 6301 */ 6302 #define USB_H_FRMOVRUNMSK6 (BIT(9)) 6303 #define USB_H_FRMOVRUNMSK6_M (USB_H_FRMOVRUNMSK6_V << USB_H_FRMOVRUNMSK6_S) 6304 #define USB_H_FRMOVRUNMSK6_V 0x00000001 6305 #define USB_H_FRMOVRUNMSK6_S 9 6306 /** USB_H_DATATGLERRMSK6 : R/W; bitpos: [10]; default: 0; 6307 * Data Toggle Error Mask n scatter/gather DMA mode for host 6308 * 1'b0: Mask Data Toggle Error 6309 * 1'b1: No Data Toggle Error Mask 6310 */ 6311 #define USB_H_DATATGLERRMSK6 (BIT(10)) 6312 #define USB_H_DATATGLERRMSK6_M (USB_H_DATATGLERRMSK6_V << USB_H_DATATGLERRMSK6_S) 6313 #define USB_H_DATATGLERRMSK6_V 0x00000001 6314 #define USB_H_DATATGLERRMSK6_S 10 6315 /** USB_H_BNAINTRMSK6 : R/W; bitpos: [11]; default: 0; 6316 * BNA (Buffer Not Available) Interrupt mask register 6317 * 1'b0: BNA Interrupt Masked 6318 * 1'b1: BNA Interrupt not masked 6319 */ 6320 #define USB_H_BNAINTRMSK6 (BIT(11)) 6321 #define USB_H_BNAINTRMSK6_M (USB_H_BNAINTRMSK6_V << USB_H_BNAINTRMSK6_S) 6322 #define USB_H_BNAINTRMSK6_V 0x00000001 6323 #define USB_H_BNAINTRMSK6_S 11 6324 /** USB_H_DESC_LST_ROLLINTRMSK6 : R/W; bitpos: [13]; default: 0; 6325 * Descriptor List rollover interrupt Mask 6326 * 1'b0: Descriptor Rollover Interrupt Mask 6327 * 1'b1: Descriptor Rollover Interrupt not masked 6328 */ 6329 #define USB_H_DESC_LST_ROLLINTRMSK6 (BIT(13)) 6330 #define USB_H_DESC_LST_ROLLINTRMSK6_M (USB_H_DESC_LST_ROLLINTRMSK6_V << USB_H_DESC_LST_ROLLINTRMSK6_S) 6331 #define USB_H_DESC_LST_ROLLINTRMSK6_V 0x00000001 6332 #define USB_H_DESC_LST_ROLLINTRMSK6_S 13 6333 6334 6335 /** USB_HCINT7_REG register 6336 * Host Channel 7 Interrupt Register 6337 */ 6338 #define USB_HCINT7_REG (SOC_DPORT_USB_BASE + 0x5e8) 6339 /** USB_H_XFERCOMPL7 : R/W1C; bitpos: [0]; default: 0; 6340 * 1'b0: Transfer in progress or No Active Transfer 6341 * 1'b1: Transfer completed normally without any errors 6342 */ 6343 #define USB_H_XFERCOMPL7 (BIT(0)) 6344 #define USB_H_XFERCOMPL7_M (USB_H_XFERCOMPL7_V << USB_H_XFERCOMPL7_S) 6345 #define USB_H_XFERCOMPL7_V 0x00000001 6346 #define USB_H_XFERCOMPL7_S 0 6347 /** USB_H_CHHLTD7 : R/W1C; bitpos: [1]; default: 0; 6348 * 1'b0: Channel not halted 6349 * 1'b1: Channel Halted 6350 */ 6351 #define USB_H_CHHLTD7 (BIT(1)) 6352 #define USB_H_CHHLTD7_M (USB_H_CHHLTD7_V << USB_H_CHHLTD7_S) 6353 #define USB_H_CHHLTD7_V 0x00000001 6354 #define USB_H_CHHLTD7_S 1 6355 /** USB_H_AHBERR7 : R/W1C; bitpos: [2]; default: 0; 6356 * 1'b0: No AHB error 6357 * 1'b1: AHB error during AHB read/write 6358 */ 6359 #define USB_H_AHBERR7 (BIT(2)) 6360 #define USB_H_AHBERR7_M (USB_H_AHBERR7_V << USB_H_AHBERR7_S) 6361 #define USB_H_AHBERR7_V 0x00000001 6362 #define USB_H_AHBERR7_S 2 6363 /** USB_H_STALL7 : R/W1C; bitpos: [3]; default: 0; 6364 * 1'b0: No Stall Response Received Interrupt 6365 * 1'b1: Stall Response Received Interrupt 6366 */ 6367 #define USB_H_STALL7 (BIT(3)) 6368 #define USB_H_STALL7_M (USB_H_STALL7_V << USB_H_STALL7_S) 6369 #define USB_H_STALL7_V 0x00000001 6370 #define USB_H_STALL7_S 3 6371 /** USB_H_NACK7 : R/W1C; bitpos: [4]; default: 0; 6372 * 1'b0: No NAK Response Received Interrupt 6373 * 1'b1: NAK Response Received Interrupt 6374 */ 6375 #define USB_H_NACK7 (BIT(4)) 6376 #define USB_H_NACK7_M (USB_H_NACK7_V << USB_H_NACK7_S) 6377 #define USB_H_NACK7_V 0x00000001 6378 #define USB_H_NACK7_S 4 6379 /** USB_H_ACK7 : R/W1C; bitpos: [5]; default: 0; 6380 * 1'b0: No ACK Response Received or Transmitted Interrupt 6381 * 1'b1: ACK Response Received or Transmitted Interrup 6382 */ 6383 #define USB_H_ACK7 (BIT(5)) 6384 #define USB_H_ACK7_M (USB_H_ACK7_V << USB_H_ACK7_S) 6385 #define USB_H_ACK7_V 0x00000001 6386 #define USB_H_ACK7_S 5 6387 /** USB_H_NYET7 : R/W1C; bitpos: [6]; default: 0; 6388 * 1'b0: No NYET Response Received Interrupt 6389 * 1'b1: NYET Response Received Interrupt 6390 */ 6391 #define USB_H_NYET7 (BIT(6)) 6392 #define USB_H_NYET7_M (USB_H_NYET7_V << USB_H_NYET7_S) 6393 #define USB_H_NYET7_V 0x00000001 6394 #define USB_H_NYET7_S 6 6395 /** USB_H_XACTERR7 : R/W1C; bitpos: [7]; default: 0; 6396 * Indicates one of the following errors occurred on the USB: 6397 * CRC check failure 6398 * Timeout 6399 * Bit stuff error 6400 * False EOP 6401 */ 6402 #define USB_H_XACTERR7 (BIT(7)) 6403 #define USB_H_XACTERR7_M (USB_H_XACTERR7_V << USB_H_XACTERR7_S) 6404 #define USB_H_XACTERR7_V 0x00000001 6405 #define USB_H_XACTERR7_S 7 6406 /** USB_H_BBLERR7 : R/W1C; bitpos: [8]; default: 0; 6407 * 1'b0: No Babble Error 6408 * 1'b1: Babble Error 6409 */ 6410 #define USB_H_BBLERR7 (BIT(8)) 6411 #define USB_H_BBLERR7_M (USB_H_BBLERR7_V << USB_H_BBLERR7_S) 6412 #define USB_H_BBLERR7_V 0x00000001 6413 #define USB_H_BBLERR7_S 8 6414 /** USB_H_FRMOVRUN7 : R/W1C; bitpos: [9]; default: 0; 6415 * 1'b0: No Frame Overrun 6416 * 1'b1: Frame Overrun 6417 */ 6418 #define USB_H_FRMOVRUN7 (BIT(9)) 6419 #define USB_H_FRMOVRUN7_M (USB_H_FRMOVRUN7_V << USB_H_FRMOVRUN7_S) 6420 #define USB_H_FRMOVRUN7_V 0x00000001 6421 #define USB_H_FRMOVRUN7_S 9 6422 /** USB_H_DATATGLERR7 : R/W1C; bitpos: [10]; default: 0; 6423 * 1'b0: No Data Toggle Error 6424 * 1'b1: Data Toggle Error 6425 */ 6426 #define USB_H_DATATGLERR7 (BIT(10)) 6427 #define USB_H_DATATGLERR7_M (USB_H_DATATGLERR7_V << USB_H_DATATGLERR7_S) 6428 #define USB_H_DATATGLERR7_V 0x00000001 6429 #define USB_H_DATATGLERR7_S 10 6430 /** USB_H_BNAINTR7 : R/W1C; bitpos: [11]; default: 0; 6431 * 1'b0: No BNA Interrupt 6432 * 1'b1: BNA Interrupt 6433 */ 6434 #define USB_H_BNAINTR7 (BIT(11)) 6435 #define USB_H_BNAINTR7_M (USB_H_BNAINTR7_V << USB_H_BNAINTR7_S) 6436 #define USB_H_BNAINTR7_V 0x00000001 6437 #define USB_H_BNAINTR7_S 11 6438 /** USB_H_XCS_XACT_ERR7 : R/W1C; bitpos: [12]; default: 0; 6439 * 1'b0: No Excessive Transaction Error 6440 * 1'b1: Excessive Transaction Error 6441 */ 6442 #define USB_H_XCS_XACT_ERR7 (BIT(12)) 6443 #define USB_H_XCS_XACT_ERR7_M (USB_H_XCS_XACT_ERR7_V << USB_H_XCS_XACT_ERR7_S) 6444 #define USB_H_XCS_XACT_ERR7_V 0x00000001 6445 #define USB_H_XCS_XACT_ERR7_S 12 6446 /** USB_H_DESC_LST_ROLLINTR7 : R/W1C; bitpos: [13]; default: 0; 6447 * 1'b0: No Descriptor rollover interrupt 6448 * 1'b1: Descriptor rollover interrupt 6449 */ 6450 #define USB_H_DESC_LST_ROLLINTR7 (BIT(13)) 6451 #define USB_H_DESC_LST_ROLLINTR7_M (USB_H_DESC_LST_ROLLINTR7_V << USB_H_DESC_LST_ROLLINTR7_S) 6452 #define USB_H_DESC_LST_ROLLINTR7_V 0x00000001 6453 #define USB_H_DESC_LST_ROLLINTR7_S 13 6454 6455 6456 /** USB_HCINTMSK7_REG register 6457 * Host Channel 7 Interrupt Mask Register 6458 */ 6459 #define USB_HCINTMSK7_REG (SOC_DPORT_USB_BASE + 0x5ec) 6460 /** USB_H_XFERCOMPLMSK7 : R/W; bitpos: [0]; default: 0; 6461 * 1'b0: Transfer Completed Mask 6462 * 1'b1: No Transfer Completed Mask 6463 */ 6464 #define USB_H_XFERCOMPLMSK7 (BIT(0)) 6465 #define USB_H_XFERCOMPLMSK7_M (USB_H_XFERCOMPLMSK7_V << USB_H_XFERCOMPLMSK7_S) 6466 #define USB_H_XFERCOMPLMSK7_V 0x00000001 6467 #define USB_H_XFERCOMPLMSK7_S 0 6468 /** USB_H_CHHLTDMSK7 : R/W; bitpos: [1]; default: 0; 6469 * 1'b0: Channel Halted Mask 6470 * 1'b1: No Channel Halted Mask 6471 */ 6472 #define USB_H_CHHLTDMSK7 (BIT(1)) 6473 #define USB_H_CHHLTDMSK7_M (USB_H_CHHLTDMSK7_V << USB_H_CHHLTDMSK7_S) 6474 #define USB_H_CHHLTDMSK7_V 0x00000001 6475 #define USB_H_CHHLTDMSK7_S 1 6476 /** USB_H_AHBERRMSK7 : R/W; bitpos: [2]; default: 0; 6477 * 1'b0: AHB Error Mask 6478 * 1'b1: No AHB Error Mask 6479 */ 6480 #define USB_H_AHBERRMSK7 (BIT(2)) 6481 #define USB_H_AHBERRMSK7_M (USB_H_AHBERRMSK7_V << USB_H_AHBERRMSK7_S) 6482 #define USB_H_AHBERRMSK7_V 0x00000001 6483 #define USB_H_AHBERRMSK7_S 2 6484 /** USB_H_STALLMSK7 : R/W; bitpos: [3]; default: 0; 6485 * 1'b0: Mask STALL Response Received Interrupt 6486 * 1'b1: No STALL Response Received Interrupt Mask 6487 */ 6488 #define USB_H_STALLMSK7 (BIT(3)) 6489 #define USB_H_STALLMSK7_M (USB_H_STALLMSK7_V << USB_H_STALLMSK7_S) 6490 #define USB_H_STALLMSK7_V 0x00000001 6491 #define USB_H_STALLMSK7_S 3 6492 /** USB_H_NAKMSK7 : R/W; bitpos: [4]; default: 0; 6493 * 1'b0: Mask NAK Response Received Interrupt 6494 * 1'b1: No NAK Response Received Interrupt Mask 6495 */ 6496 #define USB_H_NAKMSK7 (BIT(4)) 6497 #define USB_H_NAKMSK7_M (USB_H_NAKMSK7_V << USB_H_NAKMSK7_S) 6498 #define USB_H_NAKMSK7_V 0x00000001 6499 #define USB_H_NAKMSK7_S 4 6500 /** USB_H_ACKMSK7 : R/W; bitpos: [5]; default: 0; 6501 * 1'b0: Mask ACK Response Received/Transmitted Interrupt 6502 * 1'b1: No ACK Response Received/Transmitted Interrupt Mask 6503 */ 6504 #define USB_H_ACKMSK7 (BIT(5)) 6505 #define USB_H_ACKMSK7_M (USB_H_ACKMSK7_V << USB_H_ACKMSK7_S) 6506 #define USB_H_ACKMSK7_V 0x00000001 6507 #define USB_H_ACKMSK7_S 5 6508 /** USB_H_NYETMSK7 : R/W; bitpos: [6]; default: 0; 6509 * 1'b0: Mask NYET Response Received Interrupt 6510 * 1'b1: No NYET Response Received Interrupt Mask 6511 */ 6512 #define USB_H_NYETMSK7 (BIT(6)) 6513 #define USB_H_NYETMSK7_M (USB_H_NYETMSK7_V << USB_H_NYETMSK7_S) 6514 #define USB_H_NYETMSK7_V 0x00000001 6515 #define USB_H_NYETMSK7_S 6 6516 /** USB_H_XACTERRMSK7 : R/W; bitpos: [7]; default: 0; 6517 * 1'b0: Mask Transaction Error 6518 * 1'b1: No Transaction Error Mask 6519 */ 6520 #define USB_H_XACTERRMSK7 (BIT(7)) 6521 #define USB_H_XACTERRMSK7_M (USB_H_XACTERRMSK7_V << USB_H_XACTERRMSK7_S) 6522 #define USB_H_XACTERRMSK7_V 0x00000001 6523 #define USB_H_XACTERRMSK7_S 7 6524 /** USB_H_BBLERRMSK7 : R/W; bitpos: [8]; default: 0; 6525 * Babble Error Mask 6526 * 1'b0: Mask Babble Error 6527 * 1'b1: No Babble Error Mask 6528 */ 6529 #define USB_H_BBLERRMSK7 (BIT(8)) 6530 #define USB_H_BBLERRMSK7_M (USB_H_BBLERRMSK7_V << USB_H_BBLERRMSK7_S) 6531 #define USB_H_BBLERRMSK7_V 0x00000001 6532 #define USB_H_BBLERRMSK7_S 8 6533 /** USB_H_FRMOVRUNMSK7 : R/W; bitpos: [9]; default: 0; 6534 * Frame Overrun Mask 6535 * 0x0 (MASK): Mask Overrun Mask 6536 * 0x1 (NOMASK): No Frame Overrun Mask 6537 */ 6538 #define USB_H_FRMOVRUNMSK7 (BIT(9)) 6539 #define USB_H_FRMOVRUNMSK7_M (USB_H_FRMOVRUNMSK7_V << USB_H_FRMOVRUNMSK7_S) 6540 #define USB_H_FRMOVRUNMSK7_V 0x00000001 6541 #define USB_H_FRMOVRUNMSK7_S 9 6542 /** USB_H_DATATGLERRMSK7 : R/W; bitpos: [10]; default: 0; 6543 * Data Toggle Error Mask n scatter/gather DMA mode for host 6544 * 1'b0: Mask Data Toggle Error 6545 * 1'b1: No Data Toggle Error Mask 6546 */ 6547 #define USB_H_DATATGLERRMSK7 (BIT(10)) 6548 #define USB_H_DATATGLERRMSK7_M (USB_H_DATATGLERRMSK7_V << USB_H_DATATGLERRMSK7_S) 6549 #define USB_H_DATATGLERRMSK7_V 0x00000001 6550 #define USB_H_DATATGLERRMSK7_S 10 6551 /** USB_H_BNAINTRMSK7 : R/W; bitpos: [11]; default: 0; 6552 * BNA (Buffer Not Available) Interrupt mask register 6553 * 1'b0: BNA Interrupt Masked 6554 * 1'b1: BNA Interrupt not masked 6555 */ 6556 #define USB_H_BNAINTRMSK7 (BIT(11)) 6557 #define USB_H_BNAINTRMSK7_M (USB_H_BNAINTRMSK7_V << USB_H_BNAINTRMSK7_S) 6558 #define USB_H_BNAINTRMSK7_V 0x00000001 6559 #define USB_H_BNAINTRMSK7_S 11 6560 /** USB_H_DESC_LST_ROLLINTRMSK7 : R/W; bitpos: [13]; default: 0; 6561 * Descriptor List rollover interrupt Mask 6562 * 1'b0: Descriptor Rollover Interrupt Mask 6563 * 1'b1: Descriptor Rollover Interrupt not masked 6564 */ 6565 #define USB_H_DESC_LST_ROLLINTRMSK7 (BIT(13)) 6566 #define USB_H_DESC_LST_ROLLINTRMSK7_M (USB_H_DESC_LST_ROLLINTRMSK7_V << USB_H_DESC_LST_ROLLINTRMSK7_S) 6567 #define USB_H_DESC_LST_ROLLINTRMSK7_V 0x00000001 6568 #define USB_H_DESC_LST_ROLLINTRMSK7_S 13 6569 6570 6571 /** USB_DIEPMSK_REG register 6572 * Device IN Endpoint Common Interrupt Mask Register 6573 */ 6574 #define USB_DIEPMSK_REG (SOC_DPORT_USB_BASE + 0x810) 6575 /** USB_DI_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0; 6576 * 0x0 : Mask Transfer Completed Interrupt 6577 * 0x1 : No Transfer Completed Interrupt Mask 6578 */ 6579 #define USB_DI_XFERCOMPLMSK (BIT(0)) 6580 #define USB_DI_XFERCOMPLMSK_M (USB_DI_XFERCOMPLMSK_V << USB_DI_XFERCOMPLMSK_S) 6581 #define USB_DI_XFERCOMPLMSK_V 0x00000001 6582 #define USB_DI_XFERCOMPLMSK_S 0 6583 /** USB_DI_EPDISBLDMSK : R/W; bitpos: [1]; default: 0; 6584 * 0x0 : Mask Endpoint Disabled Interrupt 6585 * 0x1 : No Endpoint Disabled Interrupt Mask 6586 */ 6587 #define USB_DI_EPDISBLDMSK (BIT(1)) 6588 #define USB_DI_EPDISBLDMSK_M (USB_DI_EPDISBLDMSK_V << USB_DI_EPDISBLDMSK_S) 6589 #define USB_DI_EPDISBLDMSK_V 0x00000001 6590 #define USB_DI_EPDISBLDMSK_S 1 6591 /** USB_DI_AHBERMSK : R/W; bitpos: [2]; default: 0; 6592 * 0x0 : Mask AHB Error Interrupt 6593 * 0x1 : No AHB Error Interrupt Mask 6594 */ 6595 #define USB_DI_AHBERMSK (BIT(2)) 6596 #define USB_DI_AHBERMSK_M (USB_DI_AHBERMSK_V << USB_DI_AHBERMSK_S) 6597 #define USB_DI_AHBERMSK_V 0x00000001 6598 #define USB_DI_AHBERMSK_S 2 6599 /** USB_TIMEOUTMSK : R/W; bitpos: [3]; default: 0; 6600 * 0x0 : Mask Timeout Condition Interrupt 6601 * 0x1 : No Timeout Condition Interrupt Mask 6602 */ 6603 #define USB_TIMEOUTMSK (BIT(3)) 6604 #define USB_TIMEOUTMSK_M (USB_TIMEOUTMSK_V << USB_TIMEOUTMSK_S) 6605 #define USB_TIMEOUTMSK_V 0x00000001 6606 #define USB_TIMEOUTMSK_S 3 6607 /** USB_INTKNTXFEMPMSK : R/W; bitpos: [4]; default: 0; 6608 * 0x0 : Mask IN Token Received When TxFIFO Empty Interrupt 6609 * 0x1 : No IN Token Received When TxFIFO Empty Interrupt 6610 */ 6611 #define USB_INTKNTXFEMPMSK (BIT(4)) 6612 #define USB_INTKNTXFEMPMSK_M (USB_INTKNTXFEMPMSK_V << USB_INTKNTXFEMPMSK_S) 6613 #define USB_INTKNTXFEMPMSK_V 0x00000001 6614 #define USB_INTKNTXFEMPMSK_S 4 6615 /** USB_INTKNEPMISMSK : R/W; bitpos: [5]; default: 0; 6616 * 0x0 : Mask IN Token received with EP Mismatch Interrupt 6617 * 0x1 : No Mask IN Token received with EP Mismatch Interrupt 6618 */ 6619 #define USB_INTKNEPMISMSK (BIT(5)) 6620 #define USB_INTKNEPMISMSK_M (USB_INTKNEPMISMSK_V << USB_INTKNEPMISMSK_S) 6621 #define USB_INTKNEPMISMSK_V 0x00000001 6622 #define USB_INTKNEPMISMSK_S 5 6623 /** USB_INEPNAKEFFMSK : R/W; bitpos: [6]; default: 0; 6624 * 0x0 : Mask IN Endpoint NAK Effective Interrupt 6625 * 0x1 : No IN Endpoint NAK Effective Interrupt Mask 6626 */ 6627 #define USB_INEPNAKEFFMSK (BIT(6)) 6628 #define USB_INEPNAKEFFMSK_M (USB_INEPNAKEFFMSK_V << USB_INEPNAKEFFMSK_S) 6629 #define USB_INEPNAKEFFMSK_V 0x00000001 6630 #define USB_INEPNAKEFFMSK_S 6 6631 /** USB_TXFIFOUNDRNMSK : R/W; bitpos: [8]; default: 0; 6632 * 0x0 : Mask Fifo Underrun Interrupt 6633 * 0x1 : No Fifo Underrun Interrupt Mask 6634 */ 6635 #define USB_TXFIFOUNDRNMSK (BIT(8)) 6636 #define USB_TXFIFOUNDRNMSK_M (USB_TXFIFOUNDRNMSK_V << USB_TXFIFOUNDRNMSK_S) 6637 #define USB_TXFIFOUNDRNMSK_V 0x00000001 6638 #define USB_TXFIFOUNDRNMSK_S 8 6639 /** USB_BNAININTRMSK : R/W; bitpos: [9]; default: 0; 6640 * 0x0 : Mask BNA Interrupt 6641 * 0x1 : No BNA Interrupt Mask 6642 */ 6643 #define USB_BNAININTRMSK (BIT(9)) 6644 #define USB_BNAININTRMSK_M (USB_BNAININTRMSK_V << USB_BNAININTRMSK_S) 6645 #define USB_BNAININTRMSK_V 0x00000001 6646 #define USB_BNAININTRMSK_S 9 6647 /** USB_DI_NAKMSK : R/W; bitpos: [13]; default: 0; 6648 * 0x0 : Mask NAK Interrupt 6649 * 0x1 : No Mask NAK Interrupt 6650 */ 6651 #define USB_DI_NAKMSK (BIT(13)) 6652 #define USB_DI_NAKMSK_M (USB_DI_NAKMSK_V << USB_DI_NAKMSK_S) 6653 #define USB_DI_NAKMSK_V 0x00000001 6654 #define USB_DI_NAKMSK_S 13 6655 6656 6657 /** USB_DOEPMSK_REG register 6658 * Device OUT Endpoint Common Interrupt Mask Register 6659 */ 6660 #define USB_DOEPMSK_REG (SOC_DPORT_USB_BASE + 0x814) 6661 /** USB_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0; 6662 * 0x0 : Mask Transfer Completed Interrupt 6663 * 0x1 : No Transfer Completed Interrupt Mask 6664 */ 6665 #define USB_XFERCOMPLMSK (BIT(0)) 6666 #define USB_XFERCOMPLMSK_M (USB_XFERCOMPLMSK_V << USB_XFERCOMPLMSK_S) 6667 #define USB_XFERCOMPLMSK_V 0x00000001 6668 #define USB_XFERCOMPLMSK_S 0 6669 /** USB_EPDISBLDMSK : R/W; bitpos: [1]; default: 0; 6670 * 0x0 : Mask Endpoint Disabled Interrupt 6671 * 0x1 : No Endpoint Disabled Interrupt Mask 6672 */ 6673 #define USB_EPDISBLDMSK (BIT(1)) 6674 #define USB_EPDISBLDMSK_M (USB_EPDISBLDMSK_V << USB_EPDISBLDMSK_S) 6675 #define USB_EPDISBLDMSK_V 0x00000001 6676 #define USB_EPDISBLDMSK_S 1 6677 /** USB_AHBERMSK : R/W; bitpos: [2]; default: 0; 6678 * 0x0 : Mask AHB Error Interrupt 6679 * 0x1 : No AHB Error Interrupt Mask 6680 */ 6681 #define USB_AHBERMSK (BIT(2)) 6682 #define USB_AHBERMSK_M (USB_AHBERMSK_V << USB_AHBERMSK_S) 6683 #define USB_AHBERMSK_V 0x00000001 6684 #define USB_AHBERMSK_S 2 6685 /** USB_SETUPMSK : R/W; bitpos: [3]; default: 0; 6686 * 0x0 : Mask SETUP Phase Done Interrupt 6687 * 0x1 : No SETUP Phase Done Interrupt Mask 6688 */ 6689 #define USB_SETUPMSK (BIT(3)) 6690 #define USB_SETUPMSK_M (USB_SETUPMSK_V << USB_SETUPMSK_S) 6691 #define USB_SETUPMSK_V 0x00000001 6692 #define USB_SETUPMSK_S 3 6693 /** USB_OUTTKNEPDISMSK : R/W; bitpos: [4]; default: 0; 6694 * 0x0 : Mask OUT Token Received when Endpoint Disabled Interrupt 6695 * 0x1 : No OUT Token Received when Endpoint Disabled Interrupt Mask 6696 */ 6697 #define USB_OUTTKNEPDISMSK (BIT(4)) 6698 #define USB_OUTTKNEPDISMSK_M (USB_OUTTKNEPDISMSK_V << USB_OUTTKNEPDISMSK_S) 6699 #define USB_OUTTKNEPDISMSK_V 0x00000001 6700 #define USB_OUTTKNEPDISMSK_S 4 6701 /** USB_STSPHSERCVDMSK : R/W; bitpos: [5]; default: 0; 6702 * 0x0 : Status Phase Received Mask 6703 * 0x1 : No Status Phase Received Mask 6704 */ 6705 #define USB_STSPHSERCVDMSK (BIT(5)) 6706 #define USB_STSPHSERCVDMSK_M (USB_STSPHSERCVDMSK_V << USB_STSPHSERCVDMSK_S) 6707 #define USB_STSPHSERCVDMSK_V 0x00000001 6708 #define USB_STSPHSERCVDMSK_S 5 6709 /** USB_BACK2BACKSETUP : R/W; bitpos: [6]; default: 0; 6710 * 0x0 : Mask Back-to-Back SETUP Packets Received Interrupt 6711 * 0x1 : No Back-to-Back SETUP Packets Received Interrupt Mask 6712 */ 6713 #define USB_BACK2BACKSETUP (BIT(6)) 6714 #define USB_BACK2BACKSETUP_M (USB_BACK2BACKSETUP_V << USB_BACK2BACKSETUP_S) 6715 #define USB_BACK2BACKSETUP_V 0x00000001 6716 #define USB_BACK2BACKSETUP_S 6 6717 /** USB_OUTPKTERRMSK : R/W; bitpos: [8]; default: 0; 6718 * 0x0 : Mask OUT Packet Error Interrupt 6719 * 0x1 : No OUT Packet Error Interrupt Mask 6720 */ 6721 #define USB_OUTPKTERRMSK (BIT(8)) 6722 #define USB_OUTPKTERRMSK_M (USB_OUTPKTERRMSK_V << USB_OUTPKTERRMSK_S) 6723 #define USB_OUTPKTERRMSK_V 0x00000001 6724 #define USB_OUTPKTERRMSK_S 8 6725 /** USB_BNAOUTINTRMSK : R/W; bitpos: [9]; default: 0; 6726 * 0x0 : Mask BNA Interrupt 6727 * 0x1 : No BNA Interrupt Mask 6728 */ 6729 #define USB_BNAOUTINTRMSK (BIT(9)) 6730 #define USB_BNAOUTINTRMSK_M (USB_BNAOUTINTRMSK_V << USB_BNAOUTINTRMSK_S) 6731 #define USB_BNAOUTINTRMSK_V 0x00000001 6732 #define USB_BNAOUTINTRMSK_S 9 6733 /** USB_BBLEERRMSK : R/W; bitpos: [12]; default: 0; 6734 * 0x0 : Mask Babble Error Interrupt 6735 * 0x1 : No Babble Error Interrupt Mask 6736 */ 6737 #define USB_BBLEERRMSK (BIT(12)) 6738 #define USB_BBLEERRMSK_M (USB_BBLEERRMSK_V << USB_BBLEERRMSK_S) 6739 #define USB_BBLEERRMSK_V 0x00000001 6740 #define USB_BBLEERRMSK_S 12 6741 /** USB_NAKMSK : R/W; bitpos: [13]; default: 0; 6742 * 0x0 : Mask NAK Interrupt 6743 * 0x1 : No NAK Interrupt Mask 6744 */ 6745 #define USB_NAKMSK (BIT(13)) 6746 #define USB_NAKMSK_M (USB_NAKMSK_V << USB_NAKMSK_S) 6747 #define USB_NAKMSK_V 0x00000001 6748 #define USB_NAKMSK_S 13 6749 /** USB_NYETMSK : R/W; bitpos: [14]; default: 0; 6750 * NYET interrupt Mask 6751 * 0x0 : Mask NYET Interrupt 6752 * 0x1 : No NYET Interrupt Mask 6753 */ 6754 #define USB_NYETMSK (BIT(14)) 6755 #define USB_NYETMSK_M (USB_NYETMSK_V << USB_NYETMSK_S) 6756 #define USB_NYETMSK_V 0x00000001 6757 #define USB_NYETMSK_S 14 6758 6759 6760 /** USB_DAINT_REG register 6761 * Device All Endpoints Interrupt Register 6762 */ 6763 #define USB_DAINT_REG (SOC_DPORT_USB_BASE + 0x818) 6764 /** USB_INEPINT0 : RO; bitpos: [0]; default: 0; 6765 * IN Endpoint 0 Interrupt Bit. 6766 */ 6767 #define USB_INEPINT0 (BIT(0)) 6768 #define USB_INEPINT0_M (USB_INEPINT0_V << USB_INEPINT0_S) 6769 #define USB_INEPINT0_V 0x00000001 6770 #define USB_INEPINT0_S 0 6771 /** USB_INEPINT1 : RO; bitpos: [1]; default: 0; 6772 * IN Endpoint 1 Interrupt Bit. 6773 */ 6774 #define USB_INEPINT1 (BIT(1)) 6775 #define USB_INEPINT1_M (USB_INEPINT1_V << USB_INEPINT1_S) 6776 #define USB_INEPINT1_V 0x00000001 6777 #define USB_INEPINT1_S 1 6778 /** USB_INEPINT2 : RO; bitpos: [2]; default: 0; 6779 * IN Endpoint 2 Interrupt Bit. 6780 */ 6781 #define USB_INEPINT2 (BIT(2)) 6782 #define USB_INEPINT2_M (USB_INEPINT2_V << USB_INEPINT2_S) 6783 #define USB_INEPINT2_V 0x00000001 6784 #define USB_INEPINT2_S 2 6785 /** USB_INEPINT3 : RO; bitpos: [3]; default: 0; 6786 * IN Endpoint 3 Interrupt Bit. 6787 */ 6788 #define USB_INEPINT3 (BIT(3)) 6789 #define USB_INEPINT3_M (USB_INEPINT3_V << USB_INEPINT3_S) 6790 #define USB_INEPINT3_V 0x00000001 6791 #define USB_INEPINT3_S 3 6792 /** USB_INEPINT4 : RO; bitpos: [4]; default: 0; 6793 * IN Endpoint 4 Interrupt Bit. 6794 */ 6795 #define USB_INEPINT4 (BIT(4)) 6796 #define USB_INEPINT4_M (USB_INEPINT4_V << USB_INEPINT4_S) 6797 #define USB_INEPINT4_V 0x00000001 6798 #define USB_INEPINT4_S 4 6799 /** USB_INEPINT5 : RO; bitpos: [5]; default: 0; 6800 * IN Endpoint 5 Interrupt Bit. 6801 */ 6802 #define USB_INEPINT5 (BIT(5)) 6803 #define USB_INEPINT5_M (USB_INEPINT5_V << USB_INEPINT5_S) 6804 #define USB_INEPINT5_V 0x00000001 6805 #define USB_INEPINT5_S 5 6806 /** USB_INEPINT6 : RO; bitpos: [6]; default: 0; 6807 * IN Endpoint 6 Interrupt Bit. 6808 */ 6809 #define USB_INEPINT6 (BIT(6)) 6810 #define USB_INEPINT6_M (USB_INEPINT6_V << USB_INEPINT6_S) 6811 #define USB_INEPINT6_V 0x00000001 6812 #define USB_INEPINT6_S 6 6813 /** USB_OUTEPINT0 : RO; bitpos: [16]; default: 0; 6814 * OUT Endpoint 0 Interrupt Bit. 6815 */ 6816 #define USB_OUTEPINT0 (BIT(16)) 6817 #define USB_OUTEPINT0_M (USB_OUTEPINT0_V << USB_OUTEPINT0_S) 6818 #define USB_OUTEPINT0_V 0x00000001 6819 #define USB_OUTEPINT0_S 16 6820 /** USB_OUTEPINT1 : RO; bitpos: [17]; default: 0; 6821 * OUT Endpoint 1 Interrupt Bit. 6822 */ 6823 #define USB_OUTEPINT1 (BIT(17)) 6824 #define USB_OUTEPINT1_M (USB_OUTEPINT1_V << USB_OUTEPINT1_S) 6825 #define USB_OUTEPINT1_V 0x00000001 6826 #define USB_OUTEPINT1_S 17 6827 /** USB_OUTEPINT2 : RO; bitpos: [18]; default: 0; 6828 * OUT Endpoint 2 Interrupt Bit. 6829 */ 6830 #define USB_OUTEPINT2 (BIT(18)) 6831 #define USB_OUTEPINT2_M (USB_OUTEPINT2_V << USB_OUTEPINT2_S) 6832 #define USB_OUTEPINT2_V 0x00000001 6833 #define USB_OUTEPINT2_S 18 6834 /** USB_OUTEPINT3 : RO; bitpos: [19]; default: 0; 6835 * OUT Endpoint 3 Interrupt Bit. 6836 */ 6837 #define USB_OUTEPINT3 (BIT(19)) 6838 #define USB_OUTEPINT3_M (USB_OUTEPINT3_V << USB_OUTEPINT3_S) 6839 #define USB_OUTEPINT3_V 0x00000001 6840 #define USB_OUTEPINT3_S 19 6841 /** USB_OUTEPINT4 : RO; bitpos: [20]; default: 0; 6842 * OUT Endpoint 4 Interrupt Bit. 6843 */ 6844 #define USB_OUTEPINT4 (BIT(20)) 6845 #define USB_OUTEPINT4_M (USB_OUTEPINT4_V << USB_OUTEPINT4_S) 6846 #define USB_OUTEPINT4_V 0x00000001 6847 #define USB_OUTEPINT4_S 20 6848 /** USB_OUTEPINT5 : RO; bitpos: [21]; default: 0; 6849 * OUT Endpoint 5 Interrupt Bit. 6850 */ 6851 #define USB_OUTEPINT5 (BIT(21)) 6852 #define USB_OUTEPINT5_M (USB_OUTEPINT5_V << USB_OUTEPINT5_S) 6853 #define USB_OUTEPINT5_V 0x00000001 6854 #define USB_OUTEPINT5_S 21 6855 /** USB_OUTEPINT6 : RO; bitpos: [22]; default: 0; 6856 * OUT Endpoint 6 Interrupt Bit. 6857 */ 6858 #define USB_OUTEPINT6 (BIT(22)) 6859 #define USB_OUTEPINT6_M (USB_OUTEPINT6_V << USB_OUTEPINT6_S) 6860 #define USB_OUTEPINT6_V 0x00000001 6861 #define USB_OUTEPINT6_S 22 6862 6863 6864 /** USB_DAINTMSK_REG register 6865 * Device All Endpoints Interrupt Mask Register 6866 */ 6867 #define USB_DAINTMSK_REG (SOC_DPORT_USB_BASE + 0x81c) 6868 /** USB_INEPMSK0 : R/W; bitpos: [0]; default: 0; 6869 * IN Endpoint 0 Interrupt mask Bit. 6870 */ 6871 #define USB_INEPMSK0 (BIT(0)) 6872 #define USB_INEPMSK0_M (USB_INEPMSK0_V << USB_INEPMSK0_S) 6873 #define USB_INEPMSK0_V 0x00000001 6874 #define USB_INEPMSK0_S 0 6875 /** USB_INEPMSK1 : R/W; bitpos: [1]; default: 0; 6876 * IN Endpoint 1 Interrupt mask Bit. 6877 */ 6878 #define USB_INEPMSK1 (BIT(1)) 6879 #define USB_INEPMSK1_M (USB_INEPMSK1_V << USB_INEPMSK1_S) 6880 #define USB_INEPMSK1_V 0x00000001 6881 #define USB_INEPMSK1_S 1 6882 /** USB_INEPMSK2 : R/W; bitpos: [2]; default: 0; 6883 * IN Endpoint 2 Interrupt mask Bit. 6884 */ 6885 #define USB_INEPMSK2 (BIT(2)) 6886 #define USB_INEPMSK2_M (USB_INEPMSK2_V << USB_INEPMSK2_S) 6887 #define USB_INEPMSK2_V 0x00000001 6888 #define USB_INEPMSK2_S 2 6889 /** USB_INEPMSK3 : R/W; bitpos: [3]; default: 0; 6890 * IN Endpoint 3 Interrupt mask Bit. 6891 */ 6892 #define USB_INEPMSK3 (BIT(3)) 6893 #define USB_INEPMSK3_M (USB_INEPMSK3_V << USB_INEPMSK3_S) 6894 #define USB_INEPMSK3_V 0x00000001 6895 #define USB_INEPMSK3_S 3 6896 /** USB_INEPMSK4 : R/W; bitpos: [4]; default: 0; 6897 * IN Endpoint 4 Interrupt mask Bit. 6898 */ 6899 #define USB_INEPMSK4 (BIT(4)) 6900 #define USB_INEPMSK4_M (USB_INEPMSK4_V << USB_INEPMSK4_S) 6901 #define USB_INEPMSK4_V 0x00000001 6902 #define USB_INEPMSK4_S 4 6903 /** USB_INEPMSK5 : R/W; bitpos: [5]; default: 0; 6904 * IN Endpoint 5 Interrupt mask Bit. 6905 */ 6906 #define USB_INEPMSK5 (BIT(5)) 6907 #define USB_INEPMSK5_M (USB_INEPMSK5_V << USB_INEPMSK5_S) 6908 #define USB_INEPMSK5_V 0x00000001 6909 #define USB_INEPMSK5_S 5 6910 /** USB_INEPMSK6 : R/W; bitpos: [6]; default: 0; 6911 * IN Endpoint 6 Interrupt mask Bit. 6912 */ 6913 #define USB_INEPMSK6 (BIT(6)) 6914 #define USB_INEPMSK6_M (USB_INEPMSK6_V << USB_INEPMSK6_S) 6915 #define USB_INEPMSK6_V 0x00000001 6916 #define USB_INEPMSK6_S 6 6917 /** USB_OUTEPMSK0 : R/W; bitpos: [16]; default: 0; 6918 * OUT Endpoint 0 Interrupt mask Bit. 6919 */ 6920 #define USB_OUTEPMSK0 (BIT(16)) 6921 #define USB_OUTEPMSK0_M (USB_OUTEPMSK0_V << USB_OUTEPMSK0_S) 6922 #define USB_OUTEPMSK0_V 0x00000001 6923 #define USB_OUTEPMSK0_S 16 6924 /** USB_OUTEPMSK1 : R/W; bitpos: [17]; default: 0; 6925 * OUT Endpoint 1 Interrupt mask Bit. 6926 */ 6927 #define USB_OUTEPMSK1 (BIT(17)) 6928 #define USB_OUTEPMSK1_M (USB_OUTEPMSK1_V << USB_OUTEPMSK1_S) 6929 #define USB_OUTEPMSK1_V 0x00000001 6930 #define USB_OUTEPMSK1_S 17 6931 /** USB_OUTEPMSK2 : R/W; bitpos: [18]; default: 0; 6932 * OUT Endpoint 2 Interrupt mask Bit. 6933 */ 6934 #define USB_OUTEPMSK2 (BIT(18)) 6935 #define USB_OUTEPMSK2_M (USB_OUTEPMSK2_V << USB_OUTEPMSK2_S) 6936 #define USB_OUTEPMSK2_V 0x00000001 6937 #define USB_OUTEPMSK2_S 18 6938 /** USB_OUTEPMSK3 : R/W; bitpos: [19]; default: 0; 6939 * OUT Endpoint 3 Interrupt mask Bit. 6940 */ 6941 #define USB_OUTEPMSK3 (BIT(19)) 6942 #define USB_OUTEPMSK3_M (USB_OUTEPMSK3_V << USB_OUTEPMSK3_S) 6943 #define USB_OUTEPMSK3_V 0x00000001 6944 #define USB_OUTEPMSK3_S 19 6945 /** USB_OUTEPMSK4 : R/W; bitpos: [20]; default: 0; 6946 * OUT Endpoint 4 Interrupt mask Bit. 6947 */ 6948 #define USB_OUTEPMSK4 (BIT(20)) 6949 #define USB_OUTEPMSK4_M (USB_OUTEPMSK4_V << USB_OUTEPMSK4_S) 6950 #define USB_OUTEPMSK4_V 0x00000001 6951 #define USB_OUTEPMSK4_S 20 6952 /** USB_OUTEPMSK5 : R/W; bitpos: [21]; default: 0; 6953 * OUT Endpoint 5 Interrupt mask Bit. 6954 */ 6955 #define USB_OUTEPMSK5 (BIT(21)) 6956 #define USB_OUTEPMSK5_M (USB_OUTEPMSK5_V << USB_OUTEPMSK5_S) 6957 #define USB_OUTEPMSK5_V 0x00000001 6958 #define USB_OUTEPMSK5_S 21 6959 /** USB_OUTEPMSK6 : R/W; bitpos: [22]; default: 0; 6960 * OUT Endpoint 6 Interrupt mask Bit. 6961 */ 6962 #define USB_OUTEPMSK6 (BIT(22)) 6963 #define USB_OUTEPMSK6_M (USB_OUTEPMSK6_V << USB_OUTEPMSK6_S) 6964 #define USB_OUTEPMSK6_V 0x00000001 6965 #define USB_OUTEPMSK6_S 22 6966 6967 6968 /** USB_DIEPEMPMSK_REG register 6969 * Device IN Endpoint FIFO Empty Interrupt Mask Register 6970 */ 6971 #define USB_DIEPEMPMSK_REG (SOC_DPORT_USB_BASE + 0x834) 6972 /** USB_D_INEPTXFEMPMSK : R/W; bitpos: [16:0]; default: 0; 6973 * IN EP Tx FIFO Empty Interrupt Mask Bits 6974 * 0x1 (EP0_MASK): Mask IN EP0 Tx FIFO Empty Interrupt 6975 * 0x2 (EP1_MASK): Mask IN EP1 Tx FIFO Empty Interrupt 6976 * 0x4 (EP2_MASK): Mask IN EP2 Tx FIFO Empty Interrupt 6977 * 0x8 (EP3_MASK): Mask IN EP3 Tx FIFO Empty Interrupt 6978 * 0x10 (EP4_MASK): Mask IN EP4 Tx FIFO Empty Interrupt 6979 * 0x20 (EP5_MASK): Mask IN EP5 Tx FIFO Empty Interrupt 6980 * 0x40 (EP6_MASK): Mask IN EP6 Tx FIFO Empty Interrupt 6981 * 0x80 (EP7_MASK): Mask IN EP7 Tx FIFO Empty Interrupt 6982 * 0x100 (EP8_MASK): Mask IN EP8 Tx FIFO Empty Interrupt 6983 * 0x200 (EP9_MASK): Mask IN EP9 Tx FIFO Empty Interrupt 6984 * 0x400 (EP10_MASK): Mask IN EP10 Tx FIFO Empty Interrupt 6985 * 0x800 (EP11_MASK): Mask IN EP11 Tx FIFO Empty Interrupt 6986 * 0x1000 (EP12_MASK): Mask IN EP12 Tx FIFO Empty Interrupt 6987 * 0x2000 (EP13_MASK): Mask IN EP13 Tx FIFO Empty Interrupt 6988 * 0x4000 (EP14_MASK): Mask IN EP14 Tx FIFO Empty Interrupt 6989 * 0x8000 (EP15_MASK): Mask IN EP15 Tx FIFO Empty Interrupt 6990 */ 6991 #define USB_D_INEPTXFEMPMSK 0x0000FFFF 6992 #define USB_D_INEPTXFEMPMSK_M (USB_D_INEPTXFEMPMSK_V << USB_D_INEPTXFEMPMSK_S) 6993 #define USB_D_INEPTXFEMPMSK_V 0x0000FFFF 6994 #define USB_D_INEPTXFEMPMSK_S 0 6995 6996 6997 /** USB_DIEPINT0_REG register 6998 * Device IN Endpoint 0 Interrupt Register 6999 */ 7000 #define USB_DIEPINT0_REG (SOC_DPORT_USB_BASE + 0x908) 7001 /** USB_D_XFERCOMPL0 : R/W1C; bitpos: [0]; default: 0; 7002 * 0x0 : No Transfer Complete Interrupt 7003 * 0x1 : Transfer Completed Interrupt 7004 */ 7005 #define USB_D_XFERCOMPL0 (BIT(0)) 7006 #define USB_D_XFERCOMPL0_M (USB_D_XFERCOMPL0_V << USB_D_XFERCOMPL0_S) 7007 #define USB_D_XFERCOMPL0_V 0x00000001 7008 #define USB_D_XFERCOMPL0_S 0 7009 /** USB_D_EPDISBLD0 : R/W1C; bitpos: [1]; default: 0; 7010 * 0x0 : No Endpoint Disabled Interrupt 7011 * 0x1 : Endpoint Disabled Interrupt 7012 */ 7013 #define USB_D_EPDISBLD0 (BIT(1)) 7014 #define USB_D_EPDISBLD0_M (USB_D_EPDISBLD0_V << USB_D_EPDISBLD0_S) 7015 #define USB_D_EPDISBLD0_V 0x00000001 7016 #define USB_D_EPDISBLD0_S 1 7017 /** USB_D_AHBERR0 : R/W1C; bitpos: [2]; default: 0; 7018 * 0x0 : No AHB Error Interrupt 7019 * 0x1 : AHB Error interrupt 7020 */ 7021 #define USB_D_AHBERR0 (BIT(2)) 7022 #define USB_D_AHBERR0_M (USB_D_AHBERR0_V << USB_D_AHBERR0_S) 7023 #define USB_D_AHBERR0_V 0x00000001 7024 #define USB_D_AHBERR0_S 2 7025 /** USB_D_TIMEOUT0 : R/W1C; bitpos: [3]; default: 0; 7026 * 0x0 : No Timeout interrupt 7027 * 0x1 : Timeout interrupt 7028 */ 7029 #define USB_D_TIMEOUT0 (BIT(3)) 7030 #define USB_D_TIMEOUT0_M (USB_D_TIMEOUT0_V << USB_D_TIMEOUT0_S) 7031 #define USB_D_TIMEOUT0_V 0x00000001 7032 #define USB_D_TIMEOUT0_S 3 7033 /** USB_D_INTKNTXFEMP0 : R/W1C; bitpos: [4]; default: 0; 7034 * 0x0 : No IN Token Received when TxFIFO Empty Interrupt 7035 * 0x1 : IN Token Received when TxFIFO Empty Interrupt 7036 */ 7037 #define USB_D_INTKNTXFEMP0 (BIT(4)) 7038 #define USB_D_INTKNTXFEMP0_M (USB_D_INTKNTXFEMP0_V << USB_D_INTKNTXFEMP0_S) 7039 #define USB_D_INTKNTXFEMP0_V 0x00000001 7040 #define USB_D_INTKNTXFEMP0_S 4 7041 /** USB_D_INTKNEPMIS0 : R/W1C; bitpos: [5]; default: 0; 7042 * 0x0 : No IN Token Received with EP Mismatch Interrupt 7043 * 0x1 : IN Token Received with EP Mismatch interrupt 7044 */ 7045 #define USB_D_INTKNEPMIS0 (BIT(5)) 7046 #define USB_D_INTKNEPMIS0_M (USB_D_INTKNEPMIS0_V << USB_D_INTKNEPMIS0_S) 7047 #define USB_D_INTKNEPMIS0_V 0x00000001 7048 #define USB_D_INTKNEPMIS0_S 5 7049 /** USB_D_INEPNAKEFF0 : R/W1C; bitpos: [6]; default: 0; 7050 * IN Endpoint NAK Effective 7051 * 0x0 : No IN Endpoint NAK Effective interrupt 7052 * 0x1 : IN Endpoint NAK Effective interrupt 7053 */ 7054 #define USB_D_INEPNAKEFF0 (BIT(6)) 7055 #define USB_D_INEPNAKEFF0_M (USB_D_INEPNAKEFF0_V << USB_D_INEPNAKEFF0_S) 7056 #define USB_D_INEPNAKEFF0_V 0x00000001 7057 #define USB_D_INEPNAKEFF0_S 6 7058 /** USB_D_TXFEMP0 : RO; bitpos: [7]; default: 0; 7059 * This interrupt is asserted when the TxFIFO for this endpoint is either half or 7060 * completely empty 7061 * 0x0 : No Transmit FIFO Empty interrupt 7062 * 0x1 : Transmit FIFO Empty interrupt 7063 */ 7064 #define USB_D_TXFEMP0 (BIT(7)) 7065 #define USB_D_TXFEMP0_M (USB_D_TXFEMP0_V << USB_D_TXFEMP0_S) 7066 #define USB_D_TXFEMP0_V 0x00000001 7067 #define USB_D_TXFEMP0_S 7 7068 /** USB_D_TXFIFOUNDRN0 : R/W1C; bitpos: [8]; default: 0; 7069 * The core generates this interrupt when it detects a transmit FIFO underrun 7070 * condition in threshold mode for this endpoint 7071 * 0x0 : No Fifo Underrun interrupt 7072 * 0x1 : Fifo Underrun interrupt 7073 */ 7074 #define USB_D_TXFIFOUNDRN0 (BIT(8)) 7075 #define USB_D_TXFIFOUNDRN0_M (USB_D_TXFIFOUNDRN0_V << USB_D_TXFIFOUNDRN0_S) 7076 #define USB_D_TXFIFOUNDRN0_V 0x00000001 7077 #define USB_D_TXFIFOUNDRN0_S 8 7078 /** USB_D_BNAINTR0 : R/W1C; bitpos: [9]; default: 0; 7079 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates 7080 * this interrupt when the descriptor accessed is not ready for the Core to process, 7081 * such as Host busy or DMA done 7082 * 0x0 : No BNA interrupt 7083 * 0x1 : BNA interrupt 7084 */ 7085 #define USB_D_BNAINTR0 (BIT(9)) 7086 #define USB_D_BNAINTR0_M (USB_D_BNAINTR0_V << USB_D_BNAINTR0_S) 7087 #define USB_D_BNAINTR0_V 0x00000001 7088 #define USB_D_BNAINTR0_S 9 7089 /** USB_D_PKTDRPSTS0 : R/W1C; bitpos: [11]; default: 0; 7090 * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet 7091 * has been dropped. This bit does not have an associated mask bit and does not 7092 * generate an interrupt 7093 * 0x0 : No interrupt 7094 * 0x1 : Packet Drop Status 7095 */ 7096 #define USB_D_PKTDRPSTS0 (BIT(11)) 7097 #define USB_D_PKTDRPSTS0_M (USB_D_PKTDRPSTS0_V << USB_D_PKTDRPSTS0_S) 7098 #define USB_D_PKTDRPSTS0_V 0x00000001 7099 #define USB_D_PKTDRPSTS0_S 11 7100 /** USB_D_BBLEERR0 : R/W1C; bitpos: [12]; default: 0; 7101 * The core generates this interrupt when babble is received for the endpoint 7102 * 0x0 : No interrupt 7103 * 0x1 : BbleErr interrupt 7104 */ 7105 #define USB_D_BBLEERR0 (BIT(12)) 7106 #define USB_D_BBLEERR0_M (USB_D_BBLEERR0_V << USB_D_BBLEERR0_S) 7107 #define USB_D_BBLEERR0_V 0x00000001 7108 #define USB_D_BBLEERR0_S 12 7109 /** USB_D_NAKINTRPT0 : R/W1C; bitpos: [13]; default: 0; 7110 * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or 7111 * received by the device 7112 * 0x0 : No interrupt 7113 * 0x1 : NAK Interrupt 7114 */ 7115 #define USB_D_NAKINTRPT0 (BIT(13)) 7116 #define USB_D_NAKINTRPT0_M (USB_D_NAKINTRPT0_V << USB_D_NAKINTRPT0_S) 7117 #define USB_D_NAKINTRPT0_V 0x00000001 7118 #define USB_D_NAKINTRPT0_S 13 7119 /** USB_D_NYETINTRPT0 : R/W1C; bitpos: [14]; default: 0; 7120 * NYET Interrupt. The core generates this interrupt when a NYET response is 7121 * transmitted for a non isochronous OUT endpoint 7122 * 0x0 : No interrupt 7123 * 0x1 : NYET Interrupt 7124 */ 7125 #define USB_D_NYETINTRPT0 (BIT(14)) 7126 #define USB_D_NYETINTRPT0_M (USB_D_NYETINTRPT0_V << USB_D_NYETINTRPT0_S) 7127 #define USB_D_NYETINTRPT0_V 0x00000001 7128 #define USB_D_NYETINTRPT0_S 14 7129 7130 7131 /** USB_DIEPINT1_REG register 7132 * Device IN Endpoint 1 Interrupt Register 7133 */ 7134 #define USB_DIEPINT1_REG (SOC_DPORT_USB_BASE + 0x928) 7135 /** USB_D_XFERCOMPL1 : R/W1C; bitpos: [0]; default: 0; 7136 * 0x0 : No Transfer Complete Interrupt 7137 * 0x1 : Transfer Completed Interrupt 7138 */ 7139 #define USB_D_XFERCOMPL1 (BIT(0)) 7140 #define USB_D_XFERCOMPL1_M (USB_D_XFERCOMPL1_V << USB_D_XFERCOMPL1_S) 7141 #define USB_D_XFERCOMPL1_V 0x00000001 7142 #define USB_D_XFERCOMPL1_S 0 7143 /** USB_D_EPDISBLD1 : R/W1C; bitpos: [1]; default: 0; 7144 * 0x0 : No Endpoint Disabled Interrupt 7145 * 0x1 : Endpoint Disabled Interrupt 7146 */ 7147 #define USB_D_EPDISBLD1 (BIT(1)) 7148 #define USB_D_EPDISBLD1_M (USB_D_EPDISBLD1_V << USB_D_EPDISBLD1_S) 7149 #define USB_D_EPDISBLD1_V 0x00000001 7150 #define USB_D_EPDISBLD1_S 1 7151 /** USB_D_AHBERR1 : R/W1C; bitpos: [2]; default: 0; 7152 * 0x0 : No AHB Error Interrupt 7153 * 0x1 : AHB Error interrupt 7154 */ 7155 #define USB_D_AHBERR1 (BIT(2)) 7156 #define USB_D_AHBERR1_M (USB_D_AHBERR1_V << USB_D_AHBERR1_S) 7157 #define USB_D_AHBERR1_V 0x00000001 7158 #define USB_D_AHBERR1_S 2 7159 /** USB_D_TIMEOUT1 : R/W1C; bitpos: [3]; default: 0; 7160 * 0x0 : No Timeout interrupt 7161 * 0x1 : Timeout interrupt 7162 */ 7163 #define USB_D_TIMEOUT1 (BIT(3)) 7164 #define USB_D_TIMEOUT1_M (USB_D_TIMEOUT1_V << USB_D_TIMEOUT1_S) 7165 #define USB_D_TIMEOUT1_V 0x00000001 7166 #define USB_D_TIMEOUT1_S 3 7167 /** USB_D_INTKNTXFEMP1 : R/W1C; bitpos: [4]; default: 0; 7168 * 0x0 : No IN Token Received when TxFIFO Empty Interrupt 7169 * 0x1 : IN Token Received when TxFIFO Empty Interrupt 7170 */ 7171 #define USB_D_INTKNTXFEMP1 (BIT(4)) 7172 #define USB_D_INTKNTXFEMP1_M (USB_D_INTKNTXFEMP1_V << USB_D_INTKNTXFEMP1_S) 7173 #define USB_D_INTKNTXFEMP1_V 0x00000001 7174 #define USB_D_INTKNTXFEMP1_S 4 7175 /** USB_D_INTKNEPMIS1 : R/W1C; bitpos: [5]; default: 0; 7176 * 0x0 : No IN Token Received with EP Mismatch Interrupt 7177 * 0x1 : IN Token Received with EP Mismatch interrupt 7178 */ 7179 #define USB_D_INTKNEPMIS1 (BIT(5)) 7180 #define USB_D_INTKNEPMIS1_M (USB_D_INTKNEPMIS1_V << USB_D_INTKNEPMIS1_S) 7181 #define USB_D_INTKNEPMIS1_V 0x00000001 7182 #define USB_D_INTKNEPMIS1_S 5 7183 /** USB_D_INEPNAKEFF1 : R/W1C; bitpos: [6]; default: 0; 7184 * IN Endpoint NAK Effective 7185 * 0x0 : No IN Endpoint NAK Effective interrupt 7186 * 0x1 : IN Endpoint NAK Effective interrupt 7187 */ 7188 #define USB_D_INEPNAKEFF1 (BIT(6)) 7189 #define USB_D_INEPNAKEFF1_M (USB_D_INEPNAKEFF1_V << USB_D_INEPNAKEFF1_S) 7190 #define USB_D_INEPNAKEFF1_V 0x00000001 7191 #define USB_D_INEPNAKEFF1_S 6 7192 /** USB_D_TXFEMP1 : RO; bitpos: [7]; default: 0; 7193 * This interrupt is asserted when the TxFIFO for this endpoint is either half or 7194 * completely empty 7195 * 0x0 : No Transmit FIFO Empty interrupt 7196 * 0x1 : Transmit FIFO Empty interrupt 7197 */ 7198 #define USB_D_TXFEMP1 (BIT(7)) 7199 #define USB_D_TXFEMP1_M (USB_D_TXFEMP1_V << USB_D_TXFEMP1_S) 7200 #define USB_D_TXFEMP1_V 0x00000001 7201 #define USB_D_TXFEMP1_S 7 7202 /** USB_D_TXFIFOUNDRN1 : R/W1C; bitpos: [8]; default: 0; 7203 * The core generates this interrupt when it detects a transmit FIFO underrun 7204 * condition in threshold mode for this endpoint 7205 * 0x0 : No Fifo Underrun interrupt 7206 * 0x1 : Fifo Underrun interrupt 7207 */ 7208 #define USB_D_TXFIFOUNDRN1 (BIT(8)) 7209 #define USB_D_TXFIFOUNDRN1_M (USB_D_TXFIFOUNDRN1_V << USB_D_TXFIFOUNDRN1_S) 7210 #define USB_D_TXFIFOUNDRN1_V 0x00000001 7211 #define USB_D_TXFIFOUNDRN1_S 8 7212 /** USB_D_BNAINTR1 : R/W1C; bitpos: [9]; default: 0; 7213 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates 7214 * this interrupt when the descriptor accessed is not ready for the Core to process, 7215 * such as Host busy or DMA done 7216 * 0x0 : No BNA interrupt 7217 * 0x1 : BNA interrupt 7218 */ 7219 #define USB_D_BNAINTR1 (BIT(9)) 7220 #define USB_D_BNAINTR1_M (USB_D_BNAINTR1_V << USB_D_BNAINTR1_S) 7221 #define USB_D_BNAINTR1_V 0x00000001 7222 #define USB_D_BNAINTR1_S 9 7223 /** USB_D_PKTDRPSTS1 : R/W1C; bitpos: [11]; default: 0; 7224 * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet 7225 * has been dropped. This bit does not have an associated mask bit and does not 7226 * generate an interrupt 7227 * 0x0 : No interrupt 7228 * 0x1 : Packet Drop Status 7229 */ 7230 #define USB_D_PKTDRPSTS1 (BIT(11)) 7231 #define USB_D_PKTDRPSTS1_M (USB_D_PKTDRPSTS1_V << USB_D_PKTDRPSTS1_S) 7232 #define USB_D_PKTDRPSTS1_V 0x00000001 7233 #define USB_D_PKTDRPSTS1_S 11 7234 /** USB_D_BBLEERR1 : R/W1C; bitpos: [12]; default: 0; 7235 * The core generates this interrupt when babble is received for the endpoint 7236 * 0x0 : No interrupt 7237 * 0x1 : BbleErr interrupt 7238 */ 7239 #define USB_D_BBLEERR1 (BIT(12)) 7240 #define USB_D_BBLEERR1_M (USB_D_BBLEERR1_V << USB_D_BBLEERR1_S) 7241 #define USB_D_BBLEERR1_V 0x00000001 7242 #define USB_D_BBLEERR1_S 12 7243 /** USB_D_NAKINTRPT1 : R/W1C; bitpos: [13]; default: 0; 7244 * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or 7245 * received by the device 7246 * 0x0 : No interrupt 7247 * 0x1 : NAK Interrupt 7248 */ 7249 #define USB_D_NAKINTRPT1 (BIT(13)) 7250 #define USB_D_NAKINTRPT1_M (USB_D_NAKINTRPT1_V << USB_D_NAKINTRPT1_S) 7251 #define USB_D_NAKINTRPT1_V 0x00000001 7252 #define USB_D_NAKINTRPT1_S 13 7253 /** USB_D_NYETINTRPT1 : R/W1C; bitpos: [14]; default: 0; 7254 * NYET Interrupt. The core generates this interrupt when a NYET response is 7255 * transmitted for a non isochronous OUT endpoint 7256 * 0x0 : No interrupt 7257 * 0x1 : NYET Interrupt 7258 */ 7259 #define USB_D_NYETINTRPT1 (BIT(14)) 7260 #define USB_D_NYETINTRPT1_M (USB_D_NYETINTRPT1_V << USB_D_NYETINTRPT1_S) 7261 #define USB_D_NYETINTRPT1_V 0x00000001 7262 #define USB_D_NYETINTRPT1_S 14 7263 7264 7265 /** USB_DIEPINT2_REG register 7266 * Device IN Endpoint 2 Interrupt Register 7267 */ 7268 #define USB_DIEPINT2_REG (SOC_DPORT_USB_BASE + 0x948) 7269 /** USB_D_XFERCOMPL2 : R/W1C; bitpos: [0]; default: 0; 7270 * 0x0 : No Transfer Complete Interrupt 7271 * 0x1 : Transfer Completed Interrupt 7272 */ 7273 #define USB_D_XFERCOMPL2 (BIT(0)) 7274 #define USB_D_XFERCOMPL2_M (USB_D_XFERCOMPL2_V << USB_D_XFERCOMPL2_S) 7275 #define USB_D_XFERCOMPL2_V 0x00000001 7276 #define USB_D_XFERCOMPL2_S 0 7277 /** USB_D_EPDISBLD2 : R/W1C; bitpos: [1]; default: 0; 7278 * 0x0 : No Endpoint Disabled Interrupt 7279 * 0x1 : Endpoint Disabled Interrupt 7280 */ 7281 #define USB_D_EPDISBLD2 (BIT(1)) 7282 #define USB_D_EPDISBLD2_M (USB_D_EPDISBLD2_V << USB_D_EPDISBLD2_S) 7283 #define USB_D_EPDISBLD2_V 0x00000001 7284 #define USB_D_EPDISBLD2_S 1 7285 /** USB_D_AHBERR2 : R/W1C; bitpos: [2]; default: 0; 7286 * 0x0 : No AHB Error Interrupt 7287 * 0x1 : AHB Error interrupt 7288 */ 7289 #define USB_D_AHBERR2 (BIT(2)) 7290 #define USB_D_AHBERR2_M (USB_D_AHBERR2_V << USB_D_AHBERR2_S) 7291 #define USB_D_AHBERR2_V 0x00000001 7292 #define USB_D_AHBERR2_S 2 7293 /** USB_D_TIMEOUT2 : R/W1C; bitpos: [3]; default: 0; 7294 * 0x0 : No Timeout interrupt 7295 * 0x1 : Timeout interrupt 7296 */ 7297 #define USB_D_TIMEOUT2 (BIT(3)) 7298 #define USB_D_TIMEOUT2_M (USB_D_TIMEOUT2_V << USB_D_TIMEOUT2_S) 7299 #define USB_D_TIMEOUT2_V 0x00000001 7300 #define USB_D_TIMEOUT2_S 3 7301 /** USB_D_INTKNTXFEMP2 : R/W1C; bitpos: [4]; default: 0; 7302 * 0x0 : No IN Token Received when TxFIFO Empty Interrupt 7303 * 0x1 : IN Token Received when TxFIFO Empty Interrupt 7304 */ 7305 #define USB_D_INTKNTXFEMP2 (BIT(4)) 7306 #define USB_D_INTKNTXFEMP2_M (USB_D_INTKNTXFEMP2_V << USB_D_INTKNTXFEMP2_S) 7307 #define USB_D_INTKNTXFEMP2_V 0x00000001 7308 #define USB_D_INTKNTXFEMP2_S 4 7309 /** USB_D_INTKNEPMIS2 : R/W1C; bitpos: [5]; default: 0; 7310 * 0x0 : No IN Token Received with EP Mismatch Interrupt 7311 * 0x1 : IN Token Received with EP Mismatch interrupt 7312 */ 7313 #define USB_D_INTKNEPMIS2 (BIT(5)) 7314 #define USB_D_INTKNEPMIS2_M (USB_D_INTKNEPMIS2_V << USB_D_INTKNEPMIS2_S) 7315 #define USB_D_INTKNEPMIS2_V 0x00000001 7316 #define USB_D_INTKNEPMIS2_S 5 7317 /** USB_D_INEPNAKEFF2 : R/W1C; bitpos: [6]; default: 0; 7318 * IN Endpoint NAK Effective 7319 * 0x0 : No IN Endpoint NAK Effective interrupt 7320 * 0x1 : IN Endpoint NAK Effective interrupt 7321 */ 7322 #define USB_D_INEPNAKEFF2 (BIT(6)) 7323 #define USB_D_INEPNAKEFF2_M (USB_D_INEPNAKEFF2_V << USB_D_INEPNAKEFF2_S) 7324 #define USB_D_INEPNAKEFF2_V 0x00000001 7325 #define USB_D_INEPNAKEFF2_S 6 7326 /** USB_D_TXFEMP2 : RO; bitpos: [7]; default: 0; 7327 * This interrupt is asserted when the TxFIFO for this endpoint is either half or 7328 * completely empty 7329 * 0x0 : No Transmit FIFO Empty interrupt 7330 * 0x1 : Transmit FIFO Empty interrupt 7331 */ 7332 #define USB_D_TXFEMP2 (BIT(7)) 7333 #define USB_D_TXFEMP2_M (USB_D_TXFEMP2_V << USB_D_TXFEMP2_S) 7334 #define USB_D_TXFEMP2_V 0x00000001 7335 #define USB_D_TXFEMP2_S 7 7336 /** USB_D_TXFIFOUNDRN2 : R/W1C; bitpos: [8]; default: 0; 7337 * The core generates this interrupt when it detects a transmit FIFO underrun 7338 * condition in threshold mode for this endpoint 7339 * 0x0 : No Fifo Underrun interrupt 7340 * 0x1 : Fifo Underrun interrupt 7341 */ 7342 #define USB_D_TXFIFOUNDRN2 (BIT(8)) 7343 #define USB_D_TXFIFOUNDRN2_M (USB_D_TXFIFOUNDRN2_V << USB_D_TXFIFOUNDRN2_S) 7344 #define USB_D_TXFIFOUNDRN2_V 0x00000001 7345 #define USB_D_TXFIFOUNDRN2_S 8 7346 /** USB_D_BNAINTR2 : R/W1C; bitpos: [9]; default: 0; 7347 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates 7348 * this interrupt when the descriptor accessed is not ready for the Core to process, 7349 * such as Host busy or DMA done 7350 * 0x0 : No BNA interrupt 7351 * 0x1 : BNA interrupt 7352 */ 7353 #define USB_D_BNAINTR2 (BIT(9)) 7354 #define USB_D_BNAINTR2_M (USB_D_BNAINTR2_V << USB_D_BNAINTR2_S) 7355 #define USB_D_BNAINTR2_V 0x00000001 7356 #define USB_D_BNAINTR2_S 9 7357 /** USB_D_PKTDRPSTS2 : R/W1C; bitpos: [11]; default: 0; 7358 * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet 7359 * has been dropped. This bit does not have an associated mask bit and does not 7360 * generate an interrupt 7361 * 0x0 : No interrupt 7362 * 0x1 : Packet Drop Status 7363 */ 7364 #define USB_D_PKTDRPSTS2 (BIT(11)) 7365 #define USB_D_PKTDRPSTS2_M (USB_D_PKTDRPSTS2_V << USB_D_PKTDRPSTS2_S) 7366 #define USB_D_PKTDRPSTS2_V 0x00000001 7367 #define USB_D_PKTDRPSTS2_S 11 7368 /** USB_D_BBLEERR2 : R/W1C; bitpos: [12]; default: 0; 7369 * The core generates this interrupt when babble is received for the endpoint 7370 * 0x0 : No interrupt 7371 * 0x1 : BbleErr interrupt 7372 */ 7373 #define USB_D_BBLEERR2 (BIT(12)) 7374 #define USB_D_BBLEERR2_M (USB_D_BBLEERR2_V << USB_D_BBLEERR2_S) 7375 #define USB_D_BBLEERR2_V 0x00000001 7376 #define USB_D_BBLEERR2_S 12 7377 /** USB_D_NAKINTRPT2 : R/W1C; bitpos: [13]; default: 0; 7378 * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or 7379 * received by the device 7380 * 0x0 : No interrupt 7381 * 0x1 : NAK Interrupt 7382 */ 7383 #define USB_D_NAKINTRPT2 (BIT(13)) 7384 #define USB_D_NAKINTRPT2_M (USB_D_NAKINTRPT2_V << USB_D_NAKINTRPT2_S) 7385 #define USB_D_NAKINTRPT2_V 0x00000001 7386 #define USB_D_NAKINTRPT2_S 13 7387 /** USB_D_NYETINTRPT2 : R/W1C; bitpos: [14]; default: 0; 7388 * NYET Interrupt. The core generates this interrupt when a NYET response is 7389 * transmitted for a non isochronous OUT endpoint 7390 * 0x0 : No interrupt 7391 * 0x1 : NYET Interrupt 7392 */ 7393 #define USB_D_NYETINTRPT2 (BIT(14)) 7394 #define USB_D_NYETINTRPT2_M (USB_D_NYETINTRPT2_V << USB_D_NYETINTRPT2_S) 7395 #define USB_D_NYETINTRPT2_V 0x00000001 7396 #define USB_D_NYETINTRPT2_S 14 7397 7398 7399 /** USB_DIEPINT3_REG register 7400 * Device IN Endpoint 3 Interrupt Register 7401 */ 7402 #define USB_DIEPINT3_REG (SOC_DPORT_USB_BASE + 0x968) 7403 /** USB_D_XFERCOMPL3 : R/W1C; bitpos: [0]; default: 0; 7404 * 0x0 : No Transfer Complete Interrupt 7405 * 0x1 : Transfer Completed Interrupt 7406 */ 7407 #define USB_D_XFERCOMPL3 (BIT(0)) 7408 #define USB_D_XFERCOMPL3_M (USB_D_XFERCOMPL3_V << USB_D_XFERCOMPL3_S) 7409 #define USB_D_XFERCOMPL3_V 0x00000001 7410 #define USB_D_XFERCOMPL3_S 0 7411 /** USB_D_EPDISBLD3 : R/W1C; bitpos: [1]; default: 0; 7412 * 0x0 : No Endpoint Disabled Interrupt 7413 * 0x1 : Endpoint Disabled Interrupt 7414 */ 7415 #define USB_D_EPDISBLD3 (BIT(1)) 7416 #define USB_D_EPDISBLD3_M (USB_D_EPDISBLD3_V << USB_D_EPDISBLD3_S) 7417 #define USB_D_EPDISBLD3_V 0x00000001 7418 #define USB_D_EPDISBLD3_S 1 7419 /** USB_D_AHBERR3 : R/W1C; bitpos: [2]; default: 0; 7420 * 0x0 : No AHB Error Interrupt 7421 * 0x1 : AHB Error interrupt 7422 */ 7423 #define USB_D_AHBERR3 (BIT(2)) 7424 #define USB_D_AHBERR3_M (USB_D_AHBERR3_V << USB_D_AHBERR3_S) 7425 #define USB_D_AHBERR3_V 0x00000001 7426 #define USB_D_AHBERR3_S 2 7427 /** USB_D_TIMEOUT3 : R/W1C; bitpos: [3]; default: 0; 7428 * 0x0 : No Timeout interrupt 7429 * 0x1 : Timeout interrupt 7430 */ 7431 #define USB_D_TIMEOUT3 (BIT(3)) 7432 #define USB_D_TIMEOUT3_M (USB_D_TIMEOUT3_V << USB_D_TIMEOUT3_S) 7433 #define USB_D_TIMEOUT3_V 0x00000001 7434 #define USB_D_TIMEOUT3_S 3 7435 /** USB_D_INTKNTXFEMP3 : R/W1C; bitpos: [4]; default: 0; 7436 * 0x0 : No IN Token Received when TxFIFO Empty Interrupt 7437 * 0x1 : IN Token Received when TxFIFO Empty Interrupt 7438 */ 7439 #define USB_D_INTKNTXFEMP3 (BIT(4)) 7440 #define USB_D_INTKNTXFEMP3_M (USB_D_INTKNTXFEMP3_V << USB_D_INTKNTXFEMP3_S) 7441 #define USB_D_INTKNTXFEMP3_V 0x00000001 7442 #define USB_D_INTKNTXFEMP3_S 4 7443 /** USB_D_INTKNEPMIS3 : R/W1C; bitpos: [5]; default: 0; 7444 * 0x0 : No IN Token Received with EP Mismatch Interrupt 7445 * 0x1 : IN Token Received with EP Mismatch interrupt 7446 */ 7447 #define USB_D_INTKNEPMIS3 (BIT(5)) 7448 #define USB_D_INTKNEPMIS3_M (USB_D_INTKNEPMIS3_V << USB_D_INTKNEPMIS3_S) 7449 #define USB_D_INTKNEPMIS3_V 0x00000001 7450 #define USB_D_INTKNEPMIS3_S 5 7451 /** USB_D_INEPNAKEFF3 : R/W1C; bitpos: [6]; default: 0; 7452 * IN Endpoint NAK Effective 7453 * 0x0 : No IN Endpoint NAK Effective interrupt 7454 * 0x1 : IN Endpoint NAK Effective interrupt 7455 */ 7456 #define USB_D_INEPNAKEFF3 (BIT(6)) 7457 #define USB_D_INEPNAKEFF3_M (USB_D_INEPNAKEFF3_V << USB_D_INEPNAKEFF3_S) 7458 #define USB_D_INEPNAKEFF3_V 0x00000001 7459 #define USB_D_INEPNAKEFF3_S 6 7460 /** USB_D_TXFEMP3 : RO; bitpos: [7]; default: 0; 7461 * This interrupt is asserted when the TxFIFO for this endpoint is either half or 7462 * completely empty 7463 * 0x0 : No Transmit FIFO Empty interrupt 7464 * 0x1 : Transmit FIFO Empty interrupt 7465 */ 7466 #define USB_D_TXFEMP3 (BIT(7)) 7467 #define USB_D_TXFEMP3_M (USB_D_TXFEMP3_V << USB_D_TXFEMP3_S) 7468 #define USB_D_TXFEMP3_V 0x00000001 7469 #define USB_D_TXFEMP3_S 7 7470 /** USB_D_TXFIFOUNDRN3 : R/W1C; bitpos: [8]; default: 0; 7471 * The core generates this interrupt when it detects a transmit FIFO underrun 7472 * condition in threshold mode for this endpoint 7473 * 0x0 : No Fifo Underrun interrupt 7474 * 0x1 : Fifo Underrun interrupt 7475 */ 7476 #define USB_D_TXFIFOUNDRN3 (BIT(8)) 7477 #define USB_D_TXFIFOUNDRN3_M (USB_D_TXFIFOUNDRN3_V << USB_D_TXFIFOUNDRN3_S) 7478 #define USB_D_TXFIFOUNDRN3_V 0x00000001 7479 #define USB_D_TXFIFOUNDRN3_S 8 7480 /** USB_D_BNAINTR3 : R/W1C; bitpos: [9]; default: 0; 7481 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates 7482 * this interrupt when the descriptor accessed is not ready for the Core to process, 7483 * such as Host busy or DMA done 7484 * 0x0 : No BNA interrupt 7485 * 0x1 : BNA interrupt 7486 */ 7487 #define USB_D_BNAINTR3 (BIT(9)) 7488 #define USB_D_BNAINTR3_M (USB_D_BNAINTR3_V << USB_D_BNAINTR3_S) 7489 #define USB_D_BNAINTR3_V 0x00000001 7490 #define USB_D_BNAINTR3_S 9 7491 /** USB_D_PKTDRPSTS3 : R/W1C; bitpos: [11]; default: 0; 7492 * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet 7493 * has been dropped. This bit does not have an associated mask bit and does not 7494 * generate an interrupt 7495 * 0x0 : No interrupt 7496 * 0x1 : Packet Drop Status 7497 */ 7498 #define USB_D_PKTDRPSTS3 (BIT(11)) 7499 #define USB_D_PKTDRPSTS3_M (USB_D_PKTDRPSTS3_V << USB_D_PKTDRPSTS3_S) 7500 #define USB_D_PKTDRPSTS3_V 0x00000001 7501 #define USB_D_PKTDRPSTS3_S 11 7502 /** USB_D_BBLEERR3 : R/W1C; bitpos: [12]; default: 0; 7503 * The core generates this interrupt when babble is received for the endpoint 7504 * 0x0 : No interrupt 7505 * 0x1 : BbleErr interrupt 7506 */ 7507 #define USB_D_BBLEERR3 (BIT(12)) 7508 #define USB_D_BBLEERR3_M (USB_D_BBLEERR3_V << USB_D_BBLEERR3_S) 7509 #define USB_D_BBLEERR3_V 0x00000001 7510 #define USB_D_BBLEERR3_S 12 7511 /** USB_D_NAKINTRPT3 : R/W1C; bitpos: [13]; default: 0; 7512 * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or 7513 * received by the device 7514 * 0x0 : No interrupt 7515 * 0x1 : NAK Interrupt 7516 */ 7517 #define USB_D_NAKINTRPT3 (BIT(13)) 7518 #define USB_D_NAKINTRPT3_M (USB_D_NAKINTRPT3_V << USB_D_NAKINTRPT3_S) 7519 #define USB_D_NAKINTRPT3_V 0x00000001 7520 #define USB_D_NAKINTRPT3_S 13 7521 /** USB_D_NYETINTRPT3 : R/W1C; bitpos: [14]; default: 0; 7522 * NYET Interrupt. The core generates this interrupt when a NYET response is 7523 * transmitted for a non isochronous OUT endpoint 7524 * 0x0 : No interrupt 7525 * 0x1 : NYET Interrupt 7526 */ 7527 #define USB_D_NYETINTRPT3 (BIT(14)) 7528 #define USB_D_NYETINTRPT3_M (USB_D_NYETINTRPT3_V << USB_D_NYETINTRPT3_S) 7529 #define USB_D_NYETINTRPT3_V 0x00000001 7530 #define USB_D_NYETINTRPT3_S 14 7531 7532 7533 /** USB_DIEPINT4_REG register 7534 * Device IN Endpoint 4 Interrupt Register 7535 */ 7536 #define USB_DIEPINT4_REG (SOC_DPORT_USB_BASE + 0x988) 7537 /** USB_D_XFERCOMPL4 : R/W1C; bitpos: [0]; default: 0; 7538 * 0x0 : No Transfer Complete Interrupt 7539 * 0x1 : Transfer Completed Interrupt 7540 */ 7541 #define USB_D_XFERCOMPL4 (BIT(0)) 7542 #define USB_D_XFERCOMPL4_M (USB_D_XFERCOMPL4_V << USB_D_XFERCOMPL4_S) 7543 #define USB_D_XFERCOMPL4_V 0x00000001 7544 #define USB_D_XFERCOMPL4_S 0 7545 /** USB_D_EPDISBLD4 : R/W1C; bitpos: [1]; default: 0; 7546 * 0x0 : No Endpoint Disabled Interrupt 7547 * 0x1 : Endpoint Disabled Interrupt 7548 */ 7549 #define USB_D_EPDISBLD4 (BIT(1)) 7550 #define USB_D_EPDISBLD4_M (USB_D_EPDISBLD4_V << USB_D_EPDISBLD4_S) 7551 #define USB_D_EPDISBLD4_V 0x00000001 7552 #define USB_D_EPDISBLD4_S 1 7553 /** USB_D_AHBERR4 : R/W1C; bitpos: [2]; default: 0; 7554 * 0x0 : No AHB Error Interrupt 7555 * 0x1 : AHB Error interrupt 7556 */ 7557 #define USB_D_AHBERR4 (BIT(2)) 7558 #define USB_D_AHBERR4_M (USB_D_AHBERR4_V << USB_D_AHBERR4_S) 7559 #define USB_D_AHBERR4_V 0x00000001 7560 #define USB_D_AHBERR4_S 2 7561 /** USB_D_TIMEOUT4 : R/W1C; bitpos: [3]; default: 0; 7562 * 0x0 : No Timeout interrupt 7563 * 0x1 : Timeout interrupt 7564 */ 7565 #define USB_D_TIMEOUT4 (BIT(3)) 7566 #define USB_D_TIMEOUT4_M (USB_D_TIMEOUT4_V << USB_D_TIMEOUT4_S) 7567 #define USB_D_TIMEOUT4_V 0x00000001 7568 #define USB_D_TIMEOUT4_S 3 7569 /** USB_D_INTKNTXFEMP4 : R/W1C; bitpos: [4]; default: 0; 7570 * 0x0 : No IN Token Received when TxFIFO Empty Interrupt 7571 * 0x1 : IN Token Received when TxFIFO Empty Interrupt 7572 */ 7573 #define USB_D_INTKNTXFEMP4 (BIT(4)) 7574 #define USB_D_INTKNTXFEMP4_M (USB_D_INTKNTXFEMP4_V << USB_D_INTKNTXFEMP4_S) 7575 #define USB_D_INTKNTXFEMP4_V 0x00000001 7576 #define USB_D_INTKNTXFEMP4_S 4 7577 /** USB_D_INTKNEPMIS4 : R/W1C; bitpos: [5]; default: 0; 7578 * 0x0 : No IN Token Received with EP Mismatch Interrupt 7579 * 0x1 : IN Token Received with EP Mismatch interrupt 7580 */ 7581 #define USB_D_INTKNEPMIS4 (BIT(5)) 7582 #define USB_D_INTKNEPMIS4_M (USB_D_INTKNEPMIS4_V << USB_D_INTKNEPMIS4_S) 7583 #define USB_D_INTKNEPMIS4_V 0x00000001 7584 #define USB_D_INTKNEPMIS4_S 5 7585 /** USB_D_INEPNAKEFF4 : R/W1C; bitpos: [6]; default: 0; 7586 * IN Endpoint NAK Effective 7587 * 0x0 : No IN Endpoint NAK Effective interrupt 7588 * 0x1 : IN Endpoint NAK Effective interrupt 7589 */ 7590 #define USB_D_INEPNAKEFF4 (BIT(6)) 7591 #define USB_D_INEPNAKEFF4_M (USB_D_INEPNAKEFF4_V << USB_D_INEPNAKEFF4_S) 7592 #define USB_D_INEPNAKEFF4_V 0x00000001 7593 #define USB_D_INEPNAKEFF4_S 6 7594 /** USB_D_TXFEMP4 : RO; bitpos: [7]; default: 0; 7595 * This interrupt is asserted when the TxFIFO for this endpoint is either half or 7596 * completely empty 7597 * 0x0 : No Transmit FIFO Empty interrupt 7598 * 0x1 : Transmit FIFO Empty interrupt 7599 */ 7600 #define USB_D_TXFEMP4 (BIT(7)) 7601 #define USB_D_TXFEMP4_M (USB_D_TXFEMP4_V << USB_D_TXFEMP4_S) 7602 #define USB_D_TXFEMP4_V 0x00000001 7603 #define USB_D_TXFEMP4_S 7 7604 /** USB_D_TXFIFOUNDRN4 : R/W1C; bitpos: [8]; default: 0; 7605 * The core generates this interrupt when it detects a transmit FIFO underrun 7606 * condition in threshold mode for this endpoint 7607 * 0x0 : No Fifo Underrun interrupt 7608 * 0x1 : Fifo Underrun interrupt 7609 */ 7610 #define USB_D_TXFIFOUNDRN4 (BIT(8)) 7611 #define USB_D_TXFIFOUNDRN4_M (USB_D_TXFIFOUNDRN4_V << USB_D_TXFIFOUNDRN4_S) 7612 #define USB_D_TXFIFOUNDRN4_V 0x00000001 7613 #define USB_D_TXFIFOUNDRN4_S 8 7614 /** USB_D_BNAINTR4 : R/W1C; bitpos: [9]; default: 0; 7615 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates 7616 * this interrupt when the descriptor accessed is not ready for the Core to process, 7617 * such as Host busy or DMA done 7618 * 0x0 : No BNA interrupt 7619 * 0x1 : BNA interrupt 7620 */ 7621 #define USB_D_BNAINTR4 (BIT(9)) 7622 #define USB_D_BNAINTR4_M (USB_D_BNAINTR4_V << USB_D_BNAINTR4_S) 7623 #define USB_D_BNAINTR4_V 0x00000001 7624 #define USB_D_BNAINTR4_S 9 7625 /** USB_D_PKTDRPSTS4 : R/W1C; bitpos: [11]; default: 0; 7626 * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet 7627 * has been dropped. This bit does not have an associated mask bit and does not 7628 * generate an interrupt 7629 * 0x0 : No interrupt 7630 * 0x1 : Packet Drop Status 7631 */ 7632 #define USB_D_PKTDRPSTS4 (BIT(11)) 7633 #define USB_D_PKTDRPSTS4_M (USB_D_PKTDRPSTS4_V << USB_D_PKTDRPSTS4_S) 7634 #define USB_D_PKTDRPSTS4_V 0x00000001 7635 #define USB_D_PKTDRPSTS4_S 11 7636 /** USB_D_BBLEERR4 : R/W1C; bitpos: [12]; default: 0; 7637 * The core generates this interrupt when babble is received for the endpoint 7638 * 0x0 : No interrupt 7639 * 0x1 : BbleErr interrupt 7640 */ 7641 #define USB_D_BBLEERR4 (BIT(12)) 7642 #define USB_D_BBLEERR4_M (USB_D_BBLEERR4_V << USB_D_BBLEERR4_S) 7643 #define USB_D_BBLEERR4_V 0x00000001 7644 #define USB_D_BBLEERR4_S 12 7645 /** USB_D_NAKINTRPT4 : R/W1C; bitpos: [13]; default: 0; 7646 * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or 7647 * received by the device 7648 * 0x0 : No interrupt 7649 * 0x1 : NAK Interrupt 7650 */ 7651 #define USB_D_NAKINTRPT4 (BIT(13)) 7652 #define USB_D_NAKINTRPT4_M (USB_D_NAKINTRPT4_V << USB_D_NAKINTRPT4_S) 7653 #define USB_D_NAKINTRPT4_V 0x00000001 7654 #define USB_D_NAKINTRPT4_S 13 7655 /** USB_D_NYETINTRPT4 : R/W1C; bitpos: [14]; default: 0; 7656 * NYET Interrupt. The core generates this interrupt when a NYET response is 7657 * transmitted for a non isochronous OUT endpoint 7658 * 0x0 : No interrupt 7659 * 0x1 : NYET Interrupt 7660 */ 7661 #define USB_D_NYETINTRPT4 (BIT(14)) 7662 #define USB_D_NYETINTRPT4_M (USB_D_NYETINTRPT4_V << USB_D_NYETINTRPT4_S) 7663 #define USB_D_NYETINTRPT4_V 0x00000001 7664 #define USB_D_NYETINTRPT4_S 14 7665 7666 7667 /** USB_DIEPINT5_REG register 7668 * Device IN Endpoint 5 Interrupt Register 7669 */ 7670 #define USB_DIEPINT5_REG (SOC_DPORT_USB_BASE + 0x9a8) 7671 /** USB_D_XFERCOMPL5 : R/W1C; bitpos: [0]; default: 0; 7672 * 0x0 : No Transfer Complete Interrupt 7673 * 0x1 : Transfer Completed Interrupt 7674 */ 7675 #define USB_D_XFERCOMPL5 (BIT(0)) 7676 #define USB_D_XFERCOMPL5_M (USB_D_XFERCOMPL5_V << USB_D_XFERCOMPL5_S) 7677 #define USB_D_XFERCOMPL5_V 0x00000001 7678 #define USB_D_XFERCOMPL5_S 0 7679 /** USB_D_EPDISBLD5 : R/W1C; bitpos: [1]; default: 0; 7680 * 0x0 : No Endpoint Disabled Interrupt 7681 * 0x1 : Endpoint Disabled Interrupt 7682 */ 7683 #define USB_D_EPDISBLD5 (BIT(1)) 7684 #define USB_D_EPDISBLD5_M (USB_D_EPDISBLD5_V << USB_D_EPDISBLD5_S) 7685 #define USB_D_EPDISBLD5_V 0x00000001 7686 #define USB_D_EPDISBLD5_S 1 7687 /** USB_D_AHBERR5 : R/W1C; bitpos: [2]; default: 0; 7688 * 0x0 : No AHB Error Interrupt 7689 * 0x1 : AHB Error interrupt 7690 */ 7691 #define USB_D_AHBERR5 (BIT(2)) 7692 #define USB_D_AHBERR5_M (USB_D_AHBERR5_V << USB_D_AHBERR5_S) 7693 #define USB_D_AHBERR5_V 0x00000001 7694 #define USB_D_AHBERR5_S 2 7695 /** USB_D_TIMEOUT5 : R/W1C; bitpos: [3]; default: 0; 7696 * 0x0 : No Timeout interrupt 7697 * 0x1 : Timeout interrupt 7698 */ 7699 #define USB_D_TIMEOUT5 (BIT(3)) 7700 #define USB_D_TIMEOUT5_M (USB_D_TIMEOUT5_V << USB_D_TIMEOUT5_S) 7701 #define USB_D_TIMEOUT5_V 0x00000001 7702 #define USB_D_TIMEOUT5_S 3 7703 /** USB_D_INTKNTXFEMP5 : R/W1C; bitpos: [4]; default: 0; 7704 * 0x0 : No IN Token Received when TxFIFO Empty Interrupt 7705 * 0x1 : IN Token Received when TxFIFO Empty Interrupt 7706 */ 7707 #define USB_D_INTKNTXFEMP5 (BIT(4)) 7708 #define USB_D_INTKNTXFEMP5_M (USB_D_INTKNTXFEMP5_V << USB_D_INTKNTXFEMP5_S) 7709 #define USB_D_INTKNTXFEMP5_V 0x00000001 7710 #define USB_D_INTKNTXFEMP5_S 4 7711 /** USB_D_INTKNEPMIS5 : R/W1C; bitpos: [5]; default: 0; 7712 * 0x0 : No IN Token Received with EP Mismatch Interrupt 7713 * 0x1 : IN Token Received with EP Mismatch interrupt 7714 */ 7715 #define USB_D_INTKNEPMIS5 (BIT(5)) 7716 #define USB_D_INTKNEPMIS5_M (USB_D_INTKNEPMIS5_V << USB_D_INTKNEPMIS5_S) 7717 #define USB_D_INTKNEPMIS5_V 0x00000001 7718 #define USB_D_INTKNEPMIS5_S 5 7719 /** USB_D_INEPNAKEFF5 : R/W1C; bitpos: [6]; default: 0; 7720 * IN Endpoint NAK Effective 7721 * 0x0 : No IN Endpoint NAK Effective interrupt 7722 * 0x1 : IN Endpoint NAK Effective interrupt 7723 */ 7724 #define USB_D_INEPNAKEFF5 (BIT(6)) 7725 #define USB_D_INEPNAKEFF5_M (USB_D_INEPNAKEFF5_V << USB_D_INEPNAKEFF5_S) 7726 #define USB_D_INEPNAKEFF5_V 0x00000001 7727 #define USB_D_INEPNAKEFF5_S 6 7728 /** USB_D_TXFEMP5 : RO; bitpos: [7]; default: 0; 7729 * This interrupt is asserted when the TxFIFO for this endpoint is either half or 7730 * completely empty 7731 * 0x0 : No Transmit FIFO Empty interrupt 7732 * 0x1 : Transmit FIFO Empty interrupt 7733 */ 7734 #define USB_D_TXFEMP5 (BIT(7)) 7735 #define USB_D_TXFEMP5_M (USB_D_TXFEMP5_V << USB_D_TXFEMP5_S) 7736 #define USB_D_TXFEMP5_V 0x00000001 7737 #define USB_D_TXFEMP5_S 7 7738 /** USB_D_TXFIFOUNDRN5 : R/W1C; bitpos: [8]; default: 0; 7739 * The core generates this interrupt when it detects a transmit FIFO underrun 7740 * condition in threshold mode for this endpoint 7741 * 0x0 : No Fifo Underrun interrupt 7742 * 0x1 : Fifo Underrun interrupt 7743 */ 7744 #define USB_D_TXFIFOUNDRN5 (BIT(8)) 7745 #define USB_D_TXFIFOUNDRN5_M (USB_D_TXFIFOUNDRN5_V << USB_D_TXFIFOUNDRN5_S) 7746 #define USB_D_TXFIFOUNDRN5_V 0x00000001 7747 #define USB_D_TXFIFOUNDRN5_S 8 7748 /** USB_D_BNAINTR5 : R/W1C; bitpos: [9]; default: 0; 7749 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates 7750 * this interrupt when the descriptor accessed is not ready for the Core to process, 7751 * such as Host busy or DMA done 7752 * 0x0 : No BNA interrupt 7753 * 0x1 : BNA interrupt 7754 */ 7755 #define USB_D_BNAINTR5 (BIT(9)) 7756 #define USB_D_BNAINTR5_M (USB_D_BNAINTR5_V << USB_D_BNAINTR5_S) 7757 #define USB_D_BNAINTR5_V 0x00000001 7758 #define USB_D_BNAINTR5_S 9 7759 /** USB_D_PKTDRPSTS5 : R/W1C; bitpos: [11]; default: 0; 7760 * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet 7761 * has been dropped. This bit does not have an associated mask bit and does not 7762 * generate an interrupt 7763 * 0x0 : No interrupt 7764 * 0x1 : Packet Drop Status 7765 */ 7766 #define USB_D_PKTDRPSTS5 (BIT(11)) 7767 #define USB_D_PKTDRPSTS5_M (USB_D_PKTDRPSTS5_V << USB_D_PKTDRPSTS5_S) 7768 #define USB_D_PKTDRPSTS5_V 0x00000001 7769 #define USB_D_PKTDRPSTS5_S 11 7770 /** USB_D_BBLEERR5 : R/W1C; bitpos: [12]; default: 0; 7771 * The core generates this interrupt when babble is received for the endpoint 7772 * 0x0 : No interrupt 7773 * 0x1 : BbleErr interrupt 7774 */ 7775 #define USB_D_BBLEERR5 (BIT(12)) 7776 #define USB_D_BBLEERR5_M (USB_D_BBLEERR5_V << USB_D_BBLEERR5_S) 7777 #define USB_D_BBLEERR5_V 0x00000001 7778 #define USB_D_BBLEERR5_S 12 7779 /** USB_D_NAKINTRPT5 : R/W1C; bitpos: [13]; default: 0; 7780 * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or 7781 * received by the device 7782 * 0x0 : No interrupt 7783 * 0x1 : NAK Interrupt 7784 */ 7785 #define USB_D_NAKINTRPT5 (BIT(13)) 7786 #define USB_D_NAKINTRPT5_M (USB_D_NAKINTRPT5_V << USB_D_NAKINTRPT5_S) 7787 #define USB_D_NAKINTRPT5_V 0x00000001 7788 #define USB_D_NAKINTRPT5_S 13 7789 /** USB_D_NYETINTRPT5 : R/W1C; bitpos: [14]; default: 0; 7790 * NYET Interrupt. The core generates this interrupt when a NYET response is 7791 * transmitted for a non isochronous OUT endpoint 7792 * 0x0 : No interrupt 7793 * 0x1 : NYET Interrupt 7794 */ 7795 #define USB_D_NYETINTRPT5 (BIT(14)) 7796 #define USB_D_NYETINTRPT5_M (USB_D_NYETINTRPT5_V << USB_D_NYETINTRPT5_S) 7797 #define USB_D_NYETINTRPT5_V 0x00000001 7798 #define USB_D_NYETINTRPT5_S 14 7799 7800 7801 /** USB_DIEPINT6_REG register 7802 * Device IN Endpoint 6 Interrupt Register 7803 */ 7804 #define USB_DIEPINT6_REG (SOC_DPORT_USB_BASE + 0x9c8) 7805 /** USB_D_XFERCOMPL6 : R/W1C; bitpos: [0]; default: 0; 7806 * 0x0 : No Transfer Complete Interrupt 7807 * 0x1 : Transfer Completed Interrupt 7808 */ 7809 #define USB_D_XFERCOMPL6 (BIT(0)) 7810 #define USB_D_XFERCOMPL6_M (USB_D_XFERCOMPL6_V << USB_D_XFERCOMPL6_S) 7811 #define USB_D_XFERCOMPL6_V 0x00000001 7812 #define USB_D_XFERCOMPL6_S 0 7813 /** USB_D_EPDISBLD6 : R/W1C; bitpos: [1]; default: 0; 7814 * 0x0 : No Endpoint Disabled Interrupt 7815 * 0x1 : Endpoint Disabled Interrupt 7816 */ 7817 #define USB_D_EPDISBLD6 (BIT(1)) 7818 #define USB_D_EPDISBLD6_M (USB_D_EPDISBLD6_V << USB_D_EPDISBLD6_S) 7819 #define USB_D_EPDISBLD6_V 0x00000001 7820 #define USB_D_EPDISBLD6_S 1 7821 /** USB_D_AHBERR6 : R/W1C; bitpos: [2]; default: 0; 7822 * 0x0 : No AHB Error Interrupt 7823 * 0x1 : AHB Error interrupt 7824 */ 7825 #define USB_D_AHBERR6 (BIT(2)) 7826 #define USB_D_AHBERR6_M (USB_D_AHBERR6_V << USB_D_AHBERR6_S) 7827 #define USB_D_AHBERR6_V 0x00000001 7828 #define USB_D_AHBERR6_S 2 7829 /** USB_D_TIMEOUT6 : R/W1C; bitpos: [3]; default: 0; 7830 * 0x0 : No Timeout interrupt 7831 * 0x1 : Timeout interrupt 7832 */ 7833 #define USB_D_TIMEOUT6 (BIT(3)) 7834 #define USB_D_TIMEOUT6_M (USB_D_TIMEOUT6_V << USB_D_TIMEOUT6_S) 7835 #define USB_D_TIMEOUT6_V 0x00000001 7836 #define USB_D_TIMEOUT6_S 3 7837 /** USB_D_INTKNTXFEMP6 : R/W1C; bitpos: [4]; default: 0; 7838 * 0x0 : No IN Token Received when TxFIFO Empty Interrupt 7839 * 0x1 : IN Token Received when TxFIFO Empty Interrupt 7840 */ 7841 #define USB_D_INTKNTXFEMP6 (BIT(4)) 7842 #define USB_D_INTKNTXFEMP6_M (USB_D_INTKNTXFEMP6_V << USB_D_INTKNTXFEMP6_S) 7843 #define USB_D_INTKNTXFEMP6_V 0x00000001 7844 #define USB_D_INTKNTXFEMP6_S 4 7845 /** USB_D_INTKNEPMIS6 : R/W1C; bitpos: [5]; default: 0; 7846 * 0x0 : No IN Token Received with EP Mismatch Interrupt 7847 * 0x1 : IN Token Received with EP Mismatch interrupt 7848 */ 7849 #define USB_D_INTKNEPMIS6 (BIT(5)) 7850 #define USB_D_INTKNEPMIS6_M (USB_D_INTKNEPMIS6_V << USB_D_INTKNEPMIS6_S) 7851 #define USB_D_INTKNEPMIS6_V 0x00000001 7852 #define USB_D_INTKNEPMIS6_S 5 7853 /** USB_D_INEPNAKEFF6 : R/W1C; bitpos: [6]; default: 0; 7854 * IN Endpoint NAK Effective 7855 * 0x0 : No IN Endpoint NAK Effective interrupt 7856 * 0x1 : IN Endpoint NAK Effective interrupt 7857 */ 7858 #define USB_D_INEPNAKEFF6 (BIT(6)) 7859 #define USB_D_INEPNAKEFF6_M (USB_D_INEPNAKEFF6_V << USB_D_INEPNAKEFF6_S) 7860 #define USB_D_INEPNAKEFF6_V 0x00000001 7861 #define USB_D_INEPNAKEFF6_S 6 7862 /** USB_D_TXFEMP6 : RO; bitpos: [7]; default: 0; 7863 * This interrupt is asserted when the TxFIFO for this endpoint is either half or 7864 * completely empty 7865 * 0x0 : No Transmit FIFO Empty interrupt 7866 * 0x1 : Transmit FIFO Empty interrupt 7867 */ 7868 #define USB_D_TXFEMP6 (BIT(7)) 7869 #define USB_D_TXFEMP6_M (USB_D_TXFEMP6_V << USB_D_TXFEMP6_S) 7870 #define USB_D_TXFEMP6_V 0x00000001 7871 #define USB_D_TXFEMP6_S 7 7872 /** USB_D_TXFIFOUNDRN6 : R/W1C; bitpos: [8]; default: 0; 7873 * The core generates this interrupt when it detects a transmit FIFO underrun 7874 * condition in threshold mode for this endpoint 7875 * 0x0 : No Fifo Underrun interrupt 7876 * 0x1 : Fifo Underrun interrupt 7877 */ 7878 #define USB_D_TXFIFOUNDRN6 (BIT(8)) 7879 #define USB_D_TXFIFOUNDRN6_M (USB_D_TXFIFOUNDRN6_V << USB_D_TXFIFOUNDRN6_S) 7880 #define USB_D_TXFIFOUNDRN6_V 0x00000001 7881 #define USB_D_TXFIFOUNDRN6_S 8 7882 /** USB_D_BNAINTR6 : R/W1C; bitpos: [9]; default: 0; 7883 * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates 7884 * this interrupt when the descriptor accessed is not ready for the Core to process, 7885 * such as Host busy or DMA done 7886 * 0x0 : No BNA interrupt 7887 * 0x1 : BNA interrupt 7888 */ 7889 #define USB_D_BNAINTR6 (BIT(9)) 7890 #define USB_D_BNAINTR6_M (USB_D_BNAINTR6_V << USB_D_BNAINTR6_S) 7891 #define USB_D_BNAINTR6_V 0x00000001 7892 #define USB_D_BNAINTR6_S 9 7893 /** USB_D_PKTDRPSTS6 : R/W1C; bitpos: [11]; default: 0; 7894 * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet 7895 * has been dropped. This bit does not have an associated mask bit and does not 7896 * generate an interrupt 7897 * 0x0 : No interrupt 7898 * 0x1 : Packet Drop Status 7899 */ 7900 #define USB_D_PKTDRPSTS6 (BIT(11)) 7901 #define USB_D_PKTDRPSTS6_M (USB_D_PKTDRPSTS6_V << USB_D_PKTDRPSTS6_S) 7902 #define USB_D_PKTDRPSTS6_V 0x00000001 7903 #define USB_D_PKTDRPSTS6_S 11 7904 /** USB_D_BBLEERR6 : R/W1C; bitpos: [12]; default: 0; 7905 * The core generates this interrupt when babble is received for the endpoint 7906 * 0x0 : No interrupt 7907 * 0x1 : BbleErr interrupt 7908 */ 7909 #define USB_D_BBLEERR6 (BIT(12)) 7910 #define USB_D_BBLEERR6_M (USB_D_BBLEERR6_V << USB_D_BBLEERR6_S) 7911 #define USB_D_BBLEERR6_V 0x00000001 7912 #define USB_D_BBLEERR6_S 12 7913 /** USB_D_NAKINTRPT6 : R/W1C; bitpos: [13]; default: 0; 7914 * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or 7915 * received by the device 7916 * 0x0 : No interrupt 7917 * 0x1 : NAK Interrupt 7918 */ 7919 #define USB_D_NAKINTRPT6 (BIT(13)) 7920 #define USB_D_NAKINTRPT6_M (USB_D_NAKINTRPT6_V << USB_D_NAKINTRPT6_S) 7921 #define USB_D_NAKINTRPT6_V 0x00000001 7922 #define USB_D_NAKINTRPT6_S 13 7923 /** USB_D_NYETINTRPT6 : R/W1C; bitpos: [14]; default: 0; 7924 * NYET Interrupt. The core generates this interrupt when a NYET response is 7925 * transmitted for a non isochronous OUT endpoint 7926 * 0x0 : No interrupt 7927 * 0x1 : NYET Interrupt 7928 */ 7929 #define USB_D_NYETINTRPT6 (BIT(14)) 7930 #define USB_D_NYETINTRPT6_M (USB_D_NYETINTRPT6_V << USB_D_NYETINTRPT6_S) 7931 #define USB_D_NYETINTRPT6_V 0x00000001 7932 #define USB_D_NYETINTRPT6_S 14 7933 7934 7935 /** USB_DOEPINT0_REG register 7936 * Device OUT Endpoint 0 Interrupt Register 7937 */ 7938 #define USB_DOEPINT0_REG (SOC_DPORT_USB_BASE + 0xb08) 7939 /** USB_XFERCOMPL0 : R/W1C; bitpos: [0]; default: 0; 7940 * Transfer Completed Interrupt 7941 * 0x0 : No Transfer Complete Interrupt 7942 * 0x1 : Transfer Complete Interrupt 7943 */ 7944 #define USB_XFERCOMPL0 (BIT(0)) 7945 #define USB_XFERCOMPL0_M (USB_XFERCOMPL0_V << USB_XFERCOMPL0_S) 7946 #define USB_XFERCOMPL0_V 0x00000001 7947 #define USB_XFERCOMPL0_S 0 7948 /** USB_EPDISBLD0 : R/W1C; bitpos: [1]; default: 0; 7949 * Endpoint Disabled Interrupt 7950 * 0x0 : No Endpoint Disabled Interrupt 7951 * 0x1 : Endpoint Disabled Interrupt 7952 */ 7953 #define USB_EPDISBLD0 (BIT(1)) 7954 #define USB_EPDISBLD0_M (USB_EPDISBLD0_V << USB_EPDISBLD0_S) 7955 #define USB_EPDISBLD0_V 0x00000001 7956 #define USB_EPDISBLD0_S 1 7957 /** USB_AHBERR0 : R/W1C; bitpos: [2]; default: 0; 7958 * AHB Error 7959 * 0x0 : No AHB Error Interrupt 7960 * 0x1 : AHB Error interrupt 7961 */ 7962 #define USB_AHBERR0 (BIT(2)) 7963 #define USB_AHBERR0_M (USB_AHBERR0_V << USB_AHBERR0_S) 7964 #define USB_AHBERR0_V 0x00000001 7965 #define USB_AHBERR0_S 2 7966 /** USB_SETUP0 : R/W1C; bitpos: [3]; default: 0; 7967 * SETUP Phase Done 7968 * 0x0 : No SETUP Phase Done 7969 * 0x1 : SETUP Phase Done 7970 */ 7971 #define USB_SETUP0 (BIT(3)) 7972 #define USB_SETUP0_M (USB_SETUP0_V << USB_SETUP0_S) 7973 #define USB_SETUP0_V 0x00000001 7974 #define USB_SETUP0_S 3 7975 /** USB_OUTTKNEPDIS0 : R/W1C; bitpos: [4]; default: 0; 7976 * OUT Token Received When Endpoint Disabled 7977 * 0x0 : No OUT Token Received When Endpoint Disabled 7978 * 0x1 : OUT Token Received When Endpoint Disabled 7979 */ 7980 #define USB_OUTTKNEPDIS0 (BIT(4)) 7981 #define USB_OUTTKNEPDIS0_M (USB_OUTTKNEPDIS0_V << USB_OUTTKNEPDIS0_S) 7982 #define USB_OUTTKNEPDIS0_V 0x00000001 7983 #define USB_OUTTKNEPDIS0_S 4 7984 /** USB_STSPHSERCVD0 : R/W1C; bitpos: [5]; default: 0; 7985 * Status Phase Received for Control Write 7986 * 0x0 : No Status Phase Received for Control Write 7987 * 0x1 : Status Phase Received for Control Write 7988 */ 7989 #define USB_STSPHSERCVD0 (BIT(5)) 7990 #define USB_STSPHSERCVD0_M (USB_STSPHSERCVD0_V << USB_STSPHSERCVD0_S) 7991 #define USB_STSPHSERCVD0_V 0x00000001 7992 #define USB_STSPHSERCVD0_S 5 7993 /** USB_BACK2BACKSETUP0 : R/W1C; bitpos: [6]; default: 0; 7994 * Back-to-Back SETUP Packets Received 7995 * 0x0 : No Back-to-Back SETUP Packets Received 7996 * 0x1 : Back-to-Back SETUP Packets Received 7997 */ 7998 #define USB_BACK2BACKSETUP0 (BIT(6)) 7999 #define USB_BACK2BACKSETUP0_M (USB_BACK2BACKSETUP0_V << USB_BACK2BACKSETUP0_S) 8000 #define USB_BACK2BACKSETUP0_V 0x00000001 8001 #define USB_BACK2BACKSETUP0_S 6 8002 /** USB_OUTPKTERR0 : R/W1C; bitpos: [8]; default: 0; 8003 * OUT Packet Error 8004 * 0x0 : No OUT Packet Error 8005 * 0x1 : OUT Packet Error 8006 */ 8007 #define USB_OUTPKTERR0 (BIT(8)) 8008 #define USB_OUTPKTERR0_M (USB_OUTPKTERR0_V << USB_OUTPKTERR0_S) 8009 #define USB_OUTPKTERR0_V 0x00000001 8010 #define USB_OUTPKTERR0_S 8 8011 /** USB_BNAINTR0 : R/W1C; bitpos: [9]; default: 0; 8012 * Buffer Not Available Interrupt 8013 * 0x0 : No BNA interrupt 8014 * 0x1 : BNA interrupt 8015 */ 8016 #define USB_BNAINTR0 (BIT(9)) 8017 #define USB_BNAINTR0_M (USB_BNAINTR0_V << USB_BNAINTR0_S) 8018 #define USB_BNAINTR0_V 0x00000001 8019 #define USB_BNAINTR0_S 9 8020 /** USB_PKTDRPSTS0 : R/W1C; bitpos: [11]; default: 0; 8021 * 0x0 : No interrupt 8022 * 0x1 : Packet Drop Status interrupt 8023 */ 8024 #define USB_PKTDRPSTS0 (BIT(11)) 8025 #define USB_PKTDRPSTS0_M (USB_PKTDRPSTS0_V << USB_PKTDRPSTS0_S) 8026 #define USB_PKTDRPSTS0_V 0x00000001 8027 #define USB_PKTDRPSTS0_S 11 8028 /** USB_BBLEERR0 : R/W1C; bitpos: [12]; default: 0; 8029 * 0x0 : No BbleErr interrupt 8030 * 0x1 : BbleErr interrupt 8031 */ 8032 #define USB_BBLEERR0 (BIT(12)) 8033 #define USB_BBLEERR0_M (USB_BBLEERR0_V << USB_BBLEERR0_S) 8034 #define USB_BBLEERR0_V 0x00000001 8035 #define USB_BBLEERR0_S 12 8036 /** USB_NAKINTRPT0 : R/W1C; bitpos: [13]; default: 0; 8037 * 0x0 : No NAK interrupt 8038 * 0x1 : NAK Interrupt 8039 */ 8040 #define USB_NAKINTRPT0 (BIT(13)) 8041 #define USB_NAKINTRPT0_M (USB_NAKINTRPT0_V << USB_NAKINTRPT0_S) 8042 #define USB_NAKINTRPT0_V 0x00000001 8043 #define USB_NAKINTRPT0_S 13 8044 /** USB_NYEPINTRPT0 : R/W1C; bitpos: [14]; default: 0; 8045 * 0x0 : No NYET interrupt 8046 * 0x1 : NYET Interrupt 8047 */ 8048 #define USB_NYEPINTRPT0 (BIT(14)) 8049 #define USB_NYEPINTRPT0_M (USB_NYEPINTRPT0_V << USB_NYEPINTRPT0_S) 8050 #define USB_NYEPINTRPT0_V 0x00000001 8051 #define USB_NYEPINTRPT0_S 14 8052 /** USB_STUPPKTRCVD0 : R/W1C; bitpos: [15]; default: 0; 8053 * 0x0 : No Setup packet received 8054 * 0x1 : Setup packet received 8055 */ 8056 #define USB_STUPPKTRCVD0 (BIT(15)) 8057 #define USB_STUPPKTRCVD0_M (USB_STUPPKTRCVD0_V << USB_STUPPKTRCVD0_S) 8058 #define USB_STUPPKTRCVD0_V 0x00000001 8059 #define USB_STUPPKTRCVD0_S 15 8060 8061 8062 /** USB_DOEPINT1_REG register 8063 * Device OUT Endpoint 1 Interrupt Register 8064 */ 8065 #define USB_DOEPINT1_REG (SOC_DPORT_USB_BASE + 0xb28) 8066 /** USB_XFERCOMPL1 : R/W1C; bitpos: [0]; default: 0; 8067 * Transfer Completed Interrupt 8068 * 0x0 : No Transfer Complete Interrupt 8069 * 0x1 : Transfer Complete Interrupt 8070 */ 8071 #define USB_XFERCOMPL1 (BIT(0)) 8072 #define USB_XFERCOMPL1_M (USB_XFERCOMPL1_V << USB_XFERCOMPL1_S) 8073 #define USB_XFERCOMPL1_V 0x00000001 8074 #define USB_XFERCOMPL1_S 0 8075 /** USB_EPDISBLD1 : R/W1C; bitpos: [1]; default: 0; 8076 * Endpoint Disabled Interrupt 8077 * 0x0 : No Endpoint Disabled Interrupt 8078 * 0x1 : Endpoint Disabled Interrupt 8079 */ 8080 #define USB_EPDISBLD1 (BIT(1)) 8081 #define USB_EPDISBLD1_M (USB_EPDISBLD1_V << USB_EPDISBLD1_S) 8082 #define USB_EPDISBLD1_V 0x00000001 8083 #define USB_EPDISBLD1_S 1 8084 /** USB_AHBERR1 : R/W1C; bitpos: [2]; default: 0; 8085 * AHB Error 8086 * 0x0 : No AHB Error Interrupt 8087 * 0x1 : AHB Error interrupt 8088 */ 8089 #define USB_AHBERR1 (BIT(2)) 8090 #define USB_AHBERR1_M (USB_AHBERR1_V << USB_AHBERR1_S) 8091 #define USB_AHBERR1_V 0x00000001 8092 #define USB_AHBERR1_S 2 8093 /** USB_SETUP1 : R/W1C; bitpos: [3]; default: 0; 8094 * SETUP Phase Done 8095 * 0x0 : No SETUP Phase Done 8096 * 0x1 : SETUP Phase Done 8097 */ 8098 #define USB_SETUP1 (BIT(3)) 8099 #define USB_SETUP1_M (USB_SETUP1_V << USB_SETUP1_S) 8100 #define USB_SETUP1_V 0x00000001 8101 #define USB_SETUP1_S 3 8102 /** USB_OUTTKNEPDIS1 : R/W1C; bitpos: [4]; default: 0; 8103 * OUT Token Received When Endpoint Disabled 8104 * 0x0 : No OUT Token Received When Endpoint Disabled 8105 * 0x1 : OUT Token Received When Endpoint Disabled 8106 */ 8107 #define USB_OUTTKNEPDIS1 (BIT(4)) 8108 #define USB_OUTTKNEPDIS1_M (USB_OUTTKNEPDIS1_V << USB_OUTTKNEPDIS1_S) 8109 #define USB_OUTTKNEPDIS1_V 0x00000001 8110 #define USB_OUTTKNEPDIS1_S 4 8111 /** USB_STSPHSERCVD1 : R/W1C; bitpos: [5]; default: 0; 8112 * Status Phase Received for Control Write 8113 * 0x0 : No Status Phase Received for Control Write 8114 * 0x1 : Status Phase Received for Control Write 8115 */ 8116 #define USB_STSPHSERCVD1 (BIT(5)) 8117 #define USB_STSPHSERCVD1_M (USB_STSPHSERCVD1_V << USB_STSPHSERCVD1_S) 8118 #define USB_STSPHSERCVD1_V 0x00000001 8119 #define USB_STSPHSERCVD1_S 5 8120 /** USB_BACK2BACKSETUP1 : R/W1C; bitpos: [6]; default: 0; 8121 * Back-to-Back SETUP Packets Received 8122 * 0x0 : No Back-to-Back SETUP Packets Received 8123 * 0x1 : Back-to-Back SETUP Packets Received 8124 */ 8125 #define USB_BACK2BACKSETUP1 (BIT(6)) 8126 #define USB_BACK2BACKSETUP1_M (USB_BACK2BACKSETUP1_V << USB_BACK2BACKSETUP1_S) 8127 #define USB_BACK2BACKSETUP1_V 0x00000001 8128 #define USB_BACK2BACKSETUP1_S 6 8129 /** USB_OUTPKTERR1 : R/W1C; bitpos: [8]; default: 0; 8130 * OUT Packet Error 8131 * 0x0 : No OUT Packet Error 8132 * 0x1 : OUT Packet Error 8133 */ 8134 #define USB_OUTPKTERR1 (BIT(8)) 8135 #define USB_OUTPKTERR1_M (USB_OUTPKTERR1_V << USB_OUTPKTERR1_S) 8136 #define USB_OUTPKTERR1_V 0x00000001 8137 #define USB_OUTPKTERR1_S 8 8138 /** USB_BNAINTR1 : R/W1C; bitpos: [9]; default: 0; 8139 * Buffer Not Available Interrupt 8140 * 0x0 : No BNA interrupt 8141 * 0x1 : BNA interrupt 8142 */ 8143 #define USB_BNAINTR1 (BIT(9)) 8144 #define USB_BNAINTR1_M (USB_BNAINTR1_V << USB_BNAINTR1_S) 8145 #define USB_BNAINTR1_V 0x00000001 8146 #define USB_BNAINTR1_S 9 8147 /** USB_PKTDRPSTS1 : R/W1C; bitpos: [11]; default: 0; 8148 * 0x0 : No interrupt 8149 * 0x1 : Packet Drop Status interrupt 8150 */ 8151 #define USB_PKTDRPSTS1 (BIT(11)) 8152 #define USB_PKTDRPSTS1_M (USB_PKTDRPSTS1_V << USB_PKTDRPSTS1_S) 8153 #define USB_PKTDRPSTS1_V 0x00000001 8154 #define USB_PKTDRPSTS1_S 11 8155 /** USB_BBLEERR1 : R/W1C; bitpos: [12]; default: 0; 8156 * 0x0 : No BbleErr interrupt 8157 * 0x1 : BbleErr interrupt 8158 */ 8159 #define USB_BBLEERR1 (BIT(12)) 8160 #define USB_BBLEERR1_M (USB_BBLEERR1_V << USB_BBLEERR1_S) 8161 #define USB_BBLEERR1_V 0x00000001 8162 #define USB_BBLEERR1_S 12 8163 /** USB_NAKINTRPT1 : R/W1C; bitpos: [13]; default: 0; 8164 * 0x0 : No NAK interrupt 8165 * 0x1 : NAK Interrupt 8166 */ 8167 #define USB_NAKINTRPT1 (BIT(13)) 8168 #define USB_NAKINTRPT1_M (USB_NAKINTRPT1_V << USB_NAKINTRPT1_S) 8169 #define USB_NAKINTRPT1_V 0x00000001 8170 #define USB_NAKINTRPT1_S 13 8171 /** USB_NYEPINTRPT1 : R/W1C; bitpos: [14]; default: 0; 8172 * 0x0 : No NYET interrupt 8173 * 0x1 : NYET Interrupt 8174 */ 8175 #define USB_NYEPINTRPT1 (BIT(14)) 8176 #define USB_NYEPINTRPT1_M (USB_NYEPINTRPT1_V << USB_NYEPINTRPT1_S) 8177 #define USB_NYEPINTRPT1_V 0x00000001 8178 #define USB_NYEPINTRPT1_S 14 8179 /** USB_STUPPKTRCVD1 : R/W1C; bitpos: [15]; default: 0; 8180 * 0x0 : No Setup packet received 8181 * 0x1 : Setup packet received 8182 */ 8183 #define USB_STUPPKTRCVD1 (BIT(15)) 8184 #define USB_STUPPKTRCVD1_M (USB_STUPPKTRCVD1_V << USB_STUPPKTRCVD1_S) 8185 #define USB_STUPPKTRCVD1_V 0x00000001 8186 #define USB_STUPPKTRCVD1_S 15 8187 8188 8189 /** USB_DOEPINT2_REG register 8190 * Device OUT Endpoint 2 Interrupt Register 8191 */ 8192 #define USB_DOEPINT2_REG (SOC_DPORT_USB_BASE + 0xb48) 8193 /** USB_XFERCOMPL2 : R/W1C; bitpos: [0]; default: 0; 8194 * Transfer Completed Interrupt 8195 * 0x0 : No Transfer Complete Interrupt 8196 * 0x1 : Transfer Complete Interrupt 8197 */ 8198 #define USB_XFERCOMPL2 (BIT(0)) 8199 #define USB_XFERCOMPL2_M (USB_XFERCOMPL2_V << USB_XFERCOMPL2_S) 8200 #define USB_XFERCOMPL2_V 0x00000001 8201 #define USB_XFERCOMPL2_S 0 8202 /** USB_EPDISBLD2 : R/W1C; bitpos: [1]; default: 0; 8203 * Endpoint Disabled Interrupt 8204 * 0x0 : No Endpoint Disabled Interrupt 8205 * 0x1 : Endpoint Disabled Interrupt 8206 */ 8207 #define USB_EPDISBLD2 (BIT(1)) 8208 #define USB_EPDISBLD2_M (USB_EPDISBLD2_V << USB_EPDISBLD2_S) 8209 #define USB_EPDISBLD2_V 0x00000001 8210 #define USB_EPDISBLD2_S 1 8211 /** USB_AHBERR2 : R/W1C; bitpos: [2]; default: 0; 8212 * AHB Error 8213 * 0x0 : No AHB Error Interrupt 8214 * 0x1 : AHB Error interrupt 8215 */ 8216 #define USB_AHBERR2 (BIT(2)) 8217 #define USB_AHBERR2_M (USB_AHBERR2_V << USB_AHBERR2_S) 8218 #define USB_AHBERR2_V 0x00000001 8219 #define USB_AHBERR2_S 2 8220 /** USB_SETUP2 : R/W1C; bitpos: [3]; default: 0; 8221 * SETUP Phase Done 8222 * 0x0 : No SETUP Phase Done 8223 * 0x1 : SETUP Phase Done 8224 */ 8225 #define USB_SETUP2 (BIT(3)) 8226 #define USB_SETUP2_M (USB_SETUP2_V << USB_SETUP2_S) 8227 #define USB_SETUP2_V 0x00000001 8228 #define USB_SETUP2_S 3 8229 /** USB_OUTTKNEPDIS2 : R/W1C; bitpos: [4]; default: 0; 8230 * OUT Token Received When Endpoint Disabled 8231 * 0x0 : No OUT Token Received When Endpoint Disabled 8232 * 0x1 : OUT Token Received When Endpoint Disabled 8233 */ 8234 #define USB_OUTTKNEPDIS2 (BIT(4)) 8235 #define USB_OUTTKNEPDIS2_M (USB_OUTTKNEPDIS2_V << USB_OUTTKNEPDIS2_S) 8236 #define USB_OUTTKNEPDIS2_V 0x00000001 8237 #define USB_OUTTKNEPDIS2_S 4 8238 /** USB_STSPHSERCVD2 : R/W1C; bitpos: [5]; default: 0; 8239 * Status Phase Received for Control Write 8240 * 0x0 : No Status Phase Received for Control Write 8241 * 0x1 : Status Phase Received for Control Write 8242 */ 8243 #define USB_STSPHSERCVD2 (BIT(5)) 8244 #define USB_STSPHSERCVD2_M (USB_STSPHSERCVD2_V << USB_STSPHSERCVD2_S) 8245 #define USB_STSPHSERCVD2_V 0x00000001 8246 #define USB_STSPHSERCVD2_S 5 8247 /** USB_BACK2BACKSETUP2 : R/W1C; bitpos: [6]; default: 0; 8248 * Back-to-Back SETUP Packets Received 8249 * 0x0 : No Back-to-Back SETUP Packets Received 8250 * 0x1 : Back-to-Back SETUP Packets Received 8251 */ 8252 #define USB_BACK2BACKSETUP2 (BIT(6)) 8253 #define USB_BACK2BACKSETUP2_M (USB_BACK2BACKSETUP2_V << USB_BACK2BACKSETUP2_S) 8254 #define USB_BACK2BACKSETUP2_V 0x00000001 8255 #define USB_BACK2BACKSETUP2_S 6 8256 /** USB_OUTPKTERR2 : R/W1C; bitpos: [8]; default: 0; 8257 * OUT Packet Error 8258 * 0x0 : No OUT Packet Error 8259 * 0x1 : OUT Packet Error 8260 */ 8261 #define USB_OUTPKTERR2 (BIT(8)) 8262 #define USB_OUTPKTERR2_M (USB_OUTPKTERR2_V << USB_OUTPKTERR2_S) 8263 #define USB_OUTPKTERR2_V 0x00000001 8264 #define USB_OUTPKTERR2_S 8 8265 /** USB_BNAINTR2 : R/W1C; bitpos: [9]; default: 0; 8266 * Buffer Not Available Interrupt 8267 * 0x0 : No BNA interrupt 8268 * 0x1 : BNA interrupt 8269 */ 8270 #define USB_BNAINTR2 (BIT(9)) 8271 #define USB_BNAINTR2_M (USB_BNAINTR2_V << USB_BNAINTR2_S) 8272 #define USB_BNAINTR2_V 0x00000001 8273 #define USB_BNAINTR2_S 9 8274 /** USB_PKTDRPSTS2 : R/W1C; bitpos: [11]; default: 0; 8275 * 0x0 : No interrupt 8276 * 0x1 : Packet Drop Status interrupt 8277 */ 8278 #define USB_PKTDRPSTS2 (BIT(11)) 8279 #define USB_PKTDRPSTS2_M (USB_PKTDRPSTS2_V << USB_PKTDRPSTS2_S) 8280 #define USB_PKTDRPSTS2_V 0x00000001 8281 #define USB_PKTDRPSTS2_S 11 8282 /** USB_BBLEERR2 : R/W1C; bitpos: [12]; default: 0; 8283 * 0x0 : No BbleErr interrupt 8284 * 0x1 : BbleErr interrupt 8285 */ 8286 #define USB_BBLEERR2 (BIT(12)) 8287 #define USB_BBLEERR2_M (USB_BBLEERR2_V << USB_BBLEERR2_S) 8288 #define USB_BBLEERR2_V 0x00000001 8289 #define USB_BBLEERR2_S 12 8290 /** USB_NAKINTRPT2 : R/W1C; bitpos: [13]; default: 0; 8291 * 0x0 : No NAK interrupt 8292 * 0x1 : NAK Interrupt 8293 */ 8294 #define USB_NAKINTRPT2 (BIT(13)) 8295 #define USB_NAKINTRPT2_M (USB_NAKINTRPT2_V << USB_NAKINTRPT2_S) 8296 #define USB_NAKINTRPT2_V 0x00000001 8297 #define USB_NAKINTRPT2_S 13 8298 /** USB_NYEPINTRPT2 : R/W1C; bitpos: [14]; default: 0; 8299 * 0x0 : No NYET interrupt 8300 * 0x1 : NYET Interrupt 8301 */ 8302 #define USB_NYEPINTRPT2 (BIT(14)) 8303 #define USB_NYEPINTRPT2_M (USB_NYEPINTRPT2_V << USB_NYEPINTRPT2_S) 8304 #define USB_NYEPINTRPT2_V 0x00000001 8305 #define USB_NYEPINTRPT2_S 14 8306 /** USB_STUPPKTRCVD2 : R/W1C; bitpos: [15]; default: 0; 8307 * 0x0 : No Setup packet received 8308 * 0x1 : Setup packet received 8309 */ 8310 #define USB_STUPPKTRCVD2 (BIT(15)) 8311 #define USB_STUPPKTRCVD2_M (USB_STUPPKTRCVD2_V << USB_STUPPKTRCVD2_S) 8312 #define USB_STUPPKTRCVD2_V 0x00000001 8313 #define USB_STUPPKTRCVD2_S 15 8314 8315 8316 /** USB_DOEPINT3_REG register 8317 * Device OUT Endpoint 3 Interrupt Register 8318 */ 8319 #define USB_DOEPINT3_REG (SOC_DPORT_USB_BASE + 0xb68) 8320 /** USB_XFERCOMPL3 : R/W1C; bitpos: [0]; default: 0; 8321 * Transfer Completed Interrupt 8322 * 0x0 : No Transfer Complete Interrupt 8323 * 0x1 : Transfer Complete Interrupt 8324 */ 8325 #define USB_XFERCOMPL3 (BIT(0)) 8326 #define USB_XFERCOMPL3_M (USB_XFERCOMPL3_V << USB_XFERCOMPL3_S) 8327 #define USB_XFERCOMPL3_V 0x00000001 8328 #define USB_XFERCOMPL3_S 0 8329 /** USB_EPDISBLD3 : R/W1C; bitpos: [1]; default: 0; 8330 * Endpoint Disabled Interrupt 8331 * 0x0 : No Endpoint Disabled Interrupt 8332 * 0x1 : Endpoint Disabled Interrupt 8333 */ 8334 #define USB_EPDISBLD3 (BIT(1)) 8335 #define USB_EPDISBLD3_M (USB_EPDISBLD3_V << USB_EPDISBLD3_S) 8336 #define USB_EPDISBLD3_V 0x00000001 8337 #define USB_EPDISBLD3_S 1 8338 /** USB_AHBERR3 : R/W1C; bitpos: [2]; default: 0; 8339 * AHB Error 8340 * 0x0 : No AHB Error Interrupt 8341 * 0x1 : AHB Error interrupt 8342 */ 8343 #define USB_AHBERR3 (BIT(2)) 8344 #define USB_AHBERR3_M (USB_AHBERR3_V << USB_AHBERR3_S) 8345 #define USB_AHBERR3_V 0x00000001 8346 #define USB_AHBERR3_S 2 8347 /** USB_SETUP3 : R/W1C; bitpos: [3]; default: 0; 8348 * SETUP Phase Done 8349 * 0x0 : No SETUP Phase Done 8350 * 0x1 : SETUP Phase Done 8351 */ 8352 #define USB_SETUP3 (BIT(3)) 8353 #define USB_SETUP3_M (USB_SETUP3_V << USB_SETUP3_S) 8354 #define USB_SETUP3_V 0x00000001 8355 #define USB_SETUP3_S 3 8356 /** USB_OUTTKNEPDIS3 : R/W1C; bitpos: [4]; default: 0; 8357 * OUT Token Received When Endpoint Disabled 8358 * 0x0 : No OUT Token Received When Endpoint Disabled 8359 * 0x1 : OUT Token Received When Endpoint Disabled 8360 */ 8361 #define USB_OUTTKNEPDIS3 (BIT(4)) 8362 #define USB_OUTTKNEPDIS3_M (USB_OUTTKNEPDIS3_V << USB_OUTTKNEPDIS3_S) 8363 #define USB_OUTTKNEPDIS3_V 0x00000001 8364 #define USB_OUTTKNEPDIS3_S 4 8365 /** USB_STSPHSERCVD3 : R/W1C; bitpos: [5]; default: 0; 8366 * Status Phase Received for Control Write 8367 * 0x0 : No Status Phase Received for Control Write 8368 * 0x1 : Status Phase Received for Control Write 8369 */ 8370 #define USB_STSPHSERCVD3 (BIT(5)) 8371 #define USB_STSPHSERCVD3_M (USB_STSPHSERCVD3_V << USB_STSPHSERCVD3_S) 8372 #define USB_STSPHSERCVD3_V 0x00000001 8373 #define USB_STSPHSERCVD3_S 5 8374 /** USB_BACK2BACKSETUP3 : R/W1C; bitpos: [6]; default: 0; 8375 * Back-to-Back SETUP Packets Received 8376 * 0x0 : No Back-to-Back SETUP Packets Received 8377 * 0x1 : Back-to-Back SETUP Packets Received 8378 */ 8379 #define USB_BACK2BACKSETUP3 (BIT(6)) 8380 #define USB_BACK2BACKSETUP3_M (USB_BACK2BACKSETUP3_V << USB_BACK2BACKSETUP3_S) 8381 #define USB_BACK2BACKSETUP3_V 0x00000001 8382 #define USB_BACK2BACKSETUP3_S 6 8383 /** USB_OUTPKTERR3 : R/W1C; bitpos: [8]; default: 0; 8384 * OUT Packet Error 8385 * 0x0 : No OUT Packet Error 8386 * 0x1 : OUT Packet Error 8387 */ 8388 #define USB_OUTPKTERR3 (BIT(8)) 8389 #define USB_OUTPKTERR3_M (USB_OUTPKTERR3_V << USB_OUTPKTERR3_S) 8390 #define USB_OUTPKTERR3_V 0x00000001 8391 #define USB_OUTPKTERR3_S 8 8392 /** USB_BNAINTR3 : R/W1C; bitpos: [9]; default: 0; 8393 * Buffer Not Available Interrupt 8394 * 0x0 : No BNA interrupt 8395 * 0x1 : BNA interrupt 8396 */ 8397 #define USB_BNAINTR3 (BIT(9)) 8398 #define USB_BNAINTR3_M (USB_BNAINTR3_V << USB_BNAINTR3_S) 8399 #define USB_BNAINTR3_V 0x00000001 8400 #define USB_BNAINTR3_S 9 8401 /** USB_PKTDRPSTS3 : R/W1C; bitpos: [11]; default: 0; 8402 * 0x0 : No interrupt 8403 * 0x1 : Packet Drop Status interrupt 8404 */ 8405 #define USB_PKTDRPSTS3 (BIT(11)) 8406 #define USB_PKTDRPSTS3_M (USB_PKTDRPSTS3_V << USB_PKTDRPSTS3_S) 8407 #define USB_PKTDRPSTS3_V 0x00000001 8408 #define USB_PKTDRPSTS3_S 11 8409 /** USB_BBLEERR3 : R/W1C; bitpos: [12]; default: 0; 8410 * 0x0 : No BbleErr interrupt 8411 * 0x1 : BbleErr interrupt 8412 */ 8413 #define USB_BBLEERR3 (BIT(12)) 8414 #define USB_BBLEERR3_M (USB_BBLEERR3_V << USB_BBLEERR3_S) 8415 #define USB_BBLEERR3_V 0x00000001 8416 #define USB_BBLEERR3_S 12 8417 /** USB_NAKINTRPT3 : R/W1C; bitpos: [13]; default: 0; 8418 * 0x0 : No NAK interrupt 8419 * 0x1 : NAK Interrupt 8420 */ 8421 #define USB_NAKINTRPT3 (BIT(13)) 8422 #define USB_NAKINTRPT3_M (USB_NAKINTRPT3_V << USB_NAKINTRPT3_S) 8423 #define USB_NAKINTRPT3_V 0x00000001 8424 #define USB_NAKINTRPT3_S 13 8425 /** USB_NYEPINTRPT3 : R/W1C; bitpos: [14]; default: 0; 8426 * 0x0 : No NYET interrupt 8427 * 0x1 : NYET Interrupt 8428 */ 8429 #define USB_NYEPINTRPT3 (BIT(14)) 8430 #define USB_NYEPINTRPT3_M (USB_NYEPINTRPT3_V << USB_NYEPINTRPT3_S) 8431 #define USB_NYEPINTRPT3_V 0x00000001 8432 #define USB_NYEPINTRPT3_S 14 8433 /** USB_STUPPKTRCVD3 : R/W1C; bitpos: [15]; default: 0; 8434 * 0x0 : No Setup packet received 8435 * 0x1 : Setup packet received 8436 */ 8437 #define USB_STUPPKTRCVD3 (BIT(15)) 8438 #define USB_STUPPKTRCVD3_M (USB_STUPPKTRCVD3_V << USB_STUPPKTRCVD3_S) 8439 #define USB_STUPPKTRCVD3_V 0x00000001 8440 #define USB_STUPPKTRCVD3_S 15 8441 8442 8443 /** USB_DOEPINT4_REG register 8444 * Device OUT Endpoint 4 Interrupt Register 8445 */ 8446 #define USB_DOEPINT4_REG (SOC_DPORT_USB_BASE + 0xb88) 8447 /** USB_XFERCOMPL4 : R/W1C; bitpos: [0]; default: 0; 8448 * Transfer Completed Interrupt 8449 * 0x0 : No Transfer Complete Interrupt 8450 * 0x1 : Transfer Complete Interrupt 8451 */ 8452 #define USB_XFERCOMPL4 (BIT(0)) 8453 #define USB_XFERCOMPL4_M (USB_XFERCOMPL4_V << USB_XFERCOMPL4_S) 8454 #define USB_XFERCOMPL4_V 0x00000001 8455 #define USB_XFERCOMPL4_S 0 8456 /** USB_EPDISBLD4 : R/W1C; bitpos: [1]; default: 0; 8457 * Endpoint Disabled Interrupt 8458 * 0x0 : No Endpoint Disabled Interrupt 8459 * 0x1 : Endpoint Disabled Interrupt 8460 */ 8461 #define USB_EPDISBLD4 (BIT(1)) 8462 #define USB_EPDISBLD4_M (USB_EPDISBLD4_V << USB_EPDISBLD4_S) 8463 #define USB_EPDISBLD4_V 0x00000001 8464 #define USB_EPDISBLD4_S 1 8465 /** USB_AHBERR4 : R/W1C; bitpos: [2]; default: 0; 8466 * AHB Error 8467 * 0x0 : No AHB Error Interrupt 8468 * 0x1 : AHB Error interrupt 8469 */ 8470 #define USB_AHBERR4 (BIT(2)) 8471 #define USB_AHBERR4_M (USB_AHBERR4_V << USB_AHBERR4_S) 8472 #define USB_AHBERR4_V 0x00000001 8473 #define USB_AHBERR4_S 2 8474 /** USB_SETUP4 : R/W1C; bitpos: [3]; default: 0; 8475 * SETUP Phase Done 8476 * 0x0 : No SETUP Phase Done 8477 * 0x1 : SETUP Phase Done 8478 */ 8479 #define USB_SETUP4 (BIT(3)) 8480 #define USB_SETUP4_M (USB_SETUP4_V << USB_SETUP4_S) 8481 #define USB_SETUP4_V 0x00000001 8482 #define USB_SETUP4_S 3 8483 /** USB_OUTTKNEPDIS4 : R/W1C; bitpos: [4]; default: 0; 8484 * OUT Token Received When Endpoint Disabled 8485 * 0x0 : No OUT Token Received When Endpoint Disabled 8486 * 0x1 : OUT Token Received When Endpoint Disabled 8487 */ 8488 #define USB_OUTTKNEPDIS4 (BIT(4)) 8489 #define USB_OUTTKNEPDIS4_M (USB_OUTTKNEPDIS4_V << USB_OUTTKNEPDIS4_S) 8490 #define USB_OUTTKNEPDIS4_V 0x00000001 8491 #define USB_OUTTKNEPDIS4_S 4 8492 /** USB_STSPHSERCVD4 : R/W1C; bitpos: [5]; default: 0; 8493 * Status Phase Received for Control Write 8494 * 0x0 : No Status Phase Received for Control Write 8495 * 0x1 : Status Phase Received for Control Write 8496 */ 8497 #define USB_STSPHSERCVD4 (BIT(5)) 8498 #define USB_STSPHSERCVD4_M (USB_STSPHSERCVD4_V << USB_STSPHSERCVD4_S) 8499 #define USB_STSPHSERCVD4_V 0x00000001 8500 #define USB_STSPHSERCVD4_S 5 8501 /** USB_BACK2BACKSETUP4 : R/W1C; bitpos: [6]; default: 0; 8502 * Back-to-Back SETUP Packets Received 8503 * 0x0 : No Back-to-Back SETUP Packets Received 8504 * 0x1 : Back-to-Back SETUP Packets Received 8505 */ 8506 #define USB_BACK2BACKSETUP4 (BIT(6)) 8507 #define USB_BACK2BACKSETUP4_M (USB_BACK2BACKSETUP4_V << USB_BACK2BACKSETUP4_S) 8508 #define USB_BACK2BACKSETUP4_V 0x00000001 8509 #define USB_BACK2BACKSETUP4_S 6 8510 /** USB_OUTPKTERR4 : R/W1C; bitpos: [8]; default: 0; 8511 * OUT Packet Error 8512 * 0x0 : No OUT Packet Error 8513 * 0x1 : OUT Packet Error 8514 */ 8515 #define USB_OUTPKTERR4 (BIT(8)) 8516 #define USB_OUTPKTERR4_M (USB_OUTPKTERR4_V << USB_OUTPKTERR4_S) 8517 #define USB_OUTPKTERR4_V 0x00000001 8518 #define USB_OUTPKTERR4_S 8 8519 /** USB_BNAINTR4 : R/W1C; bitpos: [9]; default: 0; 8520 * Buffer Not Available Interrupt 8521 * 0x0 : No BNA interrupt 8522 * 0x1 : BNA interrupt 8523 */ 8524 #define USB_BNAINTR4 (BIT(9)) 8525 #define USB_BNAINTR4_M (USB_BNAINTR4_V << USB_BNAINTR4_S) 8526 #define USB_BNAINTR4_V 0x00000001 8527 #define USB_BNAINTR4_S 9 8528 /** USB_PKTDRPSTS4 : R/W1C; bitpos: [11]; default: 0; 8529 * 0x0 : No interrupt 8530 * 0x1 : Packet Drop Status interrupt 8531 */ 8532 #define USB_PKTDRPSTS4 (BIT(11)) 8533 #define USB_PKTDRPSTS4_M (USB_PKTDRPSTS4_V << USB_PKTDRPSTS4_S) 8534 #define USB_PKTDRPSTS4_V 0x00000001 8535 #define USB_PKTDRPSTS4_S 11 8536 /** USB_BBLEERR4 : R/W1C; bitpos: [12]; default: 0; 8537 * 0x0 : No BbleErr interrupt 8538 * 0x1 : BbleErr interrupt 8539 */ 8540 #define USB_BBLEERR4 (BIT(12)) 8541 #define USB_BBLEERR4_M (USB_BBLEERR4_V << USB_BBLEERR4_S) 8542 #define USB_BBLEERR4_V 0x00000001 8543 #define USB_BBLEERR4_S 12 8544 /** USB_NAKINTRPT4 : R/W1C; bitpos: [13]; default: 0; 8545 * 0x0 : No NAK interrupt 8546 * 0x1 : NAK Interrupt 8547 */ 8548 #define USB_NAKINTRPT4 (BIT(13)) 8549 #define USB_NAKINTRPT4_M (USB_NAKINTRPT4_V << USB_NAKINTRPT4_S) 8550 #define USB_NAKINTRPT4_V 0x00000001 8551 #define USB_NAKINTRPT4_S 13 8552 /** USB_NYEPINTRPT4 : R/W1C; bitpos: [14]; default: 0; 8553 * 0x0 : No NYET interrupt 8554 * 0x1 : NYET Interrupt 8555 */ 8556 #define USB_NYEPINTRPT4 (BIT(14)) 8557 #define USB_NYEPINTRPT4_M (USB_NYEPINTRPT4_V << USB_NYEPINTRPT4_S) 8558 #define USB_NYEPINTRPT4_V 0x00000001 8559 #define USB_NYEPINTRPT4_S 14 8560 /** USB_STUPPKTRCVD4 : R/W1C; bitpos: [15]; default: 0; 8561 * 0x0 : No Setup packet received 8562 * 0x1 : Setup packet received 8563 */ 8564 #define USB_STUPPKTRCVD4 (BIT(15)) 8565 #define USB_STUPPKTRCVD4_M (USB_STUPPKTRCVD4_V << USB_STUPPKTRCVD4_S) 8566 #define USB_STUPPKTRCVD4_V 0x00000001 8567 #define USB_STUPPKTRCVD4_S 15 8568 8569 8570 /** USB_DOEPINT5_REG register 8571 * Device OUT Endpoint 5 Interrupt Register 8572 */ 8573 #define USB_DOEPINT5_REG (SOC_DPORT_USB_BASE + 0xba8) 8574 /** USB_XFERCOMPL5 : R/W1C; bitpos: [0]; default: 0; 8575 * Transfer Completed Interrupt 8576 * 0x0 : No Transfer Complete Interrupt 8577 * 0x1 : Transfer Complete Interrupt 8578 */ 8579 #define USB_XFERCOMPL5 (BIT(0)) 8580 #define USB_XFERCOMPL5_M (USB_XFERCOMPL5_V << USB_XFERCOMPL5_S) 8581 #define USB_XFERCOMPL5_V 0x00000001 8582 #define USB_XFERCOMPL5_S 0 8583 /** USB_EPDISBLD5 : R/W1C; bitpos: [1]; default: 0; 8584 * Endpoint Disabled Interrupt 8585 * 0x0 : No Endpoint Disabled Interrupt 8586 * 0x1 : Endpoint Disabled Interrupt 8587 */ 8588 #define USB_EPDISBLD5 (BIT(1)) 8589 #define USB_EPDISBLD5_M (USB_EPDISBLD5_V << USB_EPDISBLD5_S) 8590 #define USB_EPDISBLD5_V 0x00000001 8591 #define USB_EPDISBLD5_S 1 8592 /** USB_AHBERR5 : R/W1C; bitpos: [2]; default: 0; 8593 * AHB Error 8594 * 0x0 : No AHB Error Interrupt 8595 * 0x1 : AHB Error interrupt 8596 */ 8597 #define USB_AHBERR5 (BIT(2)) 8598 #define USB_AHBERR5_M (USB_AHBERR5_V << USB_AHBERR5_S) 8599 #define USB_AHBERR5_V 0x00000001 8600 #define USB_AHBERR5_S 2 8601 /** USB_SETUP5 : R/W1C; bitpos: [3]; default: 0; 8602 * SETUP Phase Done 8603 * 0x0 : No SETUP Phase Done 8604 * 0x1 : SETUP Phase Done 8605 */ 8606 #define USB_SETUP5 (BIT(3)) 8607 #define USB_SETUP5_M (USB_SETUP5_V << USB_SETUP5_S) 8608 #define USB_SETUP5_V 0x00000001 8609 #define USB_SETUP5_S 3 8610 /** USB_OUTTKNEPDIS5 : R/W1C; bitpos: [4]; default: 0; 8611 * OUT Token Received When Endpoint Disabled 8612 * 0x0 : No OUT Token Received When Endpoint Disabled 8613 * 0x1 : OUT Token Received When Endpoint Disabled 8614 */ 8615 #define USB_OUTTKNEPDIS5 (BIT(4)) 8616 #define USB_OUTTKNEPDIS5_M (USB_OUTTKNEPDIS5_V << USB_OUTTKNEPDIS5_S) 8617 #define USB_OUTTKNEPDIS5_V 0x00000001 8618 #define USB_OUTTKNEPDIS5_S 4 8619 /** USB_STSPHSERCVD5 : R/W1C; bitpos: [5]; default: 0; 8620 * Status Phase Received for Control Write 8621 * 0x0 : No Status Phase Received for Control Write 8622 * 0x1 : Status Phase Received for Control Write 8623 */ 8624 #define USB_STSPHSERCVD5 (BIT(5)) 8625 #define USB_STSPHSERCVD5_M (USB_STSPHSERCVD5_V << USB_STSPHSERCVD5_S) 8626 #define USB_STSPHSERCVD5_V 0x00000001 8627 #define USB_STSPHSERCVD5_S 5 8628 /** USB_BACK2BACKSETUP5 : R/W1C; bitpos: [6]; default: 0; 8629 * Back-to-Back SETUP Packets Received 8630 * 0x0 : No Back-to-Back SETUP Packets Received 8631 * 0x1 : Back-to-Back SETUP Packets Received 8632 */ 8633 #define USB_BACK2BACKSETUP5 (BIT(6)) 8634 #define USB_BACK2BACKSETUP5_M (USB_BACK2BACKSETUP5_V << USB_BACK2BACKSETUP5_S) 8635 #define USB_BACK2BACKSETUP5_V 0x00000001 8636 #define USB_BACK2BACKSETUP5_S 6 8637 /** USB_OUTPKTERR5 : R/W1C; bitpos: [8]; default: 0; 8638 * OUT Packet Error 8639 * 0x0 : No OUT Packet Error 8640 * 0x1 : OUT Packet Error 8641 */ 8642 #define USB_OUTPKTERR5 (BIT(8)) 8643 #define USB_OUTPKTERR5_M (USB_OUTPKTERR5_V << USB_OUTPKTERR5_S) 8644 #define USB_OUTPKTERR5_V 0x00000001 8645 #define USB_OUTPKTERR5_S 8 8646 /** USB_BNAINTR5 : R/W1C; bitpos: [9]; default: 0; 8647 * Buffer Not Available Interrupt 8648 * 0x0 : No BNA interrupt 8649 * 0x1 : BNA interrupt 8650 */ 8651 #define USB_BNAINTR5 (BIT(9)) 8652 #define USB_BNAINTR5_M (USB_BNAINTR5_V << USB_BNAINTR5_S) 8653 #define USB_BNAINTR5_V 0x00000001 8654 #define USB_BNAINTR5_S 9 8655 /** USB_PKTDRPSTS5 : R/W1C; bitpos: [11]; default: 0; 8656 * 0x0 : No interrupt 8657 * 0x1 : Packet Drop Status interrupt 8658 */ 8659 #define USB_PKTDRPSTS5 (BIT(11)) 8660 #define USB_PKTDRPSTS5_M (USB_PKTDRPSTS5_V << USB_PKTDRPSTS5_S) 8661 #define USB_PKTDRPSTS5_V 0x00000001 8662 #define USB_PKTDRPSTS5_S 11 8663 /** USB_BBLEERR5 : R/W1C; bitpos: [12]; default: 0; 8664 * 0x0 : No BbleErr interrupt 8665 * 0x1 : BbleErr interrupt 8666 */ 8667 #define USB_BBLEERR5 (BIT(12)) 8668 #define USB_BBLEERR5_M (USB_BBLEERR5_V << USB_BBLEERR5_S) 8669 #define USB_BBLEERR5_V 0x00000001 8670 #define USB_BBLEERR5_S 12 8671 /** USB_NAKINTRPT5 : R/W1C; bitpos: [13]; default: 0; 8672 * 0x0 : No NAK interrupt 8673 * 0x1 : NAK Interrupt 8674 */ 8675 #define USB_NAKINTRPT5 (BIT(13)) 8676 #define USB_NAKINTRPT5_M (USB_NAKINTRPT5_V << USB_NAKINTRPT5_S) 8677 #define USB_NAKINTRPT5_V 0x00000001 8678 #define USB_NAKINTRPT5_S 13 8679 /** USB_NYEPINTRPT5 : R/W1C; bitpos: [14]; default: 0; 8680 * 0x0 : No NYET interrupt 8681 * 0x1 : NYET Interrupt 8682 */ 8683 #define USB_NYEPINTRPT5 (BIT(14)) 8684 #define USB_NYEPINTRPT5_M (USB_NYEPINTRPT5_V << USB_NYEPINTRPT5_S) 8685 #define USB_NYEPINTRPT5_V 0x00000001 8686 #define USB_NYEPINTRPT5_S 14 8687 /** USB_STUPPKTRCVD5 : R/W1C; bitpos: [15]; default: 0; 8688 * 0x0 : No Setup packet received 8689 * 0x1 : Setup packet received 8690 */ 8691 #define USB_STUPPKTRCVD5 (BIT(15)) 8692 #define USB_STUPPKTRCVD5_M (USB_STUPPKTRCVD5_V << USB_STUPPKTRCVD5_S) 8693 #define USB_STUPPKTRCVD5_V 0x00000001 8694 #define USB_STUPPKTRCVD5_S 15 8695 8696 8697 /** USB_DOEPINT6_REG register 8698 * Device OUT Endpoint 6 Interrupt Register 8699 */ 8700 #define USB_DOEPINT6_REG (SOC_DPORT_USB_BASE + 0xbc8) 8701 /** USB_XFERCOMPL6 : R/W1C; bitpos: [0]; default: 0; 8702 * Transfer Completed Interrupt 8703 * 0x0 : No Transfer Complete Interrupt 8704 * 0x1 : Transfer Complete Interrupt 8705 */ 8706 #define USB_XFERCOMPL6 (BIT(0)) 8707 #define USB_XFERCOMPL6_M (USB_XFERCOMPL6_V << USB_XFERCOMPL6_S) 8708 #define USB_XFERCOMPL6_V 0x00000001 8709 #define USB_XFERCOMPL6_S 0 8710 /** USB_EPDISBLD6 : R/W1C; bitpos: [1]; default: 0; 8711 * Endpoint Disabled Interrupt 8712 * 0x0 : No Endpoint Disabled Interrupt 8713 * 0x1 : Endpoint Disabled Interrupt 8714 */ 8715 #define USB_EPDISBLD6 (BIT(1)) 8716 #define USB_EPDISBLD6_M (USB_EPDISBLD6_V << USB_EPDISBLD6_S) 8717 #define USB_EPDISBLD6_V 0x00000001 8718 #define USB_EPDISBLD6_S 1 8719 /** USB_AHBERR6 : R/W1C; bitpos: [2]; default: 0; 8720 * AHB Error 8721 * 0x0 : No AHB Error Interrupt 8722 * 0x1 : AHB Error interrupt 8723 */ 8724 #define USB_AHBERR6 (BIT(2)) 8725 #define USB_AHBERR6_M (USB_AHBERR6_V << USB_AHBERR6_S) 8726 #define USB_AHBERR6_V 0x00000001 8727 #define USB_AHBERR6_S 2 8728 /** USB_SETUP6 : R/W1C; bitpos: [3]; default: 0; 8729 * SETUP Phase Done 8730 * 0x0 : No SETUP Phase Done 8731 * 0x1 : SETUP Phase Done 8732 */ 8733 #define USB_SETUP6 (BIT(3)) 8734 #define USB_SETUP6_M (USB_SETUP6_V << USB_SETUP6_S) 8735 #define USB_SETUP6_V 0x00000001 8736 #define USB_SETUP6_S 3 8737 /** USB_OUTTKNEPDIS6 : R/W1C; bitpos: [4]; default: 0; 8738 * OUT Token Received When Endpoint Disabled 8739 * 0x0 : No OUT Token Received When Endpoint Disabled 8740 * 0x1 : OUT Token Received When Endpoint Disabled 8741 */ 8742 #define USB_OUTTKNEPDIS6 (BIT(4)) 8743 #define USB_OUTTKNEPDIS6_M (USB_OUTTKNEPDIS6_V << USB_OUTTKNEPDIS6_S) 8744 #define USB_OUTTKNEPDIS6_V 0x00000001 8745 #define USB_OUTTKNEPDIS6_S 4 8746 /** USB_STSPHSERCVD6 : R/W1C; bitpos: [5]; default: 0; 8747 * Status Phase Received for Control Write 8748 * 0x0 : No Status Phase Received for Control Write 8749 * 0x1 : Status Phase Received for Control Write 8750 */ 8751 #define USB_STSPHSERCVD6 (BIT(5)) 8752 #define USB_STSPHSERCVD6_M (USB_STSPHSERCVD6_V << USB_STSPHSERCVD6_S) 8753 #define USB_STSPHSERCVD6_V 0x00000001 8754 #define USB_STSPHSERCVD6_S 5 8755 /** USB_BACK2BACKSETUP6 : R/W1C; bitpos: [6]; default: 0; 8756 * Back-to-Back SETUP Packets Received 8757 * 0x0 : No Back-to-Back SETUP Packets Received 8758 * 0x1 : Back-to-Back SETUP Packets Received 8759 */ 8760 #define USB_BACK2BACKSETUP6 (BIT(6)) 8761 #define USB_BACK2BACKSETUP6_M (USB_BACK2BACKSETUP6_V << USB_BACK2BACKSETUP6_S) 8762 #define USB_BACK2BACKSETUP6_V 0x00000001 8763 #define USB_BACK2BACKSETUP6_S 6 8764 /** USB_OUTPKTERR6 : R/W1C; bitpos: [8]; default: 0; 8765 * OUT Packet Error 8766 * 0x0 : No OUT Packet Error 8767 * 0x1 : OUT Packet Error 8768 */ 8769 #define USB_OUTPKTERR6 (BIT(8)) 8770 #define USB_OUTPKTERR6_M (USB_OUTPKTERR6_V << USB_OUTPKTERR6_S) 8771 #define USB_OUTPKTERR6_V 0x00000001 8772 #define USB_OUTPKTERR6_S 8 8773 /** USB_BNAINTR6 : R/W1C; bitpos: [9]; default: 0; 8774 * Buffer Not Available Interrupt 8775 * 0x0 : No BNA interrupt 8776 * 0x1 : BNA interrupt 8777 */ 8778 #define USB_BNAINTR6 (BIT(9)) 8779 #define USB_BNAINTR6_M (USB_BNAINTR6_V << USB_BNAINTR6_S) 8780 #define USB_BNAINTR6_V 0x00000001 8781 #define USB_BNAINTR6_S 9 8782 /** USB_PKTDRPSTS6 : R/W1C; bitpos: [11]; default: 0; 8783 * 0x0 : No interrupt 8784 * 0x1 : Packet Drop Status interrupt 8785 */ 8786 #define USB_PKTDRPSTS6 (BIT(11)) 8787 #define USB_PKTDRPSTS6_M (USB_PKTDRPSTS6_V << USB_PKTDRPSTS6_S) 8788 #define USB_PKTDRPSTS6_V 0x00000001 8789 #define USB_PKTDRPSTS6_S 11 8790 /** USB_BBLEERR6 : R/W1C; bitpos: [12]; default: 0; 8791 * 0x0 : No BbleErr interrupt 8792 * 0x1 : BbleErr interrupt 8793 */ 8794 #define USB_BBLEERR6 (BIT(12)) 8795 #define USB_BBLEERR6_M (USB_BBLEERR6_V << USB_BBLEERR6_S) 8796 #define USB_BBLEERR6_V 0x00000001 8797 #define USB_BBLEERR6_S 12 8798 /** USB_NAKINTRPT6 : R/W1C; bitpos: [13]; default: 0; 8799 * 0x0 : No NAK interrupt 8800 * 0x1 : NAK Interrupt 8801 */ 8802 #define USB_NAKINTRPT6 (BIT(13)) 8803 #define USB_NAKINTRPT6_M (USB_NAKINTRPT6_V << USB_NAKINTRPT6_S) 8804 #define USB_NAKINTRPT6_V 0x00000001 8805 #define USB_NAKINTRPT6_S 13 8806 /** USB_NYEPINTRPT6 : R/W1C; bitpos: [14]; default: 0; 8807 * 0x0 : No NYET interrupt 8808 * 0x1 : NYET Interrupt 8809 */ 8810 #define USB_NYEPINTRPT6 (BIT(14)) 8811 #define USB_NYEPINTRPT6_M (USB_NYEPINTRPT6_V << USB_NYEPINTRPT6_S) 8812 #define USB_NYEPINTRPT6_V 0x00000001 8813 #define USB_NYEPINTRPT6_S 14 8814 /** USB_STUPPKTRCVD6 : R/W1C; bitpos: [15]; default: 0; 8815 * 0x0 : No Setup packet received 8816 * 0x1 : Setup packet received 8817 */ 8818 #define USB_STUPPKTRCVD6 (BIT(15)) 8819 #define USB_STUPPKTRCVD6_M (USB_STUPPKTRCVD6_V << USB_STUPPKTRCVD6_S) 8820 #define USB_STUPPKTRCVD6_V 0x00000001 8821 #define USB_STUPPKTRCVD6_S 15 8822 8823 8824 8825 8826 /** configuration registers */ 8827 /** USB_GAHBCFG_REG register 8828 * AHB Configuration Register 8829 */ 8830 #define USB_GAHBCFG_REG (SOC_DPORT_USB_BASE + 0x8) 8831 /** USB_GLBLLNTRMSK : R/W; bitpos: [0]; default: 0; 8832 * 1'b0: Mask the interrupt assertion to the application. 8833 * 1'b1: Unmask the interrupt assertion to the application 8834 */ 8835 #define USB_GLBLLNTRMSK (BIT(0)) 8836 #define USB_GLBLLNTRMSK_M (USB_GLBLLNTRMSK_V << USB_GLBLLNTRMSK_S) 8837 #define USB_GLBLLNTRMSK_V 0x00000001 8838 #define USB_GLBLLNTRMSK_S 0 8839 /** USB_HBSTLEN : R/W; bitpos: [5:1]; default: 0; 8840 * this field is used in Internal DMA modes 8841 * 4'b0000 Single 8842 * 4'b0001: INCR 8843 * 4'b0011 INCR4 8844 * 4'b0101 INCR8 8845 * 4'b0111 INCR16 8846 * Others: Reserved 8847 */ 8848 #define USB_HBSTLEN 0x0000000F 8849 #define USB_HBSTLEN_M (USB_HBSTLEN_V << USB_HBSTLEN_S) 8850 #define USB_HBSTLEN_V 0x0000000F 8851 #define USB_HBSTLEN_S 1 8852 /** USB_DMAEN : R/W; bitpos: [5]; default: 0; 8853 * This bit is always 0 when Slave-Only mode has been selected 8854 * 1'b0:Core operates in Slave mode 8855 * 1'b1:Core operates in a DMA mode 8856 */ 8857 #define USB_DMAEN (BIT(5)) 8858 #define USB_DMAEN_M (USB_DMAEN_V << USB_DMAEN_S) 8859 #define USB_DMAEN_V 0x00000001 8860 #define USB_DMAEN_S 5 8861 /** USB_NPTXFEMPLVL : R/W; bitpos: [7]; default: 0; 8862 * Non-Periodic TxFIFO Empty Level 8863 * 1'b0: DIEPINTn_REG.REG_TXFEMP interrupt indicates that the Non-Periodic TxFIFO is 8864 * half empty or that the IN Endpoint TxFIFO is half empty 8865 * 1'b1: GINTSTS_REG.USB_NPTXFEMP interrupt indicates that the Non-Periodic TxFIFO is 8866 * completely empty or that the IN Endpoint TxFIFO is completely empty 8867 */ 8868 #define USB_NPTXFEMPLVL (BIT(7)) 8869 #define USB_NPTXFEMPLVL_M (USB_NPTXFEMPLVL_V << USB_NPTXFEMPLVL_S) 8870 #define USB_NPTXFEMPLVL_V 0x00000001 8871 #define USB_NPTXFEMPLVL_S 7 8872 /** USB_PTXFEMPLVL : R/W; bitpos: [8]; default: 0; 8873 * Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt 8874 * register (GINTSTS_REG.USB_PTXFEMP) is triggered. This bit is used only in Slave 8875 * mode 8876 * 1'b0: GINTSTS_REG.USB_PTXFEMP interrupt indicates that the Periodic TxFIFO is half 8877 * empty 8878 * 1'b1: GINTSTS_REG.USB_PTXFEMP interrupt indicates that the Periodic TxFIFO is 8879 * completely empty 8880 */ 8881 #define USB_PTXFEMPLVL (BIT(8)) 8882 #define USB_PTXFEMPLVL_M (USB_PTXFEMPLVL_V << USB_PTXFEMPLVL_S) 8883 #define USB_PTXFEMPLVL_V 0x00000001 8884 #define USB_PTXFEMPLVL_S 8 8885 /** USB_REMMEMSUPP : R/W; bitpos: [21]; default: 0; 8886 * Remote Memory Support (RemMemSupp) This bit is programmed to enable the 8887 * functionality to wait for thesystem DMA Done Signal for the DMA Write Transfers 8888 * 1'b0:Remote Memory Support Feature disabled 8889 * 1'b1:Remote Memory Support Feature enabled 8890 */ 8891 #define USB_REMMEMSUPP (BIT(21)) 8892 #define USB_REMMEMSUPP_M (USB_REMMEMSUPP_V << USB_REMMEMSUPP_S) 8893 #define USB_REMMEMSUPP_V 0x00000001 8894 #define USB_REMMEMSUPP_S 21 8895 /** USB_NOTIALLDMAWRIT : R/W; bitpos: [22]; default: 0; 8896 * Notify All DMA Write Transactions (NotiAllDmaWrit) This bit is programmed to enable 8897 * the System DMA Done functionality for all the DMA write Transactions corresponding 8898 * to the Channel/Endpoint. This bit is valid only when GAHBCFG.RemMemSupp is set to 1 8899 */ 8900 #define USB_NOTIALLDMAWRIT (BIT(22)) 8901 #define USB_NOTIALLDMAWRIT_M (USB_NOTIALLDMAWRIT_V << USB_NOTIALLDMAWRIT_S) 8902 #define USB_NOTIALLDMAWRIT_V 0x00000001 8903 #define USB_NOTIALLDMAWRIT_S 22 8904 /** USB_AHBSINGLE : R/W; bitpos: [23]; default: 0; 8905 * AHB Single Support (AHBSingle) This bit when programmed supports Single transfers 8906 * for the remaining data in a transfer when the core is operating in DMA mode 8907 * 1'b0: The remaining data in the transfer is sent using INCR burst size 8908 * 1'b1: The remaining data in the transfer is sent using Single burst size 8909 */ 8910 #define USB_AHBSINGLE (BIT(23)) 8911 #define USB_AHBSINGLE_M (USB_AHBSINGLE_V << USB_AHBSINGLE_S) 8912 #define USB_AHBSINGLE_V 0x00000001 8913 #define USB_AHBSINGLE_S 23 8914 /** USB_INVDESCENDIANESS : R/W; bitpos: [24]; default: 0; 8915 * Invert Descriptor Endianess 8916 * 1'b0: Descriptor Endianness is same as AHB Master Endianness 8917 * 1'b1:Invert Descriptor Endianess according to AHB Master endianness 8918 */ 8919 #define USB_INVDESCENDIANESS (BIT(24)) 8920 #define USB_INVDESCENDIANESS_M (USB_INVDESCENDIANESS_V << USB_INVDESCENDIANESS_S) 8921 #define USB_INVDESCENDIANESS_V 0x00000001 8922 #define USB_INVDESCENDIANESS_S 24 8923 8924 8925 /** USB_GUSBCFG_REG register 8926 * USB Configuration Register 8927 */ 8928 #define USB_GUSBCFG_REG (SOC_DPORT_USB_BASE + 0xc) 8929 /** USB_TOUTCAL : R/W; bitpos: [3:0]; default: 0; 8930 * FS Timeout Calibration 8931 */ 8932 #define USB_TOUTCAL 0x00000007 8933 #define USB_TOUTCAL_M (USB_TOUTCAL_V << USB_TOUTCAL_S) 8934 #define USB_TOUTCAL_V 0x00000007 8935 #define USB_TOUTCAL_S 0 8936 /** USB_PHYIF : R/W; bitpos: [3]; default: 0; 8937 * The application uses this bit to configure the core to support a 8938 * UTMI+ PHY with an 8- or 16-bit interface. When a ULPI PHY is 8939 * chosen, this must be Set to 8-bit mode 8940 * 1'b0: 8 bits 8941 * 1'b1: 16 bits 8942 */ 8943 #define USB_PHYIF (BIT(3)) 8944 #define USB_PHYIF_M (USB_PHYIF_V << USB_PHYIF_S) 8945 #define USB_PHYIF_V 0x00000001 8946 #define USB_PHYIF_S 3 8947 /** USB_ULPI_UTMI_SEL : RO; bitpos: [4]; default: 0; 8948 * 1'b0: UTMI+ Interface 8949 * 1'b1: ULPI Interface 8950 */ 8951 #define USB_ULPI_UTMI_SEL (BIT(4)) 8952 #define USB_ULPI_UTMI_SEL_M (USB_ULPI_UTMI_SEL_V << USB_ULPI_UTMI_SEL_S) 8953 #define USB_ULPI_UTMI_SEL_V 0x00000001 8954 #define USB_ULPI_UTMI_SEL_S 4 8955 /** USB_FSINTF : R/W; bitpos: [5]; default: 0; 8956 * 1'b0: 6-pin unidirectional full-speed serial interface 8957 * 1'b1: 3-pin bidirectional full-speed serial interface 8958 */ 8959 #define USB_FSINTF (BIT(5)) 8960 #define USB_FSINTF_M (USB_FSINTF_V << USB_FSINTF_S) 8961 #define USB_FSINTF_V 0x00000001 8962 #define USB_FSINTF_S 5 8963 /** USB_PHYSEL : RO; bitpos: [6]; default: 1; 8964 * 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY 8965 * 1'b1: USB 1.1 full-speed serial transceiver 8966 */ 8967 #define USB_PHYSEL (BIT(6)) 8968 #define USB_PHYSEL_M (USB_PHYSEL_V << USB_PHYSEL_S) 8969 #define USB_PHYSEL_V 0x00000001 8970 #define USB_PHYSEL_S 6 8971 /** USB_SRPCAP : R/W; bitpos: [8]; default: 0; 8972 * 1'b0: SRP capability is not enabled 8973 * 1'b1: SRP capability is enabled 8974 */ 8975 #define USB_SRPCAP (BIT(8)) 8976 #define USB_SRPCAP_M (USB_SRPCAP_V << USB_SRPCAP_S) 8977 #define USB_SRPCAP_V 0x00000001 8978 #define USB_SRPCAP_S 8 8979 /** USB_HNPCAP : R/W; bitpos: [9]; default: 0; 8980 * 1'b0: HNP capability is not enabled 8981 * 1'b1: HNP capability is enabled 8982 */ 8983 #define USB_HNPCAP (BIT(9)) 8984 #define USB_HNPCAP_M (USB_HNPCAP_V << USB_HNPCAP_S) 8985 #define USB_HNPCAP_V 0x00000001 8986 #define USB_HNPCAP_S 9 8987 /** USB_USBTRDTIM : R/W; bitpos: [14:10]; default: 5; 8988 * 4'h5: When the MAC interface is 16-bit UTMI+ 8989 * 4'h9: When the MAC interface is 8-bit UTMI+ 8990 */ 8991 #define USB_USBTRDTIM 0x0000000F 8992 #define USB_USBTRDTIM_M (USB_USBTRDTIM_V << USB_USBTRDTIM_S) 8993 #define USB_USBTRDTIM_V 0x0000000F 8994 #define USB_USBTRDTIM_S 10 8995 /** USB_TERMSELDLPULSE : R/W; bitpos: [22]; default: 0; 8996 * TermSel DLine Pulsing Selection 8997 * 1'b0: Data line pulsing using utmi_txvalid (Default) 8998 * 1'b1: Data line pulsing using utmi_termsel 8999 */ 9000 #define USB_TERMSELDLPULSE (BIT(22)) 9001 #define USB_TERMSELDLPULSE_M (USB_TERMSELDLPULSE_V << USB_TERMSELDLPULSE_S) 9002 #define USB_TERMSELDLPULSE_V 0x00000001 9003 #define USB_TERMSELDLPULSE_S 22 9004 /** USB_TXENDDELAY : R/W; bitpos: [28]; default: 0; 9005 * 1'b0 : Normal Mode 9006 * 1'b1 : Tx End delay 9007 */ 9008 #define USB_TXENDDELAY (BIT(28)) 9009 #define USB_TXENDDELAY_M (USB_TXENDDELAY_V << USB_TXENDDELAY_S) 9010 #define USB_TXENDDELAY_V 0x00000001 9011 #define USB_TXENDDELAY_S 28 9012 /** USB_FORCEHSTMODE : R/W; bitpos: [29]; default: 0; 9013 * 1'b0 : Normal Mode 9014 * 1'b1 : Force Host Mode 9015 */ 9016 #define USB_FORCEHSTMODE (BIT(29)) 9017 #define USB_FORCEHSTMODE_M (USB_FORCEHSTMODE_V << USB_FORCEHSTMODE_S) 9018 #define USB_FORCEHSTMODE_V 0x00000001 9019 #define USB_FORCEHSTMODE_S 29 9020 /** USB_FORCEDEVMODE : R/W; bitpos: [30]; default: 0; 9021 * 1'b0 : Normal Mode 9022 * 1'b1 : Force Device Mode 9023 */ 9024 #define USB_FORCEDEVMODE (BIT(30)) 9025 #define USB_FORCEDEVMODE_M (USB_FORCEDEVMODE_V << USB_FORCEDEVMODE_S) 9026 #define USB_FORCEDEVMODE_V 0x00000001 9027 #define USB_FORCEDEVMODE_S 30 9028 /** USB_CORRUPTTXPKT : R/W; bitpos: [31]; default: 0; 9029 * This bit is for debug purposes only. Never Set this bit to 1. The application 9030 * should always write 1'b0 to this bit 9031 * 1'b0:Normal Mode 9032 * 1'b1:Debug Mode 9033 */ 9034 #define USB_CORRUPTTXPKT (BIT(31)) 9035 #define USB_CORRUPTTXPKT_M (USB_CORRUPTTXPKT_V << USB_CORRUPTTXPKT_S) 9036 #define USB_CORRUPTTXPKT_V 0x00000001 9037 #define USB_CORRUPTTXPKT_S 31 9038 9039 9040 /** USB_GRSTCTL_REG register 9041 * Reset Register 9042 */ 9043 #define USB_GRSTCTL_REG (SOC_DPORT_USB_BASE + 0x10) 9044 /** USB_CSFTRST : R_WS_SC; bitpos: [0]; default: 0; 9045 * Core Soft Reset 9046 */ 9047 #define USB_CSFTRST (BIT(0)) 9048 #define USB_CSFTRST_M (USB_CSFTRST_V << USB_CSFTRST_S) 9049 #define USB_CSFTRST_V 0x00000001 9050 #define USB_CSFTRST_S 0 9051 /** USB_PIUFSSFTRST : R_WS_SC; bitpos: [1]; default: 0; 9052 * 1'b0: No Reset 9053 * 1'b1:PIU FS Dedicated Controller Soft Reset 9054 */ 9055 #define USB_PIUFSSFTRST (BIT(1)) 9056 #define USB_PIUFSSFTRST_M (USB_PIUFSSFTRST_V << USB_PIUFSSFTRST_S) 9057 #define USB_PIUFSSFTRST_V 0x00000001 9058 #define USB_PIUFSSFTRST_S 1 9059 /** USB_FRMCNTRRST : R/W1S; bitpos: [2]; default: 0; 9060 * Host only. Host Frame Counter Reset.The application writes this bit to reset the 9061 * (micro)Frame number counter inside the core. When the (micro)Frame counter is 9062 * reset, the subsequent SOF sent out by the core has a (micro)Frame number of 0 9063 */ 9064 #define USB_FRMCNTRRST (BIT(2)) 9065 #define USB_FRMCNTRRST_M (USB_FRMCNTRRST_V << USB_FRMCNTRRST_S) 9066 #define USB_FRMCNTRRST_V 0x00000001 9067 #define USB_FRMCNTRRST_S 2 9068 /** USB_RXFFLSH : R/W1S; bitpos: [4]; default: 0; 9069 * RxFIFO Flush. The application can flush the entire RxFIFO using this bit, but must 9070 * first ensure that the core is not in the middle of a transaction.The application 9071 * must only write to this bit after checking that the controller is neither reading 9072 * from the RxFIFO nor writing to the RxFIFO 9073 * 1'b0:Does not flush the entire RxFIFO 9074 * 1'b1:flushes the entire RxFIFO 9075 */ 9076 #define USB_RXFFLSH (BIT(4)) 9077 #define USB_RXFFLSH_M (USB_RXFFLSH_V << USB_RXFFLSH_S) 9078 #define USB_RXFFLSH_V 0x00000001 9079 #define USB_RXFFLSH_S 4 9080 /** USB_TXFFLSH : R/W1S; bitpos: [5]; default: 0; 9081 * TxFIFO Flush.This bit selectively flushes a single or all transmit FIFOs, but 9082 * cannot do so If the core is in the midst of a transaction.The application must 9083 * write this bit only after checking that the core is neither writing to the TxFIFO 9084 * nor reading from the TxFIFO. 9085 */ 9086 #define USB_TXFFLSH (BIT(5)) 9087 #define USB_TXFFLSH_M (USB_TXFFLSH_V << USB_TXFFLSH_S) 9088 #define USB_TXFFLSH_V 0x00000001 9089 #define USB_TXFFLSH_S 5 9090 /** USB_TXFNUM : R/W; bitpos: [11:6]; default: 0; 9091 * TxFIFO Number.This is the FIFO number that must be flushed using the TxFIFO Flush 9092 * bit. This field must not be changed until the core clears the TxFIFO Flush bit 9093 */ 9094 #define USB_TXFNUM 0x0000001F 9095 #define USB_TXFNUM_M (USB_TXFNUM_V << USB_TXFNUM_S) 9096 #define USB_TXFNUM_V 0x0000001F 9097 #define USB_TXFNUM_S 6 9098 /** USB_DMAREQ : RO; bitpos: [30]; default: 0; 9099 * DMA Request Signal 9100 * 1'b0:No DMA request 9101 * 1'b1:DMA request is in progress 9102 */ 9103 #define USB_DMAREQ (BIT(30)) 9104 #define USB_DMAREQ_M (USB_DMAREQ_V << USB_DMAREQ_S) 9105 #define USB_DMAREQ_V 0x00000001 9106 #define USB_DMAREQ_S 30 9107 /** USB_AHBIDLE : RO; bitpos: [31]; default: 0; 9108 * AHB Master Idle 9109 * 1'b0:Not Idle 9110 * 1'b1:AHB Master Idle 9111 */ 9112 #define USB_AHBIDLE (BIT(31)) 9113 #define USB_AHBIDLE_M (USB_AHBIDLE_V << USB_AHBIDLE_S) 9114 #define USB_AHBIDLE_V 0x00000001 9115 #define USB_AHBIDLE_S 31 9116 9117 9118 /** USB_GRXFSIZ_REG register 9119 * Receive FIFO Size Register 9120 */ 9121 #define USB_GRXFSIZ_REG (SOC_DPORT_USB_BASE + 0x24) 9122 /** USB_RXFDEP : R/W; bitpos: [16:0]; default: 256; 9123 * RxFIFO Depth.This value is in terms of 32-bit words.Minimum value is 16,Maximum 9124 * value is 32,768 9125 */ 9126 #define USB_RXFDEP 0x0000FFFF 9127 #define USB_RXFDEP_M (USB_RXFDEP_V << USB_RXFDEP_S) 9128 #define USB_RXFDEP_V 0x0000FFFF 9129 #define USB_RXFDEP_S 0 9130 9131 9132 /** USB_GNPTXFSIZ_REG register 9133 * Non-periodic Transmit FIFO Size Register 9134 */ 9135 #define USB_GNPTXFSIZ_REG (SOC_DPORT_USB_BASE + 0x28) 9136 /** USB_NPTXFSTADDR : R/W; bitpos: [16:0]; default: 256; 9137 * The NPTxFStAddr field description is valid only for host mode.This field contains 9138 * the memory start address for Non-periodic Transmit FIFO RAM. 9139 */ 9140 #define USB_NPTXFSTADDR 0x0000FFFF 9141 #define USB_NPTXFSTADDR_M (USB_NPTXFSTADDR_V << USB_NPTXFSTADDR_S) 9142 #define USB_NPTXFSTADDR_V 0x0000FFFF 9143 #define USB_NPTXFSTADDR_S 0 9144 /** USB_NPTXFDEP : R/W; bitpos: [32:16]; default: 256; 9145 * The NPTxFDep field description is valid only for host mode or device mode when 9146 * OTG_EN_DED_TX_FIFO=0.Minimum value is 16,Maximum value is 32,768. 9147 */ 9148 #define USB_NPTXFDEP 0x0000FFFF 9149 #define USB_NPTXFDEP_M (USB_NPTXFDEP_V << USB_NPTXFDEP_S) 9150 #define USB_NPTXFDEP_V 0x0000FFFF 9151 #define USB_NPTXFDEP_S 16 9152 9153 9154 /** USB_GNPTXSTS_REG register 9155 * Non-periodic Transmit FIFO/Queue Status Register 9156 */ 9157 #define USB_GNPTXSTS_REG (SOC_DPORT_USB_BASE + 0x2c) 9158 /** USB_NPTXFSPCAVAIL : RO; bitpos: [16:0]; default: 256; 9159 * Non-periodic TxFIFO Space Avail.Indicates the amount of free space available in the 9160 * Non-periodic TxFIFO.Values are in terms of 32-bit words. 9161 */ 9162 #define USB_NPTXFSPCAVAIL 0x0000FFFF 9163 #define USB_NPTXFSPCAVAIL_M (USB_NPTXFSPCAVAIL_V << USB_NPTXFSPCAVAIL_S) 9164 #define USB_NPTXFSPCAVAIL_V 0x0000FFFF 9165 #define USB_NPTXFSPCAVAIL_S 0 9166 /** USB_NPTXQSPCAVAIL : RO; bitpos: [20:16]; default: 4; 9167 * Non-periodic Transmit Request Queue Space Available.Indicates the amount of free 9168 * space available in the Non-periodic Transmit Request Queue. This queue holds both 9169 * IN and OUT requests in Host mode. Device mode has only IN requests. 9170 */ 9171 #define USB_NPTXQSPCAVAIL 0x0000000F 9172 #define USB_NPTXQSPCAVAIL_M (USB_NPTXQSPCAVAIL_V << USB_NPTXQSPCAVAIL_S) 9173 #define USB_NPTXQSPCAVAIL_V 0x0000000F 9174 #define USB_NPTXQSPCAVAIL_S 16 9175 /** USB_NPTXQTOP : RO; bitpos: [31:24]; default: 0; 9176 * Top of the Non-periodic Transmit Request Queue. 9177 * Bits [30:27]: Channel/endpoint number. 9178 * Bits [26:25]: 2'b00: IN/OUT token 2'b01: Zero-length transmit packet (device 9179 * IN/host OUT) 2'b10: PING/CSPLIT token 2'b11: Channel halt command. 9180 * Bit [24]: Terminate (last Entry for selected channel/endpoint). 9181 */ 9182 #define USB_NPTXQTOP 0x0000007F 9183 #define USB_NPTXQTOP_M (USB_NPTXQTOP_V << USB_NPTXQTOP_S) 9184 #define USB_NPTXQTOP_V 0x0000007F 9185 #define USB_NPTXQTOP_S 24 9186 9187 9188 /** USB_HCTSIZ0_REG register 9189 * Host Channel 0Transfer Size Register 9190 */ 9191 #define USB_HCTSIZ0_REG (SOC_DPORT_USB_BASE + 0x510) 9192 /** USB_H_XFERSIZE0 : R/W; bitpos: [19:0]; default: 0; 9193 * Non-Scatter/Gather DMA Mode: Transfer Size. 9194 * Scatter/Gather DMA Mode: 9195 * [18:16]: Reserved 9196 * [15:8]: NTD (Number of Transfer Descriptors) 9197 */ 9198 #define USB_H_XFERSIZE0 0x0007FFFF 9199 #define USB_H_XFERSIZE0_M (USB_H_XFERSIZE0_V << USB_H_XFERSIZE0_S) 9200 #define USB_H_XFERSIZE0_V 0x0007FFFF 9201 #define USB_H_XFERSIZE0_S 0 9202 /** USB_H_PKTCNT0 : R/W; bitpos: [29:19]; default: 0; 9203 * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the 9204 * application with the expected number of packets to be transmitted (OUT) or received 9205 * (IN). 9206 * Scatter/Gather DMA Mode: Reserved. 9207 */ 9208 #define USB_H_PKTCNT0 0x000003FF 9209 #define USB_H_PKTCNT0_M (USB_H_PKTCNT0_V << USB_H_PKTCNT0_S) 9210 #define USB_H_PKTCNT0_V 0x000003FF 9211 #define USB_H_PKTCNT0_S 19 9212 /** USB_H_PID0 : R/W; bitpos: [31:29]; default: 0; 9213 * 2'b00: DATA0 9214 * 2'b01: DATA2 9215 * 2'b10: DATA1 9216 * 2'b11: MDATA (non-control)/SETUP (control) 9217 */ 9218 #define USB_H_PID0 0x00000003 9219 #define USB_H_PID0_M (USB_H_PID0_V << USB_H_PID0_S) 9220 #define USB_H_PID0_V 0x00000003 9221 #define USB_H_PID0_S 29 9222 /** USB_H_DOPNG0 : R/W; bitpos: [31]; default: 0; 9223 * This bit is used only for OUT transfers. Setting this field to 1 directs the host 9224 * to do PING protocol 9225 * 1'b0: No ping protocol 9226 * 1'b1: Ping protocol 9227 */ 9228 #define USB_H_DOPNG0 (BIT(31)) 9229 #define USB_H_DOPNG0_M (USB_H_DOPNG0_V << USB_H_DOPNG0_S) 9230 #define USB_H_DOPNG0_V 0x00000001 9231 #define USB_H_DOPNG0_S 31 9232 9233 9234 /** USB_HCTSIZ1_REG register 9235 * Host Channel 1Transfer Size Register 9236 */ 9237 #define USB_HCTSIZ1_REG (SOC_DPORT_USB_BASE + 0x530) 9238 /** USB_H_XFERSIZE1 : R/W; bitpos: [19:0]; default: 0; 9239 * Non-Scatter/Gather DMA Mode: Transfer Size. 9240 * Scatter/Gather DMA Mode: 9241 * [18:16]: Reserved 9242 * [15:8]: NTD (Number of Transfer Descriptors) 9243 */ 9244 #define USB_H_XFERSIZE1 0x0007FFFF 9245 #define USB_H_XFERSIZE1_M (USB_H_XFERSIZE1_V << USB_H_XFERSIZE1_S) 9246 #define USB_H_XFERSIZE1_V 0x0007FFFF 9247 #define USB_H_XFERSIZE1_S 0 9248 /** USB_H_PKTCNT1 : R/W; bitpos: [29:19]; default: 0; 9249 * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the 9250 * application with the expected number of packets to be transmitted (OUT) or received 9251 * (IN). 9252 * Scatter/Gather DMA Mode: Reserved. 9253 */ 9254 #define USB_H_PKTCNT1 0x000003FF 9255 #define USB_H_PKTCNT1_M (USB_H_PKTCNT1_V << USB_H_PKTCNT1_S) 9256 #define USB_H_PKTCNT1_V 0x000003FF 9257 #define USB_H_PKTCNT1_S 19 9258 /** USB_H_PID1 : R/W; bitpos: [31:29]; default: 0; 9259 * 2'b00: DATA0 9260 * 2'b01: DATA2 9261 * 2'b10: DATA1 9262 * 2'b11: MDATA (non-control)/SETUP (control) 9263 */ 9264 #define USB_H_PID1 0x00000003 9265 #define USB_H_PID1_M (USB_H_PID1_V << USB_H_PID1_S) 9266 #define USB_H_PID1_V 0x00000003 9267 #define USB_H_PID1_S 29 9268 /** USB_H_DOPNG1 : R/W; bitpos: [31]; default: 0; 9269 * This bit is used only for OUT transfers. Setting this field to 1 directs the host 9270 * to do PING protocol 9271 * 1'b0: No ping protocol 9272 * 1'b1: Ping protocol 9273 */ 9274 #define USB_H_DOPNG1 (BIT(31)) 9275 #define USB_H_DOPNG1_M (USB_H_DOPNG1_V << USB_H_DOPNG1_S) 9276 #define USB_H_DOPNG1_V 0x00000001 9277 #define USB_H_DOPNG1_S 31 9278 9279 9280 /** USB_HCTSIZ2_REG register 9281 * Host Channel 2Transfer Size Register 9282 */ 9283 #define USB_HCTSIZ2_REG (SOC_DPORT_USB_BASE + 0x550) 9284 /** USB_H_XFERSIZE2 : R/W; bitpos: [19:0]; default: 0; 9285 * Non-Scatter/Gather DMA Mode: Transfer Size. 9286 * Scatter/Gather DMA Mode: 9287 * [18:16]: Reserved 9288 * [15:8]: NTD (Number of Transfer Descriptors) 9289 */ 9290 #define USB_H_XFERSIZE2 0x0007FFFF 9291 #define USB_H_XFERSIZE2_M (USB_H_XFERSIZE2_V << USB_H_XFERSIZE2_S) 9292 #define USB_H_XFERSIZE2_V 0x0007FFFF 9293 #define USB_H_XFERSIZE2_S 0 9294 /** USB_H_PKTCNT2 : R/W; bitpos: [29:19]; default: 0; 9295 * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the 9296 * application with the expected number of packets to be transmitted (OUT) or received 9297 * (IN). 9298 * Scatter/Gather DMA Mode: Reserved. 9299 */ 9300 #define USB_H_PKTCNT2 0x000003FF 9301 #define USB_H_PKTCNT2_M (USB_H_PKTCNT2_V << USB_H_PKTCNT2_S) 9302 #define USB_H_PKTCNT2_V 0x000003FF 9303 #define USB_H_PKTCNT2_S 19 9304 /** USB_H_PID2 : R/W; bitpos: [31:29]; default: 0; 9305 * 2'b00: DATA0 9306 * 2'b01: DATA2 9307 * 2'b10: DATA1 9308 * 2'b11: MDATA (non-control)/SETUP (control) 9309 */ 9310 #define USB_H_PID2 0x00000003 9311 #define USB_H_PID2_M (USB_H_PID2_V << USB_H_PID2_S) 9312 #define USB_H_PID2_V 0x00000003 9313 #define USB_H_PID2_S 29 9314 /** USB_H_DOPNG2 : R/W; bitpos: [31]; default: 0; 9315 * This bit is used only for OUT transfers. Setting this field to 1 directs the host 9316 * to do PING protocol 9317 * 1'b0: No ping protocol 9318 * 1'b1: Ping protocol 9319 */ 9320 #define USB_H_DOPNG2 (BIT(31)) 9321 #define USB_H_DOPNG2_M (USB_H_DOPNG2_V << USB_H_DOPNG2_S) 9322 #define USB_H_DOPNG2_V 0x00000001 9323 #define USB_H_DOPNG2_S 31 9324 9325 9326 /** USB_HCTSIZ3_REG register 9327 * Host Channel 3Transfer Size Register 9328 */ 9329 #define USB_HCTSIZ3_REG (SOC_DPORT_USB_BASE + 0x570) 9330 /** USB_H_XFERSIZE3 : R/W; bitpos: [19:0]; default: 0; 9331 * Non-Scatter/Gather DMA Mode: Transfer Size. 9332 * Scatter/Gather DMA Mode: 9333 * [18:16]: Reserved 9334 * [15:8]: NTD (Number of Transfer Descriptors) 9335 */ 9336 #define USB_H_XFERSIZE3 0x0007FFFF 9337 #define USB_H_XFERSIZE3_M (USB_H_XFERSIZE3_V << USB_H_XFERSIZE3_S) 9338 #define USB_H_XFERSIZE3_V 0x0007FFFF 9339 #define USB_H_XFERSIZE3_S 0 9340 /** USB_H_PKTCNT3 : R/W; bitpos: [29:19]; default: 0; 9341 * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the 9342 * application with the expected number of packets to be transmitted (OUT) or received 9343 * (IN). 9344 * Scatter/Gather DMA Mode: Reserved. 9345 */ 9346 #define USB_H_PKTCNT3 0x000003FF 9347 #define USB_H_PKTCNT3_M (USB_H_PKTCNT3_V << USB_H_PKTCNT3_S) 9348 #define USB_H_PKTCNT3_V 0x000003FF 9349 #define USB_H_PKTCNT3_S 19 9350 /** USB_H_PID3 : R/W; bitpos: [31:29]; default: 0; 9351 * 2'b00: DATA0 9352 * 2'b01: DATA2 9353 * 2'b10: DATA1 9354 * 2'b11: MDATA (non-control)/SETUP (control) 9355 */ 9356 #define USB_H_PID3 0x00000003 9357 #define USB_H_PID3_M (USB_H_PID3_V << USB_H_PID3_S) 9358 #define USB_H_PID3_V 0x00000003 9359 #define USB_H_PID3_S 29 9360 /** USB_H_DOPNG3 : R/W; bitpos: [31]; default: 0; 9361 * This bit is used only for OUT transfers. Setting this field to 1 directs the host 9362 * to do PING protocol 9363 * 1'b0: No ping protocol 9364 * 1'b1: Ping protocol 9365 */ 9366 #define USB_H_DOPNG3 (BIT(31)) 9367 #define USB_H_DOPNG3_M (USB_H_DOPNG3_V << USB_H_DOPNG3_S) 9368 #define USB_H_DOPNG3_V 0x00000001 9369 #define USB_H_DOPNG3_S 31 9370 9371 9372 /** USB_HCTSIZ4_REG register 9373 * Host Channel 4Transfer Size Register 9374 */ 9375 #define USB_HCTSIZ4_REG (SOC_DPORT_USB_BASE + 0x590) 9376 /** USB_H_XFERSIZE4 : R/W; bitpos: [19:0]; default: 0; 9377 * Non-Scatter/Gather DMA Mode: Transfer Size. 9378 * Scatter/Gather DMA Mode: 9379 * [18:16]: Reserved 9380 * [15:8]: NTD (Number of Transfer Descriptors) 9381 */ 9382 #define USB_H_XFERSIZE4 0x0007FFFF 9383 #define USB_H_XFERSIZE4_M (USB_H_XFERSIZE4_V << USB_H_XFERSIZE4_S) 9384 #define USB_H_XFERSIZE4_V 0x0007FFFF 9385 #define USB_H_XFERSIZE4_S 0 9386 /** USB_H_PKTCNT4 : R/W; bitpos: [29:19]; default: 0; 9387 * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the 9388 * application with the expected number of packets to be transmitted (OUT) or received 9389 * (IN). 9390 * Scatter/Gather DMA Mode: Reserved. 9391 */ 9392 #define USB_H_PKTCNT4 0x000003FF 9393 #define USB_H_PKTCNT4_M (USB_H_PKTCNT4_V << USB_H_PKTCNT4_S) 9394 #define USB_H_PKTCNT4_V 0x000003FF 9395 #define USB_H_PKTCNT4_S 19 9396 /** USB_H_PID4 : R/W; bitpos: [31:29]; default: 0; 9397 * 2'b00: DATA0 9398 * 2'b01: DATA2 9399 * 2'b10: DATA1 9400 * 2'b11: MDATA (non-control)/SETUP (control) 9401 */ 9402 #define USB_H_PID4 0x00000003 9403 #define USB_H_PID4_M (USB_H_PID4_V << USB_H_PID4_S) 9404 #define USB_H_PID4_V 0x00000003 9405 #define USB_H_PID4_S 29 9406 /** USB_H_DOPNG4 : R/W; bitpos: [31]; default: 0; 9407 * This bit is used only for OUT transfers. Setting this field to 1 directs the host 9408 * to do PING protocol 9409 * 1'b0: No ping protocol 9410 * 1'b1: Ping protocol 9411 */ 9412 #define USB_H_DOPNG4 (BIT(31)) 9413 #define USB_H_DOPNG4_M (USB_H_DOPNG4_V << USB_H_DOPNG4_S) 9414 #define USB_H_DOPNG4_V 0x00000001 9415 #define USB_H_DOPNG4_S 31 9416 9417 9418 /** USB_HCTSIZ5_REG register 9419 * Host Channel 5Transfer Size Register 9420 */ 9421 #define USB_HCTSIZ5_REG (SOC_DPORT_USB_BASE + 0x5b0) 9422 /** USB_H_XFERSIZE5 : R/W; bitpos: [19:0]; default: 0; 9423 * Non-Scatter/Gather DMA Mode: Transfer Size. 9424 * Scatter/Gather DMA Mode: 9425 * [18:16]: Reserved 9426 * [15:8]: NTD (Number of Transfer Descriptors) 9427 */ 9428 #define USB_H_XFERSIZE5 0x0007FFFF 9429 #define USB_H_XFERSIZE5_M (USB_H_XFERSIZE5_V << USB_H_XFERSIZE5_S) 9430 #define USB_H_XFERSIZE5_V 0x0007FFFF 9431 #define USB_H_XFERSIZE5_S 0 9432 /** USB_H_PKTCNT5 : R/W; bitpos: [29:19]; default: 0; 9433 * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the 9434 * application with the expected number of packets to be transmitted (OUT) or received 9435 * (IN). 9436 * Scatter/Gather DMA Mode: Reserved. 9437 */ 9438 #define USB_H_PKTCNT5 0x000003FF 9439 #define USB_H_PKTCNT5_M (USB_H_PKTCNT5_V << USB_H_PKTCNT5_S) 9440 #define USB_H_PKTCNT5_V 0x000003FF 9441 #define USB_H_PKTCNT5_S 19 9442 /** USB_H_PID5 : R/W; bitpos: [31:29]; default: 0; 9443 * 2'b00: DATA0 9444 * 2'b01: DATA2 9445 * 2'b10: DATA1 9446 * 2'b11: MDATA (non-control)/SETUP (control) 9447 */ 9448 #define USB_H_PID5 0x00000003 9449 #define USB_H_PID5_M (USB_H_PID5_V << USB_H_PID5_S) 9450 #define USB_H_PID5_V 0x00000003 9451 #define USB_H_PID5_S 29 9452 /** USB_H_DOPNG5 : R/W; bitpos: [31]; default: 0; 9453 * This bit is used only for OUT transfers. Setting this field to 1 directs the host 9454 * to do PING protocol 9455 * 1'b0: No ping protocol 9456 * 1'b1: Ping protocol 9457 */ 9458 #define USB_H_DOPNG5 (BIT(31)) 9459 #define USB_H_DOPNG5_M (USB_H_DOPNG5_V << USB_H_DOPNG5_S) 9460 #define USB_H_DOPNG5_V 0x00000001 9461 #define USB_H_DOPNG5_S 31 9462 9463 9464 /** USB_HCTSIZ6_REG register 9465 * Host Channel 6Transfer Size Register 9466 */ 9467 #define USB_HCTSIZ6_REG (SOC_DPORT_USB_BASE + 0x5d0) 9468 /** USB_H_XFERSIZE6 : R/W; bitpos: [19:0]; default: 0; 9469 * Non-Scatter/Gather DMA Mode: Transfer Size. 9470 * Scatter/Gather DMA Mode: 9471 * [18:16]: Reserved 9472 * [15:8]: NTD (Number of Transfer Descriptors) 9473 */ 9474 #define USB_H_XFERSIZE6 0x0007FFFF 9475 #define USB_H_XFERSIZE6_M (USB_H_XFERSIZE6_V << USB_H_XFERSIZE6_S) 9476 #define USB_H_XFERSIZE6_V 0x0007FFFF 9477 #define USB_H_XFERSIZE6_S 0 9478 /** USB_H_PKTCNT6 : R/W; bitpos: [29:19]; default: 0; 9479 * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the 9480 * application with the expected number of packets to be transmitted (OUT) or received 9481 * (IN). 9482 * Scatter/Gather DMA Mode: Reserved. 9483 */ 9484 #define USB_H_PKTCNT6 0x000003FF 9485 #define USB_H_PKTCNT6_M (USB_H_PKTCNT6_V << USB_H_PKTCNT6_S) 9486 #define USB_H_PKTCNT6_V 0x000003FF 9487 #define USB_H_PKTCNT6_S 19 9488 /** USB_H_PID6 : R/W; bitpos: [31:29]; default: 0; 9489 * 2'b00: DATA0 9490 * 2'b01: DATA2 9491 * 2'b10: DATA1 9492 * 2'b11: MDATA (non-control)/SETUP (control) 9493 */ 9494 #define USB_H_PID6 0x00000003 9495 #define USB_H_PID6_M (USB_H_PID6_V << USB_H_PID6_S) 9496 #define USB_H_PID6_V 0x00000003 9497 #define USB_H_PID6_S 29 9498 /** USB_H_DOPNG6 : R/W; bitpos: [31]; default: 0; 9499 * This bit is used only for OUT transfers. Setting this field to 1 directs the host 9500 * to do PING protocol 9501 * 1'b0: No ping protocol 9502 * 1'b1: Ping protocol 9503 */ 9504 #define USB_H_DOPNG6 (BIT(31)) 9505 #define USB_H_DOPNG6_M (USB_H_DOPNG6_V << USB_H_DOPNG6_S) 9506 #define USB_H_DOPNG6_V 0x00000001 9507 #define USB_H_DOPNG6_S 31 9508 9509 9510 /** USB_HCTSIZ7_REG register 9511 * Host Channel 7Transfer Size Register 9512 */ 9513 #define USB_HCTSIZ7_REG (SOC_DPORT_USB_BASE + 0x5f0) 9514 /** USB_H_XFERSIZE7 : R/W; bitpos: [19:0]; default: 0; 9515 * Non-Scatter/Gather DMA Mode: Transfer Size. 9516 * Scatter/Gather DMA Mode: 9517 * [18:16]: Reserved 9518 * [15:8]: NTD (Number of Transfer Descriptors) 9519 */ 9520 #define USB_H_XFERSIZE7 0x0007FFFF 9521 #define USB_H_XFERSIZE7_M (USB_H_XFERSIZE7_V << USB_H_XFERSIZE7_S) 9522 #define USB_H_XFERSIZE7_V 0x0007FFFF 9523 #define USB_H_XFERSIZE7_S 0 9524 /** USB_H_PKTCNT7 : R/W; bitpos: [29:19]; default: 0; 9525 * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the 9526 * application with the expected number of packets to be transmitted (OUT) or received 9527 * (IN). 9528 * Scatter/Gather DMA Mode: Reserved. 9529 */ 9530 #define USB_H_PKTCNT7 0x000003FF 9531 #define USB_H_PKTCNT7_M (USB_H_PKTCNT7_V << USB_H_PKTCNT7_S) 9532 #define USB_H_PKTCNT7_V 0x000003FF 9533 #define USB_H_PKTCNT7_S 19 9534 /** USB_H_PID7 : R/W; bitpos: [31:29]; default: 0; 9535 * 2'b00: DATA0 9536 * 2'b01: DATA2 9537 * 2'b10: DATA1 9538 * 2'b11: MDATA (non-control)/SETUP (control) 9539 */ 9540 #define USB_H_PID7 0x00000003 9541 #define USB_H_PID7_M (USB_H_PID7_V << USB_H_PID7_S) 9542 #define USB_H_PID7_V 0x00000003 9543 #define USB_H_PID7_S 29 9544 /** USB_H_DOPNG7 : R/W; bitpos: [31]; default: 0; 9545 * This bit is used only for OUT transfers. Setting this field to 1 directs the host 9546 * to do PING protocol 9547 * 1'b0: No ping protocol 9548 * 1'b1: Ping protocol 9549 */ 9550 #define USB_H_DOPNG7 (BIT(31)) 9551 #define USB_H_DOPNG7_M (USB_H_DOPNG7_V << USB_H_DOPNG7_S) 9552 #define USB_H_DOPNG7_V 0x00000001 9553 #define USB_H_DOPNG7_S 31 9554 9555 9556 9557 9558 /** Status registers */ 9559 /** USB_GRXSTSR_REG register 9560 * Receive Status Debug Read Register 9561 */ 9562 #define USB_GRXSTSR_REG (SOC_DPORT_USB_BASE + 0x1c) 9563 /** USB_G_CHNUM : RO; bitpos: [4:0]; default: 0; 9564 * Channel Number: Host only. Indicates the channel number to which the current 9565 * received packet belongs. 9566 * Endpoint Number: Device only Indicates the endpoint number to which the current 9567 * received packet belongs 9568 */ 9569 #define USB_G_CHNUM 0x0000000F 9570 #define USB_G_CHNUM_M (USB_G_CHNUM_V << USB_G_CHNUM_S) 9571 #define USB_G_CHNUM_V 0x0000000F 9572 #define USB_G_CHNUM_S 0 9573 /** USB_G_BCNT : RO; bitpos: [15:4]; default: 0; 9574 * In host mode, indicates the byte count of the received IN data Packet 9575 * In device mode, indicates the byte count of the received data packet 9576 */ 9577 #define USB_G_BCNT 0x000007FF 9578 #define USB_G_BCNT_M (USB_G_BCNT_V << USB_G_BCNT_S) 9579 #define USB_G_BCNT_V 0x000007FF 9580 #define USB_G_BCNT_S 4 9581 /** USB_G_DPID : RO; bitpos: [17:15]; default: 0; 9582 * Data PID 9583 * 0x0 (DATA0): DATA0 9584 * 0x2 (DATA1): DATA1 9585 * 0x1 (DATA2): DATA2 9586 * 0x3 (MDATA): MDATA 9587 */ 9588 #define USB_G_DPID 0x00000003 9589 #define USB_G_DPID_M (USB_G_DPID_V << USB_G_DPID_S) 9590 #define USB_G_DPID_V 0x00000003 9591 #define USB_G_DPID_S 15 9592 /** USB_G_PKTSTS : RO; bitpos: [21:17]; default: 0; 9593 * 0x1 (OUTNAK): Global OUT NAK in device mode (triggers an Interrupt) 9594 * 0x2 (INOUTDPRX): IN data packet received in host mode and OUT data received in 9595 * device mode 9596 * 0x3 (INOUTTRCOM): IN or OUT transfer completed in both host and device (triggers 9597 * an interrupt) 9598 * 0x4 (DSETUPCOM): SETUP transaction completed in device mode (triggers an interrupt) 9599 * 0x5 (DTTOG): Data toggle error (triggers an interrupt) in host Mode 9600 * 0x6 (DSETUPRX): SETUP data packet received in device mode 9601 * 0x7 (CHHALT): Channel halted in host mode (triggers an interrupt) 9602 */ 9603 #define USB_G_PKTSTS 0x0000000F 9604 #define USB_G_PKTSTS_M (USB_G_PKTSTS_V << USB_G_PKTSTS_S) 9605 #define USB_G_PKTSTS_V 0x0000000F 9606 #define USB_G_PKTSTS_S 17 9607 /** USB_G_FN : RO; bitpos: [25:21]; default: 0; 9608 * This is the least significant 4 bits of the (micro)Frame number in which the packet 9609 * is received on the USB. This field is supported only when isochronous OUT endpoints 9610 * are supported 9611 */ 9612 #define USB_G_FN 0x0000000F 9613 #define USB_G_FN_M (USB_G_FN_V << USB_G_FN_S) 9614 #define USB_G_FN_V 0x0000000F 9615 #define USB_G_FN_S 21 9616 9617 9618 /** USB_GRXSTSP_REG register 9619 * Receive Status Read/Pop Register 9620 */ 9621 #define USB_GRXSTSP_REG (SOC_DPORT_USB_BASE + 0x20) 9622 /** USB_CHNUM : RO; bitpos: [4:0]; default: 0; 9623 * Channel Number: Host only. Indicates the channel number to which the current 9624 * received packet belongs. 9625 * Endpoint Number: Device only Indicates the endpoint number to which the current 9626 * received packet belongs 9627 */ 9628 #define USB_CHNUM 0x0000000F 9629 #define USB_CHNUM_M (USB_CHNUM_V << USB_CHNUM_S) 9630 #define USB_CHNUM_V 0x0000000F 9631 #define USB_CHNUM_S 0 9632 /** USB_BCNT : RO; bitpos: [15:4]; default: 0; 9633 * In host mode, indicates the byte count of the received IN data Packet 9634 * In device mode, indicates the byte count of the received data packet 9635 */ 9636 #define USB_BCNT 0x000007FF 9637 #define USB_BCNT_M (USB_BCNT_V << USB_BCNT_S) 9638 #define USB_BCNT_V 0x000007FF 9639 #define USB_BCNT_S 4 9640 /** USB_DPID : RO; bitpos: [17:15]; default: 0; 9641 * Data PID 9642 * 0x0 (DATA0): DATA0 9643 * 0x2 (DATA1): DATA1 9644 * 0x1 (DATA2): DATA2 9645 * 0x3 (MDATA): MDATA 9646 */ 9647 #define USB_DPID 0x00000003 9648 #define USB_DPID_M (USB_DPID_V << USB_DPID_S) 9649 #define USB_DPID_V 0x00000003 9650 #define USB_DPID_S 15 9651 /** USB_PKTSTS : RO; bitpos: [21:17]; default: 0; 9652 * 0x1 (OUTNAK): Global OUT NAK in device mode (triggers an Interrupt) 9653 * 0x2 (INOUTDPRX): IN data packet received in host mode and OUT data packet received 9654 * in device mode 9655 * 0x3 (INOUTTRCOM): IN or OUT transfer completed in both host and device mode 9656 * (triggers an interrupt) 9657 * 0x4 (DSETUPCOM): SETUP transaction completed in device mode (triggers an interrupt) 9658 * 0x5 (DTTOG): Data toggle error (triggers an interrupt) in host Mode 9659 * 0x6 (DSETUPRX): SETUP data packet received in device mode 9660 * 0x7 (CHHALT): Channel halted in host mode (triggers an interrupt) 9661 */ 9662 #define USB_PKTSTS 0x0000000F 9663 #define USB_PKTSTS_M (USB_PKTSTS_V << USB_PKTSTS_S) 9664 #define USB_PKTSTS_V 0x0000000F 9665 #define USB_PKTSTS_S 17 9666 /** USB_FN : RO; bitpos: [25:21]; default: 0; 9667 * This is the least significant 4 bits of the (micro)Frame number in which the packet 9668 * is received on the USB. This field is supported only when isochronous OUT endpoints 9669 * are supported 9670 */ 9671 #define USB_FN 0x0000000F 9672 #define USB_FN_M (USB_FN_V << USB_FN_S) 9673 #define USB_FN_V 0x0000000F 9674 #define USB_FN_S 21 9675 9676 9677 /** USB_GSNPSID_REG register 9678 * Synopsys ID Register 9679 */ 9680 #define USB_GSNPSID_REG (SOC_DPORT_USB_BASE + 0x40) 9681 /** USB_SYNOPSYSID : RO; bitpos: [32:0]; default: 1330921482; 9682 * ID register 9683 */ 9684 #define USB_SYNOPSYSID 0xFFFFFFFF 9685 #define USB_SYNOPSYSID_M (USB_SYNOPSYSID_V << USB_SYNOPSYSID_S) 9686 #define USB_SYNOPSYSID_V 0xFFFFFFFF 9687 #define USB_SYNOPSYSID_S 0 9688 9689 9690 /** USB_GHWCFG1_REG register 9691 * User Hardware Configuration 1 Register 9692 */ 9693 #define USB_GHWCFG1_REG (SOC_DPORT_USB_BASE + 0x44) 9694 /** USB_EPDIR : RO; bitpos: [32:0]; default: 0; 9695 * This 32-bit field uses two bits per endpoint to determine the endpoint direction. 9696 * Bits [31:30]: Endpoint 15 direction 9697 * Bits [29:28]: Endpoint 14 direction 9698 * ... 9699 * Direction: 9700 * 2'b00: BIDIR (IN and OUT) endpoint 9701 * 2'b01: IN endpoint 9702 * 2'b10: OUT endpoint 9703 * 2'b11: Reserved 9704 */ 9705 #define USB_EPDIR 0xFFFFFFFF 9706 #define USB_EPDIR_M (USB_EPDIR_V << USB_EPDIR_S) 9707 #define USB_EPDIR_V 0xFFFFFFFF 9708 #define USB_EPDIR_S 0 9709 9710 9711 /** USB_GHWCFG2_REG register 9712 * User Hardware Configuration 2 Register 9713 */ 9714 #define USB_GHWCFG2_REG (SOC_DPORT_USB_BASE + 0x48) 9715 /** USB_OTGMODE : RO; bitpos: [3:0]; default: 0; 9716 * 3'b000: HNP- and SRP-Capable OTG (Host Device) 9717 */ 9718 #define USB_OTGMODE 0x00000007 9719 #define USB_OTGMODE_M (USB_OTGMODE_V << USB_OTGMODE_S) 9720 #define USB_OTGMODE_V 0x00000007 9721 #define USB_OTGMODE_S 0 9722 /** USB_OTGARCH : RO; bitpos: [5:3]; default: 2; 9723 * 2'b10: Internal DMA 9724 */ 9725 #define USB_OTGARCH 0x00000003 9726 #define USB_OTGARCH_M (USB_OTGARCH_V << USB_OTGARCH_S) 9727 #define USB_OTGARCH_V 0x00000003 9728 #define USB_OTGARCH_S 3 9729 /** USB_SINGPNT : RO; bitpos: [5]; default: 1; 9730 * Point-to-Point 9731 * 1'b1: Single-point application (no hub and split support). 9732 */ 9733 #define USB_SINGPNT (BIT(5)) 9734 #define USB_SINGPNT_M (USB_SINGPNT_V << USB_SINGPNT_S) 9735 #define USB_SINGPNT_V 0x00000001 9736 #define USB_SINGPNT_S 5 9737 /** USB_HSPHYTYPE : RO; bitpos: [8:6]; default: 0; 9738 * High-Speed PHY Interface Type 9739 * 2'b00: High-Speed interface not supported 9740 */ 9741 #define USB_HSPHYTYPE 0x00000003 9742 #define USB_HSPHYTYPE_M (USB_HSPHYTYPE_V << USB_HSPHYTYPE_S) 9743 #define USB_HSPHYTYPE_V 0x00000003 9744 #define USB_HSPHYTYPE_S 6 9745 /** USB_FSPHYTYPE : RO; bitpos: [10:8]; default: 1; 9746 * Full-Speed PHY Interface Type. 9747 */ 9748 #define USB_FSPHYTYPE 0x00000003 9749 #define USB_FSPHYTYPE_M (USB_FSPHYTYPE_V << USB_FSPHYTYPE_S) 9750 #define USB_FSPHYTYPE_V 0x00000003 9751 #define USB_FSPHYTYPE_S 8 9752 /** USB_NUMDEVEPS : RO; bitpos: [14:10]; default: 6; 9753 * Number of Device Endpoints. 9754 */ 9755 #define USB_NUMDEVEPS 0x0000000F 9756 #define USB_NUMDEVEPS_M (USB_NUMDEVEPS_V << USB_NUMDEVEPS_S) 9757 #define USB_NUMDEVEPS_V 0x0000000F 9758 #define USB_NUMDEVEPS_S 10 9759 /** USB_NUMHSTCHNL : RO; bitpos: [18:14]; default: 7; 9760 * Number of Host Channels. 9761 */ 9762 #define USB_NUMHSTCHNL 0x0000000F 9763 #define USB_NUMHSTCHNL_M (USB_NUMHSTCHNL_V << USB_NUMHSTCHNL_S) 9764 #define USB_NUMHSTCHNL_V 0x0000000F 9765 #define USB_NUMHSTCHNL_S 14 9766 /** USB_PERIOSUPPORT : RO; bitpos: [18]; default: 1; 9767 * 1'b0:Periodic OUT Channels is not Supported in Host Mode 9768 * 1'b1:Periodic OUT Channels Supported in Host Mode 9769 */ 9770 #define USB_PERIOSUPPORT (BIT(18)) 9771 #define USB_PERIOSUPPORT_M (USB_PERIOSUPPORT_V << USB_PERIOSUPPORT_S) 9772 #define USB_PERIOSUPPORT_V 0x00000001 9773 #define USB_PERIOSUPPORT_S 18 9774 /** USB_DYNFIFOSIZING : RO; bitpos: [19]; default: 1; 9775 * 1'b0:Dynamic FIFO Sizing Disabled 9776 * 1'b1:Dynamic FIFO Sizing Enabled 9777 */ 9778 #define USB_DYNFIFOSIZING (BIT(19)) 9779 #define USB_DYNFIFOSIZING_M (USB_DYNFIFOSIZING_V << USB_DYNFIFOSIZING_S) 9780 #define USB_DYNFIFOSIZING_V 0x00000001 9781 #define USB_DYNFIFOSIZING_S 19 9782 /** USB_MULTIPROCINTRPT : RO; bitpos: [20]; default: 0; 9783 * 1'b0: No Multi Processor Interrupt Enabled 9784 * 1'b1:Multi Processor Interrupt Enabled 9785 */ 9786 #define USB_MULTIPROCINTRPT (BIT(20)) 9787 #define USB_MULTIPROCINTRPT_M (USB_MULTIPROCINTRPT_V << USB_MULTIPROCINTRPT_S) 9788 #define USB_MULTIPROCINTRPT_V 0x00000001 9789 #define USB_MULTIPROCINTRPT_S 20 9790 /** USB_NPTXQDEPTH : RO; bitpos: [24:22]; default: 1; 9791 * Non-periodic Request Queue Depth 9792 * 2'b01: 4 9793 */ 9794 #define USB_NPTXQDEPTH 0x00000003 9795 #define USB_NPTXQDEPTH_M (USB_NPTXQDEPTH_V << USB_NPTXQDEPTH_S) 9796 #define USB_NPTXQDEPTH_V 0x00000003 9797 #define USB_NPTXQDEPTH_S 22 9798 /** USB_PTXQDEPTH : RO; bitpos: [26:24]; default: 2; 9799 * Host Mode Periodic Request Queue Depth. 9800 * 2'b10: 8 9801 */ 9802 #define USB_PTXQDEPTH 0x00000003 9803 #define USB_PTXQDEPTH_M (USB_PTXQDEPTH_V << USB_PTXQDEPTH_S) 9804 #define USB_PTXQDEPTH_V 0x00000003 9805 #define USB_PTXQDEPTH_S 24 9806 /** USB_TKNQDEPTH : RO; bitpos: [31:26]; default: 8; 9807 * Device Mode IN Token Sequence Learning Queue Depth. 9808 */ 9809 #define USB_TKNQDEPTH 0x0000001F 9810 #define USB_TKNQDEPTH_M (USB_TKNQDEPTH_V << USB_TKNQDEPTH_S) 9811 #define USB_TKNQDEPTH_V 0x0000001F 9812 #define USB_TKNQDEPTH_S 26 9813 /** USB_OTG_ENABLE_IC_USB : RO; bitpos: [31]; default: 0; 9814 * 0x0 (DISABLE): Disabled the IC_USB Full-Speed Serial Transceiver interface 9815 * 0x1 (ENABLE): Enabled the IC_USB Full-Speed Serial Transceiver interface 9816 */ 9817 #define USB_OTG_ENABLE_IC_USB (BIT(31)) 9818 #define USB_OTG_ENABLE_IC_USB_M (USB_OTG_ENABLE_IC_USB_V << USB_OTG_ENABLE_IC_USB_S) 9819 #define USB_OTG_ENABLE_IC_USB_V 0x00000001 9820 #define USB_OTG_ENABLE_IC_USB_S 31 9821 9822 9823 /** USB_GHWCFG3_REG register 9824 * User Hardware Configuration 3 Register 9825 */ 9826 #define USB_GHWCFG3_REG (SOC_DPORT_USB_BASE + 0x4c) 9827 /** USB_XFERSIZEWIDTH : RO; bitpos: [4:0]; default: 5; 9828 * Width of Transfer Size Counters 9829 * 0x5 (WIDTH16): Width of Transfer Size Counter 16 bits 9830 */ 9831 #define USB_XFERSIZEWIDTH 0x0000000F 9832 #define USB_XFERSIZEWIDTH_M (USB_XFERSIZEWIDTH_V << USB_XFERSIZEWIDTH_S) 9833 #define USB_XFERSIZEWIDTH_V 0x0000000F 9834 #define USB_XFERSIZEWIDTH_S 0 9835 /** USB_PKTSIZEWIDTH : RO; bitpos: [7:4]; default: 3; 9836 * Width of Packet Size Counters 9837 * 3'b011: 7 bits 9838 */ 9839 #define USB_PKTSIZEWIDTH 0x00000007 9840 #define USB_PKTSIZEWIDTH_M (USB_PKTSIZEWIDTH_V << USB_PKTSIZEWIDTH_S) 9841 #define USB_PKTSIZEWIDTH_V 0x00000007 9842 #define USB_PKTSIZEWIDTH_S 4 9843 /** USB_OTGEN : RO; bitpos: [7]; default: 1; 9844 * OTG Function Enabled. 9845 */ 9846 #define USB_OTGEN (BIT(7)) 9847 #define USB_OTGEN_M (USB_OTGEN_V << USB_OTGEN_S) 9848 #define USB_OTGEN_V 0x00000001 9849 #define USB_OTGEN_S 7 9850 /** USB_I2CINTSEL : RO; bitpos: [8]; default: 0; 9851 * 1'b0: I2C Interface is not available on the controller. 9852 */ 9853 #define USB_I2CINTSEL (BIT(8)) 9854 #define USB_I2CINTSEL_M (USB_I2CINTSEL_V << USB_I2CINTSEL_S) 9855 #define USB_I2CINTSEL_V 0x00000001 9856 #define USB_I2CINTSEL_S 8 9857 /** USB_VNDCTLSUPT : RO; bitpos: [9]; default: 0; 9858 * Vendor Control Interface is not available . 9859 */ 9860 #define USB_VNDCTLSUPT (BIT(9)) 9861 #define USB_VNDCTLSUPT_M (USB_VNDCTLSUPT_V << USB_VNDCTLSUPT_S) 9862 #define USB_VNDCTLSUPT_V 0x00000001 9863 #define USB_VNDCTLSUPT_S 9 9864 /** USB_OPTFEATURE : RO; bitpos: [10]; default: 1; 9865 * Optional Features have been Removed. 9866 */ 9867 #define USB_OPTFEATURE (BIT(10)) 9868 #define USB_OPTFEATURE_M (USB_OPTFEATURE_V << USB_OPTFEATURE_S) 9869 #define USB_OPTFEATURE_V 0x00000001 9870 #define USB_OPTFEATURE_S 10 9871 /** USB_RSTTYPE : RO; bitpos: [11]; default: 0; 9872 * Asynchronous reset is used in the core 9873 */ 9874 #define USB_RSTTYPE (BIT(11)) 9875 #define USB_RSTTYPE_M (USB_RSTTYPE_V << USB_RSTTYPE_S) 9876 #define USB_RSTTYPE_V 0x00000001 9877 #define USB_RSTTYPE_S 11 9878 /** USB_ADPSUPPORT : RO; bitpos: [12]; default: 0; 9879 * ADP logic is not present along with the controller. 9880 */ 9881 #define USB_ADPSUPPORT (BIT(12)) 9882 #define USB_ADPSUPPORT_M (USB_ADPSUPPORT_V << USB_ADPSUPPORT_S) 9883 #define USB_ADPSUPPORT_V 0x00000001 9884 #define USB_ADPSUPPORT_S 12 9885 /** USB_HSICMODE : RO; bitpos: [13]; default: 0; 9886 * HSIC mode specified for Mode of Operation. 9887 * 1'b0: Non-HSIC-capable 9888 */ 9889 #define USB_HSICMODE (BIT(13)) 9890 #define USB_HSICMODE_M (USB_HSICMODE_V << USB_HSICMODE_S) 9891 #define USB_HSICMODE_V 0x00000001 9892 #define USB_HSICMODE_S 13 9893 /** USB_BCSUPPORT : RO; bitpos: [14]; default: 0; 9894 * 1'b0: No Battery Charger Support 9895 */ 9896 #define USB_BCSUPPORT (BIT(14)) 9897 #define USB_BCSUPPORT_M (USB_BCSUPPORT_V << USB_BCSUPPORT_S) 9898 #define USB_BCSUPPORT_V 0x00000001 9899 #define USB_BCSUPPORT_S 14 9900 /** USB_LPMMODE : RO; bitpos: [15]; default: 0; 9901 * LPM mode specified for Mode of Operation. 9902 */ 9903 #define USB_LPMMODE (BIT(15)) 9904 #define USB_LPMMODE_M (USB_LPMMODE_V << USB_LPMMODE_S) 9905 #define USB_LPMMODE_V 0x00000001 9906 #define USB_LPMMODE_S 15 9907 /** USB_DFIFODEPTH : RO; bitpos: [32:16]; default: 256; 9908 * DFIFO Depth.This value is in terms of 32-bit words. 9909 */ 9910 #define USB_DFIFODEPTH 0x0000FFFF 9911 #define USB_DFIFODEPTH_M (USB_DFIFODEPTH_V << USB_DFIFODEPTH_S) 9912 #define USB_DFIFODEPTH_V 0x0000FFFF 9913 #define USB_DFIFODEPTH_S 16 9914 9915 9916 /** USB_GHWCFG4_REG register 9917 * User Hardware Configuration 4 Register 9918 */ 9919 #define USB_GHWCFG4_REG (SOC_DPORT_USB_BASE + 0x50) 9920 /** USB_G_NUMDEVPERIOEPS : RO; bitpos: [4:0]; default: 0; 9921 * Number of Device Mode Periodic IN Endpoints. 9922 */ 9923 #define USB_G_NUMDEVPERIOEPS 0x0000000F 9924 #define USB_G_NUMDEVPERIOEPS_M (USB_G_NUMDEVPERIOEPS_V << USB_G_NUMDEVPERIOEPS_S) 9925 #define USB_G_NUMDEVPERIOEPS_V 0x0000000F 9926 #define USB_G_NUMDEVPERIOEPS_S 0 9927 /** USB_G_PARTIALPWRDN : RO; bitpos: [4]; default: 1; 9928 * Enable Partial Power Down. 9929 */ 9930 #define USB_G_PARTIALPWRDN (BIT(4)) 9931 #define USB_G_PARTIALPWRDN_M (USB_G_PARTIALPWRDN_V << USB_G_PARTIALPWRDN_S) 9932 #define USB_G_PARTIALPWRDN_V 0x00000001 9933 #define USB_G_PARTIALPWRDN_S 4 9934 /** USB_G_AHBFREQ : RO; bitpos: [5]; default: 1; 9935 * Minimum AHB Frequency Less Than 60 MHz 9936 */ 9937 #define USB_G_AHBFREQ (BIT(5)) 9938 #define USB_G_AHBFREQ_M (USB_G_AHBFREQ_V << USB_G_AHBFREQ_S) 9939 #define USB_G_AHBFREQ_V 0x00000001 9940 #define USB_G_AHBFREQ_S 5 9941 /** USB_G_HIBERNATION : RO; bitpos: [6]; default: 0; 9942 * 1'b0: Hibernation feature not enabled. 9943 */ 9944 #define USB_G_HIBERNATION (BIT(6)) 9945 #define USB_G_HIBERNATION_M (USB_G_HIBERNATION_V << USB_G_HIBERNATION_S) 9946 #define USB_G_HIBERNATION_V 0x00000001 9947 #define USB_G_HIBERNATION_S 6 9948 /** USB_G_EXTENDEDHIBERNATION : RO; bitpos: [7]; default: 0; 9949 * Extended Hibernation feature not enabled 9950 */ 9951 #define USB_G_EXTENDEDHIBERNATION (BIT(7)) 9952 #define USB_G_EXTENDEDHIBERNATION_M (USB_G_EXTENDEDHIBERNATION_V << USB_G_EXTENDEDHIBERNATION_S) 9953 #define USB_G_EXTENDEDHIBERNATION_V 0x00000001 9954 #define USB_G_EXTENDEDHIBERNATION_S 7 9955 /** USB_G_ACGSUPT : RO; bitpos: [12]; default: 0; 9956 * Active Clock Gating is not enabled. 9957 */ 9958 #define USB_G_ACGSUPT (BIT(12)) 9959 #define USB_G_ACGSUPT_M (USB_G_ACGSUPT_V << USB_G_ACGSUPT_S) 9960 #define USB_G_ACGSUPT_V 0x00000001 9961 #define USB_G_ACGSUPT_S 12 9962 /** USB_G_ENHANCEDLPMSUPT : RO; bitpos: [13]; default: 1; 9963 * Enhanced LPM Support. 9964 */ 9965 #define USB_G_ENHANCEDLPMSUPT (BIT(13)) 9966 #define USB_G_ENHANCEDLPMSUPT_M (USB_G_ENHANCEDLPMSUPT_V << USB_G_ENHANCEDLPMSUPT_S) 9967 #define USB_G_ENHANCEDLPMSUPT_V 0x00000001 9968 #define USB_G_ENHANCEDLPMSUPT_S 13 9969 /** USB_G_PHYDATAWIDTH : RO; bitpos: [16:14]; default: 2; 9970 * UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width (PhyDataWidth) When a ULPI PHY 9971 * is used, an internal wrapper converts ULPI to UTMI+ 9972 * 2'b10: 8/16 bits, software selectable 9973 */ 9974 #define USB_G_PHYDATAWIDTH 0x00000003 9975 #define USB_G_PHYDATAWIDTH_M (USB_G_PHYDATAWIDTH_V << USB_G_PHYDATAWIDTH_S) 9976 #define USB_G_PHYDATAWIDTH_V 0x00000003 9977 #define USB_G_PHYDATAWIDTH_S 14 9978 /** USB_G_NUMCTLEPS : RO; bitpos: [20:16]; default: 0; 9979 * Number of Device Mode Control Endpoints in Addition to Endpoint 0 9980 */ 9981 #define USB_G_NUMCTLEPS 0x0000000F 9982 #define USB_G_NUMCTLEPS_M (USB_G_NUMCTLEPS_V << USB_G_NUMCTLEPS_S) 9983 #define USB_G_NUMCTLEPS_V 0x0000000F 9984 #define USB_G_NUMCTLEPS_S 16 9985 /** USB_G_IDDQFLTR : RO; bitpos: [20]; default: 1; 9986 * IDDIG Filter Enable. 9987 */ 9988 #define USB_G_IDDQFLTR (BIT(20)) 9989 #define USB_G_IDDQFLTR_M (USB_G_IDDQFLTR_V << USB_G_IDDQFLTR_S) 9990 #define USB_G_IDDQFLTR_V 0x00000001 9991 #define USB_G_IDDQFLTR_S 20 9992 /** USB_G_VBUSVALIDFLTR : RO; bitpos: [21]; default: 1; 9993 * VBUS Valid Filter Enabled. 9994 */ 9995 #define USB_G_VBUSVALIDFLTR (BIT(21)) 9996 #define USB_G_VBUSVALIDFLTR_M (USB_G_VBUSVALIDFLTR_V << USB_G_VBUSVALIDFLTR_S) 9997 #define USB_G_VBUSVALIDFLTR_V 0x00000001 9998 #define USB_G_VBUSVALIDFLTR_S 21 9999 /** USB_G_AVALIDFLTR : RO; bitpos: [22]; default: 1; 10000 * a_valid Filter Enabled. 10001 */ 10002 #define USB_G_AVALIDFLTR (BIT(22)) 10003 #define USB_G_AVALIDFLTR_M (USB_G_AVALIDFLTR_V << USB_G_AVALIDFLTR_S) 10004 #define USB_G_AVALIDFLTR_V 0x00000001 10005 #define USB_G_AVALIDFLTR_S 22 10006 /** USB_G_BVALIDFLTR : RO; bitpos: [23]; default: 1; 10007 * b_valid Filter Enabled. 10008 */ 10009 #define USB_G_BVALIDFLTR (BIT(23)) 10010 #define USB_G_BVALIDFLTR_M (USB_G_BVALIDFLTR_V << USB_G_BVALIDFLTR_S) 10011 #define USB_G_BVALIDFLTR_V 0x00000001 10012 #define USB_G_BVALIDFLTR_S 23 10013 /** USB_G_SESSENDFLTR : RO; bitpos: [24]; default: 1; 10014 * session_end Filter Enabled. 10015 */ 10016 #define USB_G_SESSENDFLTR (BIT(24)) 10017 #define USB_G_SESSENDFLTR_M (USB_G_SESSENDFLTR_V << USB_G_SESSENDFLTR_S) 10018 #define USB_G_SESSENDFLTR_V 0x00000001 10019 #define USB_G_SESSENDFLTR_S 24 10020 /** USB_G_DEDFIFOMODE : RO; bitpos: [25]; default: 1; 10021 * Enable Dedicated Transmit FIFO for device IN Endpoints 10022 */ 10023 #define USB_G_DEDFIFOMODE (BIT(25)) 10024 #define USB_G_DEDFIFOMODE_M (USB_G_DEDFIFOMODE_V << USB_G_DEDFIFOMODE_S) 10025 #define USB_G_DEDFIFOMODE_V 0x00000001 10026 #define USB_G_DEDFIFOMODE_S 25 10027 /** USB_G_INEPS : RO; bitpos: [30:26]; default: 4; 10028 * Number of Device Mode IN Endpoints Including Control Endpoints. 10029 */ 10030 #define USB_G_INEPS 0x0000000F 10031 #define USB_G_INEPS_M (USB_G_INEPS_V << USB_G_INEPS_S) 10032 #define USB_G_INEPS_V 0x0000000F 10033 #define USB_G_INEPS_S 26 10034 /** USB_G_DESCDMAENABLED : RO; bitpos: [30]; default: 1; 10035 * 0x1: Scatter/Gather DMA configuration. 10036 */ 10037 #define USB_G_DESCDMAENABLED (BIT(30)) 10038 #define USB_G_DESCDMAENABLED_M (USB_G_DESCDMAENABLED_V << USB_G_DESCDMAENABLED_S) 10039 #define USB_G_DESCDMAENABLED_V 0x00000001 10040 #define USB_G_DESCDMAENABLED_S 30 10041 /** USB_G_DESCDMA : RO; bitpos: [31]; default: 1; 10042 * Scatter/Gather DMA configuration 10043 * 1'b1: Dynamic configuration 10044 */ 10045 #define USB_G_DESCDMA (BIT(31)) 10046 #define USB_G_DESCDMA_M (USB_G_DESCDMA_V << USB_G_DESCDMA_S) 10047 #define USB_G_DESCDMA_V 0x00000001 10048 #define USB_G_DESCDMA_S 31 10049 10050 10051 /** USB_HFNUM_REG register 10052 * Frame Number configure Resigster 10053 */ 10054 #define USB_HFNUM_REG (SOC_DPORT_USB_BASE + 0x408) 10055 /** USB_FRNUM : RO; bitpos: [14:0]; default: 16383; 10056 * Frame Number 10057 * 0x0 (INACTIVE): No SOF is transmitted 10058 * 0x1 (ACTIVE): SOF is transmitted 10059 */ 10060 #define USB_FRNUM 0x00003FFF 10061 #define USB_FRNUM_M (USB_FRNUM_V << USB_FRNUM_S) 10062 #define USB_FRNUM_V 0x00003FFF 10063 #define USB_FRNUM_S 0 10064 /** USB_FRREM : RO; bitpos: [32:16]; default: 0; 10065 * Frame Time Remaining.ndicates the amount of time remaining in the current 10066 * microframe 10067 * (HS) or Frame (FS/LS), in terms of PHY clocks. 10068 */ 10069 #define USB_FRREM 0x0000FFFF 10070 #define USB_FRREM_M (USB_FRREM_V << USB_FRREM_S) 10071 #define USB_FRREM_V 0x0000FFFF 10072 #define USB_FRREM_S 16 10073 10074 10075 /** USB_HPTXSTS_REG register 10076 * Host Periodic Transmit FIFO/Queue Status Register 10077 */ 10078 #define USB_HPTXSTS_REG (SOC_DPORT_USB_BASE + 0x410) 10079 /** USB_PTXFSPCAVAIL : RO; bitpos: [16:0]; default: 256; 10080 * Periodic Transmit Data FIFO Space Available. Values are in terms of 32-bit words. 10081 */ 10082 #define USB_PTXFSPCAVAIL 0x0000FFFF 10083 #define USB_PTXFSPCAVAIL_M (USB_PTXFSPCAVAIL_V << USB_PTXFSPCAVAIL_S) 10084 #define USB_PTXFSPCAVAIL_V 0x0000FFFF 10085 #define USB_PTXFSPCAVAIL_S 0 10086 /** USB_PTXQSPCAVAIL : RO; bitpos: [21:16]; default: 8; 10087 * Periodic Transmit Request Queue Space Available. 10088 */ 10089 #define USB_PTXQSPCAVAIL 0x0000001F 10090 #define USB_PTXQSPCAVAIL_M (USB_PTXQSPCAVAIL_V << USB_PTXQSPCAVAIL_S) 10091 #define USB_PTXQSPCAVAIL_V 0x0000001F 10092 #define USB_PTXQSPCAVAIL_S 16 10093 /** USB_PTXQTOP : RO; bitpos: [32:24]; default: 0; 10094 * Bit [31]: Odd/Even (micro)Frame. 1'b0: send in even (micro)Frame 10095 * Bits [30:27]: Channel/endpoint number 10096 * Bits [26:25]: Type. 2'b00: IN/OUT. 2'b01: Zero-length packet. 2'b10: CSPLIT 10097 * 2'b11: Disable channel command 10098 * Bit [24]: Terminate 10099 */ 10100 #define USB_PTXQTOP 0x000000FF 10101 #define USB_PTXQTOP_M (USB_PTXQTOP_V << USB_PTXQTOP_S) 10102 #define USB_PTXQTOP_V 0x000000FF 10103 #define USB_PTXQTOP_S 24 10104 10105 10106 /** USB_HCDMAB$n_REG register 10107 * Host Channel $n DMA Buffer Address Register 10108 */ 10109 #define USB_HCDMAB$N_REG (SOC_DPORT_USB_BASE + 0x51c) 10110 /** USB_H_HCDMAB0 : RO; bitpos: [32:0]; default: 0; 10111 * Holds the current buffer address 10112 */ 10113 #define USB_H_HCDMAB0 0xFFFFFFFF 10114 #define USB_H_HCDMAB0_M (USB_H_HCDMAB0_V << USB_H_HCDMAB0_S) 10115 #define USB_H_HCDMAB0_V 0xFFFFFFFF 10116 #define USB_H_HCDMAB0_S 0 10117 10118 10119 /** USB_HCDMAB1_REG register 10120 * Host Channel 1 DMA Buffer Address Register 10121 */ 10122 #define USB_HCDMAB1_REG (SOC_DPORT_USB_BASE + 0x53c) 10123 /** USB_H_HCDMAB1 : RO; bitpos: [32:0]; default: 0; 10124 * Holds the current buffer address 10125 */ 10126 #define USB_H_HCDMAB1 0xFFFFFFFF 10127 #define USB_H_HCDMAB1_M (USB_H_HCDMAB1_V << USB_H_HCDMAB1_S) 10128 #define USB_H_HCDMAB1_V 0xFFFFFFFF 10129 #define USB_H_HCDMAB1_S 0 10130 10131 10132 /** USB_HCDMAB2_REG register 10133 * Host Channel 2 DMA Buffer Address Register 10134 */ 10135 #define USB_HCDMAB2_REG (SOC_DPORT_USB_BASE + 0x55c) 10136 /** USB_H_HCDMAB2 : RO; bitpos: [32:0]; default: 0; 10137 * Holds the current buffer address 10138 */ 10139 #define USB_H_HCDMAB2 0xFFFFFFFF 10140 #define USB_H_HCDMAB2_M (USB_H_HCDMAB2_V << USB_H_HCDMAB2_S) 10141 #define USB_H_HCDMAB2_V 0xFFFFFFFF 10142 #define USB_H_HCDMAB2_S 0 10143 10144 10145 /** USB_HCDMAB3_REG register 10146 * Host Channel 3 DMA Buffer Address Register 10147 */ 10148 #define USB_HCDMAB3_REG (SOC_DPORT_USB_BASE + 0x57c) 10149 /** USB_H_HCDMAB3 : RO; bitpos: [32:0]; default: 0; 10150 * Holds the current buffer address 10151 */ 10152 #define USB_H_HCDMAB3 0xFFFFFFFF 10153 #define USB_H_HCDMAB3_M (USB_H_HCDMAB3_V << USB_H_HCDMAB3_S) 10154 #define USB_H_HCDMAB3_V 0xFFFFFFFF 10155 #define USB_H_HCDMAB3_S 0 10156 10157 10158 /** USB_HCDMAB4_REG register 10159 * Host Channel 4 DMA Buffer Address Register 10160 */ 10161 #define USB_HCDMAB4_REG (SOC_DPORT_USB_BASE + 0x59c) 10162 /** USB_H_HCDMAB4 : RO; bitpos: [32:0]; default: 0; 10163 * Holds the current buffer address 10164 */ 10165 #define USB_H_HCDMAB4 0xFFFFFFFF 10166 #define USB_H_HCDMAB4_M (USB_H_HCDMAB4_V << USB_H_HCDMAB4_S) 10167 #define USB_H_HCDMAB4_V 0xFFFFFFFF 10168 #define USB_H_HCDMAB4_S 0 10169 10170 10171 /** USB_HCDMAB5_REG register 10172 * Host Channel 5 DMA Buffer Address Register 10173 */ 10174 #define USB_HCDMAB5_REG (SOC_DPORT_USB_BASE + 0x5bc) 10175 /** USB_H_HCDMAB5 : RO; bitpos: [32:0]; default: 0; 10176 * Holds the current buffer address 10177 */ 10178 #define USB_H_HCDMAB5 0xFFFFFFFF 10179 #define USB_H_HCDMAB5_M (USB_H_HCDMAB5_V << USB_H_HCDMAB5_S) 10180 #define USB_H_HCDMAB5_V 0xFFFFFFFF 10181 #define USB_H_HCDMAB5_S 0 10182 10183 10184 /** USB_HCDMAB6_REG register 10185 * Host Channel 6 DMA Buffer Address Register 10186 */ 10187 #define USB_HCDMAB6_REG (SOC_DPORT_USB_BASE + 0x5dc) 10188 /** USB_H_HCDMAB6 : RO; bitpos: [32:0]; default: 0; 10189 * Holds the current buffer address 10190 */ 10191 #define USB_H_HCDMAB6 0xFFFFFFFF 10192 #define USB_H_HCDMAB6_M (USB_H_HCDMAB6_V << USB_H_HCDMAB6_S) 10193 #define USB_H_HCDMAB6_V 0xFFFFFFFF 10194 #define USB_H_HCDMAB6_S 0 10195 10196 10197 /** USB_HCDMAB7_REG register 10198 * Host Channel 7 DMA Buffer Address Register 10199 */ 10200 #define USB_HCDMAB7_REG (SOC_DPORT_USB_BASE + 0x5fc) 10201 /** USB_H_HCDMAB7 : RO; bitpos: [32:0]; default: 0; 10202 * Holds the current buffer address 10203 */ 10204 #define USB_H_HCDMAB7 0xFFFFFFFF 10205 #define USB_H_HCDMAB7_M (USB_H_HCDMAB7_V << USB_H_HCDMAB7_S) 10206 #define USB_H_HCDMAB7_V 0xFFFFFFFF 10207 #define USB_H_HCDMAB7_S 0 10208 10209 10210 /** USB_DSTS_REG register 10211 * Device Status Register 10212 */ 10213 #define USB_DSTS_REG (SOC_DPORT_USB_BASE + 0x808) 10214 /** USB_SUSPSTS : RO; bitpos: [0]; default: 0; 10215 * Suspend Status 10216 * 0x0 : No suspend state 10217 * 0x1 : Suspend state 10218 */ 10219 #define USB_SUSPSTS (BIT(0)) 10220 #define USB_SUSPSTS_M (USB_SUSPSTS_V << USB_SUSPSTS_S) 10221 #define USB_SUSPSTS_V 0x00000001 10222 #define USB_SUSPSTS_S 0 10223 /** USB_ENUMSPD : RO; bitpos: [3:1]; default: 1; 10224 * 0x0 : High speed (PHY clock is running at 30 or 60 MHz) 10225 * 0x1 : Full speed (PHY clock is running at 30 or 60 MHz) 10226 * 0x2 : Low speed (PHY clock is running at 6 MHz) 10227 * 0x3 : Full speed (PHY clock is running at 48 MHz) 10228 */ 10229 #define USB_ENUMSPD 0x00000003 10230 #define USB_ENUMSPD_M (USB_ENUMSPD_V << USB_ENUMSPD_S) 10231 #define USB_ENUMSPD_V 0x00000003 10232 #define USB_ENUMSPD_S 1 10233 /** USB_ERRTICERR : RO; bitpos: [3]; default: 0; 10234 * 0x0 : No Erratic Error 10235 * 0x1 : Erratic Error 10236 */ 10237 #define USB_ERRTICERR (BIT(3)) 10238 #define USB_ERRTICERR_M (USB_ERRTICERR_V << USB_ERRTICERR_S) 10239 #define USB_ERRTICERR_V 0x00000001 10240 #define USB_ERRTICERR_S 3 10241 /** USB_SOFFN : RO; bitpos: [22:8]; default: 0; 10242 * Frame or Microframe Number of the Received SOF (SOFFN). This field contains a 10243 * Frame number. 10244 */ 10245 #define USB_SOFFN 0x00003FFF 10246 #define USB_SOFFN_M (USB_SOFFN_V << USB_SOFFN_S) 10247 #define USB_SOFFN_V 0x00003FFF 10248 #define USB_SOFFN_S 8 10249 /** USB_DEVLNSTS : RO; bitpos: [24:22]; default: 0; 10250 * Device Line Status 10251 * DevLnSts[1]: Logic level of D+ 10252 * DevLnSts[0]: Logic level of D- 10253 */ 10254 #define USB_DEVLNSTS 0x00000003 10255 #define USB_DEVLNSTS_M (USB_DEVLNSTS_V << USB_DEVLNSTS_S) 10256 #define USB_DEVLNSTS_V 0x00000003 10257 #define USB_DEVLNSTS_S 22 10258 10259 10260 /** USB_DTXFSTS0_REG register 10261 * Device IN Endpoint Transmit FIFO Status Register 0 10262 */ 10263 #define USB_DTXFSTS0_REG (SOC_DPORT_USB_BASE + 0x918) 10264 /** USB_D_INEPTXFSPCAVAIL0 : RO; bitpos: [16:0]; default: 0; 10265 * Indicates the amount of free space available in the Endpoint TxFIFO. 10266 */ 10267 #define USB_D_INEPTXFSPCAVAIL0 0x0000FFFF 10268 #define USB_D_INEPTXFSPCAVAIL0_M (USB_D_INEPTXFSPCAVAIL0_V << USB_D_INEPTXFSPCAVAIL0_S) 10269 #define USB_D_INEPTXFSPCAVAIL0_V 0x0000FFFF 10270 #define USB_D_INEPTXFSPCAVAIL0_S 0 10271 10272 10273 /** USB_DIEPDMAB0_REG register 10274 * Device IN Endpoint 16 Buffer Address Register 10275 */ 10276 #define USB_DIEPDMAB0_REG (SOC_DPORT_USB_BASE + 0x91c) 10277 /** USB_D_DMABUFFERADDR0 : RO; bitpos: [32:0]; default: 0; 10278 * Holds the current buffer address.This register is updated as and when the data 10279 * transfer for the corresponding end point is in progress. This register is present 10280 * only in Scatter/Gather DMA mode. Otherwise this field is reserved. 10281 */ 10282 #define USB_D_DMABUFFERADDR0 0xFFFFFFFF 10283 #define USB_D_DMABUFFERADDR0_M (USB_D_DMABUFFERADDR0_V << USB_D_DMABUFFERADDR0_S) 10284 #define USB_D_DMABUFFERADDR0_V 0xFFFFFFFF 10285 #define USB_D_DMABUFFERADDR0_S 0 10286 10287 10288 /** USB_DTXFSTS1_REG register 10289 * Device IN Endpoint Transmit FIFO Status Register 1 10290 */ 10291 #define USB_DTXFSTS1_REG (SOC_DPORT_USB_BASE + 0x938) 10292 /** USB_D_INEPTXFSPCAVAIL1 : RO; bitpos: [16:0]; default: 0; 10293 * Indicates the amount of free space available in the Endpoint TxFIFO. 10294 */ 10295 #define USB_D_INEPTXFSPCAVAIL1 0x0000FFFF 10296 #define USB_D_INEPTXFSPCAVAIL1_M (USB_D_INEPTXFSPCAVAIL1_V << USB_D_INEPTXFSPCAVAIL1_S) 10297 #define USB_D_INEPTXFSPCAVAIL1_V 0x0000FFFF 10298 #define USB_D_INEPTXFSPCAVAIL1_S 0 10299 10300 10301 /** USB_DIEPDMAB1_REG register 10302 * Device IN Endpoint 16 Buffer Address Register 10303 */ 10304 #define USB_DIEPDMAB1_REG (SOC_DPORT_USB_BASE + 0x93c) 10305 /** USB_D_DMABUFFERADDR1 : RO; bitpos: [32:0]; default: 0; 10306 * Holds the current buffer address.This register is updated as and when the data 10307 * transfer for the corresponding end point is in progress. This register is present 10308 * only in Scatter/Gather DMA mode. Otherwise this field is reserved. 10309 */ 10310 #define USB_D_DMABUFFERADDR1 0xFFFFFFFF 10311 #define USB_D_DMABUFFERADDR1_M (USB_D_DMABUFFERADDR1_V << USB_D_DMABUFFERADDR1_S) 10312 #define USB_D_DMABUFFERADDR1_V 0xFFFFFFFF 10313 #define USB_D_DMABUFFERADDR1_S 0 10314 10315 10316 /** USB_DTXFSTS2_REG register 10317 * Device IN Endpoint Transmit FIFO Status Register 2 10318 */ 10319 #define USB_DTXFSTS2_REG (SOC_DPORT_USB_BASE + 0x958) 10320 /** USB_D_INEPTXFSPCAVAIL2 : RO; bitpos: [16:0]; default: 0; 10321 * Indicates the amount of free space available in the Endpoint TxFIFO. 10322 */ 10323 #define USB_D_INEPTXFSPCAVAIL2 0x0000FFFF 10324 #define USB_D_INEPTXFSPCAVAIL2_M (USB_D_INEPTXFSPCAVAIL2_V << USB_D_INEPTXFSPCAVAIL2_S) 10325 #define USB_D_INEPTXFSPCAVAIL2_V 0x0000FFFF 10326 #define USB_D_INEPTXFSPCAVAIL2_S 0 10327 10328 10329 /** USB_DIEPDMAB2_REG register 10330 * Device IN Endpoint 16 Buffer Address Register 10331 */ 10332 #define USB_DIEPDMAB2_REG (SOC_DPORT_USB_BASE + 0x95c) 10333 /** USB_D_DMABUFFERADDR2 : RO; bitpos: [32:0]; default: 0; 10334 * Holds the current buffer address.This register is updated as and when the data 10335 * transfer for the corresponding end point is in progress. This register is present 10336 * only in Scatter/Gather DMA mode. Otherwise this field is reserved. 10337 */ 10338 #define USB_D_DMABUFFERADDR2 0xFFFFFFFF 10339 #define USB_D_DMABUFFERADDR2_M (USB_D_DMABUFFERADDR2_V << USB_D_DMABUFFERADDR2_S) 10340 #define USB_D_DMABUFFERADDR2_V 0xFFFFFFFF 10341 #define USB_D_DMABUFFERADDR2_S 0 10342 10343 10344 /** USB_DTXFSTS3_REG register 10345 * Device IN Endpoint Transmit FIFO Status Register 3 10346 */ 10347 #define USB_DTXFSTS3_REG (SOC_DPORT_USB_BASE + 0x978) 10348 /** USB_D_INEPTXFSPCAVAIL3 : RO; bitpos: [16:0]; default: 0; 10349 * Indicates the amount of free space available in the Endpoint TxFIFO. 10350 */ 10351 #define USB_D_INEPTXFSPCAVAIL3 0x0000FFFF 10352 #define USB_D_INEPTXFSPCAVAIL3_M (USB_D_INEPTXFSPCAVAIL3_V << USB_D_INEPTXFSPCAVAIL3_S) 10353 #define USB_D_INEPTXFSPCAVAIL3_V 0x0000FFFF 10354 #define USB_D_INEPTXFSPCAVAIL3_S 0 10355 10356 10357 /** USB_DIEPDMAB3_REG register 10358 * Device IN Endpoint 16 Buffer Address Register 10359 */ 10360 #define USB_DIEPDMAB3_REG (SOC_DPORT_USB_BASE + 0x97c) 10361 /** USB_D_DMABUFFERADDR3 : RO; bitpos: [32:0]; default: 0; 10362 * Holds the current buffer address.This register is updated as and when the data 10363 * transfer for the corresponding end point is in progress. This register is present 10364 * only in Scatter/Gather DMA mode. Otherwise this field is reserved. 10365 */ 10366 #define USB_D_DMABUFFERADDR3 0xFFFFFFFF 10367 #define USB_D_DMABUFFERADDR3_M (USB_D_DMABUFFERADDR3_V << USB_D_DMABUFFERADDR3_S) 10368 #define USB_D_DMABUFFERADDR3_V 0xFFFFFFFF 10369 #define USB_D_DMABUFFERADDR3_S 0 10370 10371 10372 /** USB_DTXFSTS4_REG register 10373 * Device IN Endpoint Transmit FIFO Status Register 4 10374 */ 10375 #define USB_DTXFSTS4_REG (SOC_DPORT_USB_BASE + 0x998) 10376 /** USB_D_INEPTXFSPCAVAIL4 : RO; bitpos: [16:0]; default: 0; 10377 * Indicates the amount of free space available in the Endpoint TxFIFO. 10378 */ 10379 #define USB_D_INEPTXFSPCAVAIL4 0x0000FFFF 10380 #define USB_D_INEPTXFSPCAVAIL4_M (USB_D_INEPTXFSPCAVAIL4_V << USB_D_INEPTXFSPCAVAIL4_S) 10381 #define USB_D_INEPTXFSPCAVAIL4_V 0x0000FFFF 10382 #define USB_D_INEPTXFSPCAVAIL4_S 0 10383 10384 10385 /** USB_DIEPDMAB4_REG register 10386 * Device IN Endpoint 16 Buffer Address Register 10387 */ 10388 #define USB_DIEPDMAB4_REG (SOC_DPORT_USB_BASE + 0x99c) 10389 /** USB_D_DMABUFFERADDR4 : RO; bitpos: [32:0]; default: 0; 10390 * Holds the current buffer address.This register is updated as and when the data 10391 * transfer for the corresponding end point is in progress. This register is present 10392 * only in Scatter/Gather DMA mode. Otherwise this field is reserved. 10393 */ 10394 #define USB_D_DMABUFFERADDR4 0xFFFFFFFF 10395 #define USB_D_DMABUFFERADDR4_M (USB_D_DMABUFFERADDR4_V << USB_D_DMABUFFERADDR4_S) 10396 #define USB_D_DMABUFFERADDR4_V 0xFFFFFFFF 10397 #define USB_D_DMABUFFERADDR4_S 0 10398 10399 10400 /** USB_DTXFSTS5_REG register 10401 * Device IN Endpoint Transmit FIFO Status Register 5 10402 */ 10403 #define USB_DTXFSTS5_REG (SOC_DPORT_USB_BASE + 0x9b8) 10404 /** USB_D_INEPTXFSPCAVAIL5 : RO; bitpos: [16:0]; default: 0; 10405 * Indicates the amount of free space available in the Endpoint TxFIFO. 10406 */ 10407 #define USB_D_INEPTXFSPCAVAIL5 0x0000FFFF 10408 #define USB_D_INEPTXFSPCAVAIL5_M (USB_D_INEPTXFSPCAVAIL5_V << USB_D_INEPTXFSPCAVAIL5_S) 10409 #define USB_D_INEPTXFSPCAVAIL5_V 0x0000FFFF 10410 #define USB_D_INEPTXFSPCAVAIL5_S 0 10411 10412 10413 /** USB_DIEPDMAB5_REG register 10414 * Device IN Endpoint 16 Buffer Address Register 10415 */ 10416 #define USB_DIEPDMAB5_REG (SOC_DPORT_USB_BASE + 0x9bc) 10417 /** USB_D_DMABUFFERADDR5 : RO; bitpos: [32:0]; default: 0; 10418 * Holds the current buffer address.This register is updated as and when the data 10419 * transfer for the corresponding end point is in progress. This register is present 10420 * only in Scatter/Gather DMA mode. Otherwise this field is reserved. 10421 */ 10422 #define USB_D_DMABUFFERADDR5 0xFFFFFFFF 10423 #define USB_D_DMABUFFERADDR5_M (USB_D_DMABUFFERADDR5_V << USB_D_DMABUFFERADDR5_S) 10424 #define USB_D_DMABUFFERADDR5_V 0xFFFFFFFF 10425 #define USB_D_DMABUFFERADDR5_S 0 10426 10427 10428 /** USB_DTXFSTS6_REG register 10429 * Device IN Endpoint Transmit FIFO Status Register 6 10430 */ 10431 #define USB_DTXFSTS6_REG (SOC_DPORT_USB_BASE + 0x9d8) 10432 /** USB_D_INEPTXFSPCAVAIL6 : RO; bitpos: [16:0]; default: 0; 10433 * Indicates the amount of free space available in the Endpoint TxFIFO. 10434 */ 10435 #define USB_D_INEPTXFSPCAVAIL6 0x0000FFFF 10436 #define USB_D_INEPTXFSPCAVAIL6_M (USB_D_INEPTXFSPCAVAIL6_V << USB_D_INEPTXFSPCAVAIL6_S) 10437 #define USB_D_INEPTXFSPCAVAIL6_V 0x0000FFFF 10438 #define USB_D_INEPTXFSPCAVAIL6_S 0 10439 10440 10441 /** USB_DIEPDMAB6_REG register 10442 * Device IN Endpoint 16 Buffer Address Register 10443 */ 10444 #define USB_DIEPDMAB6_REG (SOC_DPORT_USB_BASE + 0x9dc) 10445 /** USB_D_DMABUFFERADDR6 : RO; bitpos: [32:0]; default: 0; 10446 * Holds the current buffer address.This register is updated as and when the data 10447 * transfer for the corresponding end point is in progress. This register is present 10448 * only in Scatter/Gather DMA mode. Otherwise this field is reserved. 10449 */ 10450 #define USB_D_DMABUFFERADDR6 0xFFFFFFFF 10451 #define USB_D_DMABUFFERADDR6_M (USB_D_DMABUFFERADDR6_V << USB_D_DMABUFFERADDR6_S) 10452 #define USB_D_DMABUFFERADDR6_V 0xFFFFFFFF 10453 #define USB_D_DMABUFFERADDR6_S 0 10454 10455 10456 10457 10458 #ifdef __cplusplus 10459 } 10460 #endif 10461
