1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /** RMT_CH0DATA_REG register 16 * Read and write data for channel 0 via APB FIFO 17 */ 18 #define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0) 19 /** RMT_CH0_DATA : RO; bitpos: [31:0]; default: 0; 20 * This register is used to read and write data for channel 0 via APB FIFO. 21 */ 22 #define RMT_CH0_DATA 0xFFFFFFFFU 23 #define RMT_CH0_DATA_M (RMT_CH0_DATA_V << RMT_CH0_DATA_S) 24 #define RMT_CH0_DATA_V 0xFFFFFFFFU 25 #define RMT_CH0_DATA_S 0 26 27 /** RMT_CH1DATA_REG register 28 * Read and write data for channel 1 via APB FIFO 29 */ 30 #define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x4) 31 /** RMT_CH0_DATA : RO; bitpos: [31:0]; default: 0; 32 * This register is used to read and write data for channel 1 via APB FIFO. 33 */ 34 #define RMT_CH0_DATA 0xFFFFFFFFU 35 #define RMT_CH0_DATA_M (RMT_CH0_DATA_V << RMT_CH0_DATA_S) 36 #define RMT_CH0_DATA_V 0xFFFFFFFFU 37 #define RMT_CH0_DATA_S 0 38 39 /** RMT_CH2DATA_REG register 40 * Read and write data for channel 2 via APB FIFO 41 */ 42 #define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x8) 43 /** RMT_CH0_DATA : RO; bitpos: [31:0]; default: 0; 44 * This register is used to read and write data for channel 2 via APB FIFO. 45 */ 46 #define RMT_CH0_DATA 0xFFFFFFFFU 47 #define RMT_CH0_DATA_M (RMT_CH0_DATA_V << RMT_CH0_DATA_S) 48 #define RMT_CH0_DATA_V 0xFFFFFFFFU 49 #define RMT_CH0_DATA_S 0 50 51 /** RMT_CH3DATA_REG register 52 * Read and write data for channel 3 via APB FIFO 53 */ 54 #define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0xc) 55 /** RMT_CH0_DATA : RO; bitpos: [31:0]; default: 0; 56 * This register is used to read and write data for channel 3 via APB FIFO. 57 */ 58 #define RMT_CH0_DATA 0xFFFFFFFFU 59 #define RMT_CH0_DATA_M (RMT_CH0_DATA_V << RMT_CH0_DATA_S) 60 #define RMT_CH0_DATA_V 0xFFFFFFFFU 61 #define RMT_CH0_DATA_S 0 62 63 /** RMT_CH0CONF0_REG register 64 * Channel 0 configuration register 0 65 */ 66 #define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x10) 67 /** RMT_DIV_CNT_CH0 : R/W; bitpos: [7:0]; default: 2; 68 * This field is used to configure clock divider for channel 0. 69 */ 70 #define RMT_DIV_CNT_CH0 0x000000FFU 71 #define RMT_DIV_CNT_CH0_M (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S) 72 #define RMT_DIV_CNT_CH0_V 0x000000FFU 73 #define RMT_DIV_CNT_CH0_S 0 74 /** RMT_IDLE_THRES_CH0 : R/W; bitpos: [23:8]; default: 4096; 75 * Receiving ends when no edge is detected on input signals for continuous clock 76 * cycles longer than this field value. 77 */ 78 #define RMT_IDLE_THRES_CH0 0x0000FFFFU 79 #define RMT_IDLE_THRES_CH0_M (RMT_IDLE_THRES_CH0_V << RMT_IDLE_THRES_CH0_S) 80 #define RMT_IDLE_THRES_CH0_V 0x0000FFFFU 81 #define RMT_IDLE_THRES_CH0_S 8 82 /** RMT_MEM_SIZE_CH0 : R/W; bitpos: [26:24]; default: 1; 83 * This field is used to configure the maximum blocks allocated to channel 0. The 84 * valid range is from 1 ~ 4-0. 85 */ 86 #define RMT_MEM_SIZE_CH0 0x00000007U 87 #define RMT_MEM_SIZE_CH0_M (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S) 88 #define RMT_MEM_SIZE_CH0_V 0x00000007U 89 #define RMT_MEM_SIZE_CH0_S 24 90 /** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [27]; default: 1; 91 * 1: Add carrier modulation on output signals only at data sending state for channel 92 * 0. 0: Add carrier modulation on signals at all states for channel 0. States here 93 * include idle state (ST_IDLE), reading data from RAM (ST_RD_MEM), and sending data 94 * stored in RAM (ST_SEND). Only valid when RMT_CARRIER_EN_CH0 is set to 1. 95 */ 96 #define RMT_CARRIER_EFF_EN_CH0 (BIT(27)) 97 #define RMT_CARRIER_EFF_EN_CH0_M (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S) 98 #define RMT_CARRIER_EFF_EN_CH0_V 0x00000001U 99 #define RMT_CARRIER_EFF_EN_CH0_S 27 100 /** RMT_CARRIER_EN_CH0 : R/W; bitpos: [28]; default: 1; 101 * This bit is used to enable carrier modulation for channel 0. 1: Add carrier 102 * modulation on output signals. 0: No carrier modulation is added on output signals. 103 */ 104 #define RMT_CARRIER_EN_CH0 (BIT(28)) 105 #define RMT_CARRIER_EN_CH0_M (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S) 106 #define RMT_CARRIER_EN_CH0_V 0x00000001U 107 #define RMT_CARRIER_EN_CH0_S 28 108 /** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [29]; default: 1; 109 * This bit is used to configure the position of carrier wave for channel 0. 110 * 111 * 1'h0: Add carrier wave on low-level output signals. 112 * 113 * 1'h1: Add carrier wave on high-level output signals. 114 */ 115 #define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) 116 #define RMT_CARRIER_OUT_LV_CH0_M (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S) 117 #define RMT_CARRIER_OUT_LV_CH0_V 0x00000001U 118 #define RMT_CARRIER_OUT_LV_CH0_S 29 119 120 /** RMT_CH0CONF1_REG register 121 * Channel 0 configuration register 1 122 */ 123 #define RMT_CH0CONF1_REG (DR_REG_RMT_BASE + 0x14) 124 /** RMT_TX_START_CH0 : R/W; bitpos: [0]; default: 0; 125 * Set this bit to start sending data on channel 0. 126 */ 127 #define RMT_TX_START_CH0 (BIT(0)) 128 #define RMT_TX_START_CH0_M (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S) 129 #define RMT_TX_START_CH0_V 0x00000001U 130 #define RMT_TX_START_CH0_S 0 131 /** RMT_RX_EN_CH0 : R/W; bitpos: [1]; default: 0; 132 * Set this bit to enable receiver to receive data on channel 0. 133 */ 134 #define RMT_RX_EN_CH0 (BIT(1)) 135 #define RMT_RX_EN_CH0_M (RMT_RX_EN_CH0_V << RMT_RX_EN_CH0_S) 136 #define RMT_RX_EN_CH0_V 0x00000001U 137 #define RMT_RX_EN_CH0_S 1 138 /** RMT_MEM_WR_RST_CH0 : WO; bitpos: [2]; default: 0; 139 * Set this bit to reset RAM write address accessed by the receiver for channel 0. 140 */ 141 #define RMT_MEM_WR_RST_CH0 (BIT(2)) 142 #define RMT_MEM_WR_RST_CH0_M (RMT_MEM_WR_RST_CH0_V << RMT_MEM_WR_RST_CH0_S) 143 #define RMT_MEM_WR_RST_CH0_V 0x00000001U 144 #define RMT_MEM_WR_RST_CH0_S 2 145 /** RMT_MEM_RD_RST_CH0 : WO; bitpos: [3]; default: 0; 146 * Set this bit to reset RAM read address accessed by the transmitter for channel 0. 147 */ 148 #define RMT_MEM_RD_RST_CH0 (BIT(3)) 149 #define RMT_MEM_RD_RST_CH0_M (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S) 150 #define RMT_MEM_RD_RST_CH0_V 0x00000001U 151 #define RMT_MEM_RD_RST_CH0_S 3 152 /** RMT_APB_MEM_RST_CH0 : WO; bitpos: [4]; default: 0; 153 * Set this bit to reset W/R ram address for channel 0 by accessing apb fifo. 154 */ 155 #define RMT_APB_MEM_RST_CH0 (BIT(4)) 156 #define RMT_APB_MEM_RST_CH0_M (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S) 157 #define RMT_APB_MEM_RST_CH0_V 0x00000001U 158 #define RMT_APB_MEM_RST_CH0_S 4 159 /** RMT_MEM_OWNER_CH0 : R/W; bitpos: [5]; default: 1; 160 * This bit marks the ownership of channel 0's RAM block. 161 * 162 * 1'h1: Receiver is using the RAM. 163 * 164 * 1'h0: Transmitter is using the RAM. 165 */ 166 #define RMT_MEM_OWNER_CH0 (BIT(5)) 167 #define RMT_MEM_OWNER_CH0_M (RMT_MEM_OWNER_CH0_V << RMT_MEM_OWNER_CH0_S) 168 #define RMT_MEM_OWNER_CH0_V 0x00000001U 169 #define RMT_MEM_OWNER_CH0_S 5 170 /** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [6]; default: 0; 171 * Set this bit to restart transmission in continuous node from the first data in 172 * channel 0. 173 */ 174 #define RMT_TX_CONTI_MODE_CH0 (BIT(6)) 175 #define RMT_TX_CONTI_MODE_CH0_M (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S) 176 #define RMT_TX_CONTI_MODE_CH0_V 0x00000001U 177 #define RMT_TX_CONTI_MODE_CH0_S 6 178 /** RMT_RX_FILTER_EN_CH0 : R/W; bitpos: [7]; default: 0; 179 * Set this bit to enable the receiver's filter for channel 0. 180 */ 181 #define RMT_RX_FILTER_EN_CH0 (BIT(7)) 182 #define RMT_RX_FILTER_EN_CH0_M (RMT_RX_FILTER_EN_CH0_V << RMT_RX_FILTER_EN_CH0_S) 183 #define RMT_RX_FILTER_EN_CH0_V 0x00000001U 184 #define RMT_RX_FILTER_EN_CH0_S 7 185 /** RMT_RX_FILTER_THRES_CH0 : R/W; bitpos: [15:8]; default: 15; 186 * Set this field to ignore the input pulse when its width is less than 187 * RMT_RX_FILTER_THRES_CH0 APB clock cycles in receive mode. 188 */ 189 #define RMT_RX_FILTER_THRES_CH0 0x000000FFU 190 #define RMT_RX_FILTER_THRES_CH0_M (RMT_RX_FILTER_THRES_CH0_V << RMT_RX_FILTER_THRES_CH0_S) 191 #define RMT_RX_FILTER_THRES_CH0_V 0x000000FFU 192 #define RMT_RX_FILTER_THRES_CH0_S 8 193 /** RMT_CHK_RX_CARRIER_EN_CH0 : R/W; bitpos: [16]; default: 0; 194 * Set this bit to enable memory loop read mode when carrier modulation is enabled for 195 * channel 0. 196 */ 197 #define RMT_CHK_RX_CARRIER_EN_CH0 (BIT(16)) 198 #define RMT_CHK_RX_CARRIER_EN_CH0_M (RMT_CHK_RX_CARRIER_EN_CH0_V << RMT_CHK_RX_CARRIER_EN_CH0_S) 199 #define RMT_CHK_RX_CARRIER_EN_CH0_V 0x00000001U 200 #define RMT_CHK_RX_CARRIER_EN_CH0_S 16 201 /** RMT_REF_ALWAYS_ON_CH0 : R/W; bitpos: [17]; default: 0; 202 * Set this bit to select a base clock for channel 0. 203 * 204 * 1'h1: APB_CLK 1'h0: REF_TICK 205 */ 206 #define RMT_REF_ALWAYS_ON_CH0 (BIT(17)) 207 #define RMT_REF_ALWAYS_ON_CH0_M (RMT_REF_ALWAYS_ON_CH0_V << RMT_REF_ALWAYS_ON_CH0_S) 208 #define RMT_REF_ALWAYS_ON_CH0_V 0x00000001U 209 #define RMT_REF_ALWAYS_ON_CH0_S 17 210 /** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [18]; default: 0; 211 * This bit configures the level of output signals in channel 0 when the transmitter 212 * is in idle state. 213 */ 214 #define RMT_IDLE_OUT_LV_CH0 (BIT(18)) 215 #define RMT_IDLE_OUT_LV_CH0_M (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S) 216 #define RMT_IDLE_OUT_LV_CH0_V 0x00000001U 217 #define RMT_IDLE_OUT_LV_CH0_S 18 218 /** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [19]; default: 0; 219 * This is the output enable bit for channel 0 in idle state. 220 */ 221 #define RMT_IDLE_OUT_EN_CH0 (BIT(19)) 222 #define RMT_IDLE_OUT_EN_CH0_M (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S) 223 #define RMT_IDLE_OUT_EN_CH0_V 0x00000001U 224 #define RMT_IDLE_OUT_EN_CH0_S 19 225 /** RMT_TX_STOP_CH0 : R/W; bitpos: [20]; default: 0; 226 * Set this bit to stop the transmitter of channel 0 sending data out. 227 */ 228 #define RMT_TX_STOP_CH0 (BIT(20)) 229 #define RMT_TX_STOP_CH0_M (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S) 230 #define RMT_TX_STOP_CH0_V 0x00000001U 231 #define RMT_TX_STOP_CH0_S 20 232 233 /** RMT_CH1CONF0_REG register 234 * Channel 1 configuration register 0 235 */ 236 #define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x18) 237 /** RMT_DIV_CNT_CH0 : R/W; bitpos: [7:0]; default: 2; 238 * This field is used to configure clock divider for channel 1. 239 */ 240 #define RMT_DIV_CNT_CH0 0x000000FFU 241 #define RMT_DIV_CNT_CH0_M (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S) 242 #define RMT_DIV_CNT_CH0_V 0x000000FFU 243 #define RMT_DIV_CNT_CH0_S 0 244 /** RMT_IDLE_THRES_CH0 : R/W; bitpos: [23:8]; default: 4096; 245 * Receiving ends when no edge is detected on input signals for continuous clock 246 * cycles longer than this field value. 247 */ 248 #define RMT_IDLE_THRES_CH0 0x0000FFFFU 249 #define RMT_IDLE_THRES_CH0_M (RMT_IDLE_THRES_CH0_V << RMT_IDLE_THRES_CH0_S) 250 #define RMT_IDLE_THRES_CH0_V 0x0000FFFFU 251 #define RMT_IDLE_THRES_CH0_S 8 252 /** RMT_MEM_SIZE_CH0 : R/W; bitpos: [26:24]; default: 1; 253 * This field is used to configure the maximum blocks allocated to channel 1. The 254 * valid range is from 1 ~ 4-1. 255 */ 256 #define RMT_MEM_SIZE_CH0 0x00000007U 257 #define RMT_MEM_SIZE_CH0_M (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S) 258 #define RMT_MEM_SIZE_CH0_V 0x00000007U 259 #define RMT_MEM_SIZE_CH0_S 24 260 /** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [27]; default: 1; 261 * 1: Add carrier modulation on output signals only at data sending state for channel 262 * 1. 0: Add carrier modulation on signals at all states for channel 1. States here 263 * include idle state (ST_IDLE), reading data from RAM (ST_RD_MEM), and sending data 264 * stored in RAM (ST_SEND). Only valid when RMT_CARRIER_EN_CH1 is set to 1. 265 */ 266 #define RMT_CARRIER_EFF_EN_CH0 (BIT(27)) 267 #define RMT_CARRIER_EFF_EN_CH0_M (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S) 268 #define RMT_CARRIER_EFF_EN_CH0_V 0x00000001U 269 #define RMT_CARRIER_EFF_EN_CH0_S 27 270 /** RMT_CARRIER_EN_CH0 : R/W; bitpos: [28]; default: 1; 271 * This bit is used to enable carrier modulation for channel 1. 1: Add carrier 272 * modulation on output signals. 0: No carrier modulation is added on output signals. 273 */ 274 #define RMT_CARRIER_EN_CH0 (BIT(28)) 275 #define RMT_CARRIER_EN_CH0_M (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S) 276 #define RMT_CARRIER_EN_CH0_V 0x00000001U 277 #define RMT_CARRIER_EN_CH0_S 28 278 /** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [29]; default: 1; 279 * This bit is used to configure the position of carrier wave for channel 1. 280 * 281 * 1'h0: Add carrier wave on low-level output signals. 282 * 283 * 1'h1: Add carrier wave on high-level output signals. 284 */ 285 #define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) 286 #define RMT_CARRIER_OUT_LV_CH0_M (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S) 287 #define RMT_CARRIER_OUT_LV_CH0_V 0x00000001U 288 #define RMT_CARRIER_OUT_LV_CH0_S 29 289 290 /** RMT_CH1CONF1_REG register 291 * Channel 1 configuration register 1 292 */ 293 #define RMT_CH1CONF1_REG (DR_REG_RMT_BASE + 0x1c) 294 /** RMT_TX_START_CH0 : R/W; bitpos: [0]; default: 0; 295 * Set this bit to start sending data on channel 1. 296 */ 297 #define RMT_TX_START_CH0 (BIT(0)) 298 #define RMT_TX_START_CH0_M (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S) 299 #define RMT_TX_START_CH0_V 0x00000001U 300 #define RMT_TX_START_CH0_S 0 301 /** RMT_RX_EN_CH0 : R/W; bitpos: [1]; default: 0; 302 * Set this bit to enable receiver to receive data on channel 1. 303 */ 304 #define RMT_RX_EN_CH0 (BIT(1)) 305 #define RMT_RX_EN_CH0_M (RMT_RX_EN_CH0_V << RMT_RX_EN_CH0_S) 306 #define RMT_RX_EN_CH0_V 0x00000001U 307 #define RMT_RX_EN_CH0_S 1 308 /** RMT_MEM_WR_RST_CH0 : WO; bitpos: [2]; default: 0; 309 * Set this bit to reset RAM write address accessed by the receiver for channel 1. 310 */ 311 #define RMT_MEM_WR_RST_CH0 (BIT(2)) 312 #define RMT_MEM_WR_RST_CH0_M (RMT_MEM_WR_RST_CH0_V << RMT_MEM_WR_RST_CH0_S) 313 #define RMT_MEM_WR_RST_CH0_V 0x00000001U 314 #define RMT_MEM_WR_RST_CH0_S 2 315 /** RMT_MEM_RD_RST_CH0 : WO; bitpos: [3]; default: 0; 316 * Set this bit to reset RAM read address accessed by the transmitter for channel 1. 317 */ 318 #define RMT_MEM_RD_RST_CH0 (BIT(3)) 319 #define RMT_MEM_RD_RST_CH0_M (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S) 320 #define RMT_MEM_RD_RST_CH0_V 0x00000001U 321 #define RMT_MEM_RD_RST_CH0_S 3 322 /** RMT_APB_MEM_RST_CH0 : WO; bitpos: [4]; default: 0; 323 * Set this bit to reset W/R ram address for channel 1 by accessing apb fifo. 324 */ 325 #define RMT_APB_MEM_RST_CH0 (BIT(4)) 326 #define RMT_APB_MEM_RST_CH0_M (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S) 327 #define RMT_APB_MEM_RST_CH0_V 0x00000001U 328 #define RMT_APB_MEM_RST_CH0_S 4 329 /** RMT_MEM_OWNER_CH0 : R/W; bitpos: [5]; default: 1; 330 * This bit marks the ownership of channel 1's RAM block. 331 * 332 * 1'h1: Receiver is using the RAM. 333 * 334 * 1'h0: Transmitter is using the RAM. 335 */ 336 #define RMT_MEM_OWNER_CH0 (BIT(5)) 337 #define RMT_MEM_OWNER_CH0_M (RMT_MEM_OWNER_CH0_V << RMT_MEM_OWNER_CH0_S) 338 #define RMT_MEM_OWNER_CH0_V 0x00000001U 339 #define RMT_MEM_OWNER_CH0_S 5 340 /** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [6]; default: 0; 341 * Set this bit to restart transmission in continuous node from the first data in 342 * channel 1. 343 */ 344 #define RMT_TX_CONTI_MODE_CH0 (BIT(6)) 345 #define RMT_TX_CONTI_MODE_CH0_M (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S) 346 #define RMT_TX_CONTI_MODE_CH0_V 0x00000001U 347 #define RMT_TX_CONTI_MODE_CH0_S 6 348 /** RMT_RX_FILTER_EN_CH0 : R/W; bitpos: [7]; default: 0; 349 * Set this bit to enable the receiver's filter for channel 1. 350 */ 351 #define RMT_RX_FILTER_EN_CH0 (BIT(7)) 352 #define RMT_RX_FILTER_EN_CH0_M (RMT_RX_FILTER_EN_CH0_V << RMT_RX_FILTER_EN_CH0_S) 353 #define RMT_RX_FILTER_EN_CH0_V 0x00000001U 354 #define RMT_RX_FILTER_EN_CH0_S 7 355 /** RMT_RX_FILTER_THRES_CH0 : R/W; bitpos: [15:8]; default: 15; 356 * Set this field to ignore the input pulse when its width is less than 357 * RMT_RX_FILTER_THRES_CH1 APB clock cycles in receive mode. 358 */ 359 #define RMT_RX_FILTER_THRES_CH0 0x000000FFU 360 #define RMT_RX_FILTER_THRES_CH0_M (RMT_RX_FILTER_THRES_CH0_V << RMT_RX_FILTER_THRES_CH0_S) 361 #define RMT_RX_FILTER_THRES_CH0_V 0x000000FFU 362 #define RMT_RX_FILTER_THRES_CH0_S 8 363 /** RMT_CHK_RX_CARRIER_EN_CH0 : R/W; bitpos: [16]; default: 0; 364 * Set this bit to enable memory loop read mode when carrier modulation is enabled for 365 * channel 1. 366 */ 367 #define RMT_CHK_RX_CARRIER_EN_CH0 (BIT(16)) 368 #define RMT_CHK_RX_CARRIER_EN_CH0_M (RMT_CHK_RX_CARRIER_EN_CH0_V << RMT_CHK_RX_CARRIER_EN_CH0_S) 369 #define RMT_CHK_RX_CARRIER_EN_CH0_V 0x00000001U 370 #define RMT_CHK_RX_CARRIER_EN_CH0_S 16 371 /** RMT_REF_ALWAYS_ON_CH0 : R/W; bitpos: [17]; default: 0; 372 * Set this bit to select a base clock for channel 1. 373 * 374 * 1'h1: APB_CLK 1'h0: REF_TICK 375 */ 376 #define RMT_REF_ALWAYS_ON_CH0 (BIT(17)) 377 #define RMT_REF_ALWAYS_ON_CH0_M (RMT_REF_ALWAYS_ON_CH0_V << RMT_REF_ALWAYS_ON_CH0_S) 378 #define RMT_REF_ALWAYS_ON_CH0_V 0x00000001U 379 #define RMT_REF_ALWAYS_ON_CH0_S 17 380 /** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [18]; default: 0; 381 * This bit configures the level of output signals in channel 1 when the transmitter 382 * is in idle state. 383 */ 384 #define RMT_IDLE_OUT_LV_CH0 (BIT(18)) 385 #define RMT_IDLE_OUT_LV_CH0_M (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S) 386 #define RMT_IDLE_OUT_LV_CH0_V 0x00000001U 387 #define RMT_IDLE_OUT_LV_CH0_S 18 388 /** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [19]; default: 0; 389 * This is the output enable bit for channel 1 in idle state. 390 */ 391 #define RMT_IDLE_OUT_EN_CH0 (BIT(19)) 392 #define RMT_IDLE_OUT_EN_CH0_M (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S) 393 #define RMT_IDLE_OUT_EN_CH0_V 0x00000001U 394 #define RMT_IDLE_OUT_EN_CH0_S 19 395 /** RMT_TX_STOP_CH0 : R/W; bitpos: [20]; default: 0; 396 * Set this bit to stop the transmitter of channel 1 sending data out. 397 */ 398 #define RMT_TX_STOP_CH0 (BIT(20)) 399 #define RMT_TX_STOP_CH0_M (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S) 400 #define RMT_TX_STOP_CH0_V 0x00000001U 401 #define RMT_TX_STOP_CH0_S 20 402 403 /** RMT_CH2CONF0_REG register 404 * Channel 2 configuration register 0 405 */ 406 #define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x20) 407 /** RMT_DIV_CNT_CH0 : R/W; bitpos: [7:0]; default: 2; 408 * This field is used to configure clock divider for channel 2. 409 */ 410 #define RMT_DIV_CNT_CH0 0x000000FFU 411 #define RMT_DIV_CNT_CH0_M (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S) 412 #define RMT_DIV_CNT_CH0_V 0x000000FFU 413 #define RMT_DIV_CNT_CH0_S 0 414 /** RMT_IDLE_THRES_CH0 : R/W; bitpos: [23:8]; default: 4096; 415 * Receiving ends when no edge is detected on input signals for continuous clock 416 * cycles longer than this field value. 417 */ 418 #define RMT_IDLE_THRES_CH0 0x0000FFFFU 419 #define RMT_IDLE_THRES_CH0_M (RMT_IDLE_THRES_CH0_V << RMT_IDLE_THRES_CH0_S) 420 #define RMT_IDLE_THRES_CH0_V 0x0000FFFFU 421 #define RMT_IDLE_THRES_CH0_S 8 422 /** RMT_MEM_SIZE_CH0 : R/W; bitpos: [26:24]; default: 1; 423 * This field is used to configure the maximum blocks allocated to channel 2. The 424 * valid range is from 1 ~ 4-2. 425 */ 426 #define RMT_MEM_SIZE_CH0 0x00000007U 427 #define RMT_MEM_SIZE_CH0_M (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S) 428 #define RMT_MEM_SIZE_CH0_V 0x00000007U 429 #define RMT_MEM_SIZE_CH0_S 24 430 /** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [27]; default: 1; 431 * 1: Add carrier modulation on output signals only at data sending state for channel 432 * 2. 0: Add carrier modulation on signals at all states for channel 2. States here 433 * include idle state (ST_IDLE), reading data from RAM (ST_RD_MEM), and sending data 434 * stored in RAM (ST_SEND). Only valid when RMT_CARRIER_EN_CH2 is set to 1. 435 */ 436 #define RMT_CARRIER_EFF_EN_CH0 (BIT(27)) 437 #define RMT_CARRIER_EFF_EN_CH0_M (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S) 438 #define RMT_CARRIER_EFF_EN_CH0_V 0x00000001U 439 #define RMT_CARRIER_EFF_EN_CH0_S 27 440 /** RMT_CARRIER_EN_CH0 : R/W; bitpos: [28]; default: 1; 441 * This bit is used to enable carrier modulation for channel 2. 1: Add carrier 442 * modulation on output signals. 0: No carrier modulation is added on output signals. 443 */ 444 #define RMT_CARRIER_EN_CH0 (BIT(28)) 445 #define RMT_CARRIER_EN_CH0_M (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S) 446 #define RMT_CARRIER_EN_CH0_V 0x00000001U 447 #define RMT_CARRIER_EN_CH0_S 28 448 /** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [29]; default: 1; 449 * This bit is used to configure the position of carrier wave for channel 2. 450 * 451 * 1'h0: Add carrier wave on low-level output signals. 452 * 453 * 1'h1: Add carrier wave on high-level output signals. 454 */ 455 #define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) 456 #define RMT_CARRIER_OUT_LV_CH0_M (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S) 457 #define RMT_CARRIER_OUT_LV_CH0_V 0x00000001U 458 #define RMT_CARRIER_OUT_LV_CH0_S 29 459 460 /** RMT_CH2CONF1_REG register 461 * Channel 2 configuration register 1 462 */ 463 #define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x24) 464 /** RMT_TX_START_CH0 : R/W; bitpos: [0]; default: 0; 465 * Set this bit to start sending data on channel 2. 466 */ 467 #define RMT_TX_START_CH0 (BIT(0)) 468 #define RMT_TX_START_CH0_M (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S) 469 #define RMT_TX_START_CH0_V 0x00000001U 470 #define RMT_TX_START_CH0_S 0 471 /** RMT_RX_EN_CH0 : R/W; bitpos: [1]; default: 0; 472 * Set this bit to enable receiver to receive data on channel 2. 473 */ 474 #define RMT_RX_EN_CH0 (BIT(1)) 475 #define RMT_RX_EN_CH0_M (RMT_RX_EN_CH0_V << RMT_RX_EN_CH0_S) 476 #define RMT_RX_EN_CH0_V 0x00000001U 477 #define RMT_RX_EN_CH0_S 1 478 /** RMT_MEM_WR_RST_CH0 : WO; bitpos: [2]; default: 0; 479 * Set this bit to reset RAM write address accessed by the receiver for channel 2. 480 */ 481 #define RMT_MEM_WR_RST_CH0 (BIT(2)) 482 #define RMT_MEM_WR_RST_CH0_M (RMT_MEM_WR_RST_CH0_V << RMT_MEM_WR_RST_CH0_S) 483 #define RMT_MEM_WR_RST_CH0_V 0x00000001U 484 #define RMT_MEM_WR_RST_CH0_S 2 485 /** RMT_MEM_RD_RST_CH0 : WO; bitpos: [3]; default: 0; 486 * Set this bit to reset RAM read address accessed by the transmitter for channel 2. 487 */ 488 #define RMT_MEM_RD_RST_CH0 (BIT(3)) 489 #define RMT_MEM_RD_RST_CH0_M (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S) 490 #define RMT_MEM_RD_RST_CH0_V 0x00000001U 491 #define RMT_MEM_RD_RST_CH0_S 3 492 /** RMT_APB_MEM_RST_CH0 : WO; bitpos: [4]; default: 0; 493 * Set this bit to reset W/R ram address for channel 2 by accessing apb fifo. 494 */ 495 #define RMT_APB_MEM_RST_CH0 (BIT(4)) 496 #define RMT_APB_MEM_RST_CH0_M (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S) 497 #define RMT_APB_MEM_RST_CH0_V 0x00000001U 498 #define RMT_APB_MEM_RST_CH0_S 4 499 /** RMT_MEM_OWNER_CH0 : R/W; bitpos: [5]; default: 1; 500 * This bit marks the ownership of channel 2's RAM block. 501 * 502 * 1'h1: Receiver is using the RAM. 503 * 504 * 1'h0: Transmitter is using the RAM. 505 */ 506 #define RMT_MEM_OWNER_CH0 (BIT(5)) 507 #define RMT_MEM_OWNER_CH0_M (RMT_MEM_OWNER_CH0_V << RMT_MEM_OWNER_CH0_S) 508 #define RMT_MEM_OWNER_CH0_V 0x00000001U 509 #define RMT_MEM_OWNER_CH0_S 5 510 /** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [6]; default: 0; 511 * Set this bit to restart transmission in continuous node from the first data in 512 * channel 2. 513 */ 514 #define RMT_TX_CONTI_MODE_CH0 (BIT(6)) 515 #define RMT_TX_CONTI_MODE_CH0_M (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S) 516 #define RMT_TX_CONTI_MODE_CH0_V 0x00000001U 517 #define RMT_TX_CONTI_MODE_CH0_S 6 518 /** RMT_RX_FILTER_EN_CH0 : R/W; bitpos: [7]; default: 0; 519 * Set this bit to enable the receiver's filter for channel 2. 520 */ 521 #define RMT_RX_FILTER_EN_CH0 (BIT(7)) 522 #define RMT_RX_FILTER_EN_CH0_M (RMT_RX_FILTER_EN_CH0_V << RMT_RX_FILTER_EN_CH0_S) 523 #define RMT_RX_FILTER_EN_CH0_V 0x00000001U 524 #define RMT_RX_FILTER_EN_CH0_S 7 525 /** RMT_RX_FILTER_THRES_CH0 : R/W; bitpos: [15:8]; default: 15; 526 * Set this field to ignore the input pulse when its width is less than 527 * RMT_RX_FILTER_THRES_CH2 APB clock cycles in receive mode. 528 */ 529 #define RMT_RX_FILTER_THRES_CH0 0x000000FFU 530 #define RMT_RX_FILTER_THRES_CH0_M (RMT_RX_FILTER_THRES_CH0_V << RMT_RX_FILTER_THRES_CH0_S) 531 #define RMT_RX_FILTER_THRES_CH0_V 0x000000FFU 532 #define RMT_RX_FILTER_THRES_CH0_S 8 533 /** RMT_CHK_RX_CARRIER_EN_CH0 : R/W; bitpos: [16]; default: 0; 534 * Set this bit to enable memory loop read mode when carrier modulation is enabled for 535 * channel 2. 536 */ 537 #define RMT_CHK_RX_CARRIER_EN_CH0 (BIT(16)) 538 #define RMT_CHK_RX_CARRIER_EN_CH0_M (RMT_CHK_RX_CARRIER_EN_CH0_V << RMT_CHK_RX_CARRIER_EN_CH0_S) 539 #define RMT_CHK_RX_CARRIER_EN_CH0_V 0x00000001U 540 #define RMT_CHK_RX_CARRIER_EN_CH0_S 16 541 /** RMT_REF_ALWAYS_ON_CH0 : R/W; bitpos: [17]; default: 0; 542 * Set this bit to select a base clock for channel 2. 543 * 544 * 1'h1: APB_CLK 1'h0: REF_TICK 545 */ 546 #define RMT_REF_ALWAYS_ON_CH0 (BIT(17)) 547 #define RMT_REF_ALWAYS_ON_CH0_M (RMT_REF_ALWAYS_ON_CH0_V << RMT_REF_ALWAYS_ON_CH0_S) 548 #define RMT_REF_ALWAYS_ON_CH0_V 0x00000001U 549 #define RMT_REF_ALWAYS_ON_CH0_S 17 550 /** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [18]; default: 0; 551 * This bit configures the level of output signals in channel 2 when the transmitter 552 * is in idle state. 553 */ 554 #define RMT_IDLE_OUT_LV_CH0 (BIT(18)) 555 #define RMT_IDLE_OUT_LV_CH0_M (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S) 556 #define RMT_IDLE_OUT_LV_CH0_V 0x00000001U 557 #define RMT_IDLE_OUT_LV_CH0_S 18 558 /** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [19]; default: 0; 559 * This is the output enable bit for channel 2 in idle state. 560 */ 561 #define RMT_IDLE_OUT_EN_CH0 (BIT(19)) 562 #define RMT_IDLE_OUT_EN_CH0_M (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S) 563 #define RMT_IDLE_OUT_EN_CH0_V 0x00000001U 564 #define RMT_IDLE_OUT_EN_CH0_S 19 565 /** RMT_TX_STOP_CH0 : R/W; bitpos: [20]; default: 0; 566 * Set this bit to stop the transmitter of channel 2 sending data out. 567 */ 568 #define RMT_TX_STOP_CH0 (BIT(20)) 569 #define RMT_TX_STOP_CH0_M (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S) 570 #define RMT_TX_STOP_CH0_V 0x00000001U 571 #define RMT_TX_STOP_CH0_S 20 572 573 /** RMT_CH3CONF0_REG register 574 * Channel 3 configuration register 0 575 */ 576 #define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x28) 577 /** RMT_DIV_CNT_CH0 : R/W; bitpos: [7:0]; default: 2; 578 * This field is used to configure clock divider for channel 3. 579 */ 580 #define RMT_DIV_CNT_CH0 0x000000FFU 581 #define RMT_DIV_CNT_CH0_M (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S) 582 #define RMT_DIV_CNT_CH0_V 0x000000FFU 583 #define RMT_DIV_CNT_CH0_S 0 584 /** RMT_IDLE_THRES_CH0 : R/W; bitpos: [23:8]; default: 4096; 585 * Receiving ends when no edge is detected on input signals for continuous clock 586 * cycles longer than this field value. 587 */ 588 #define RMT_IDLE_THRES_CH0 0x0000FFFFU 589 #define RMT_IDLE_THRES_CH0_M (RMT_IDLE_THRES_CH0_V << RMT_IDLE_THRES_CH0_S) 590 #define RMT_IDLE_THRES_CH0_V 0x0000FFFFU 591 #define RMT_IDLE_THRES_CH0_S 8 592 /** RMT_MEM_SIZE_CH0 : R/W; bitpos: [26:24]; default: 1; 593 * This field is used to configure the maximum blocks allocated to channel 3. The 594 * valid range is from 1 ~ 4-3. 595 */ 596 #define RMT_MEM_SIZE_CH0 0x00000007U 597 #define RMT_MEM_SIZE_CH0_M (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S) 598 #define RMT_MEM_SIZE_CH0_V 0x00000007U 599 #define RMT_MEM_SIZE_CH0_S 24 600 /** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [27]; default: 1; 601 * 1: Add carrier modulation on output signals only at data sending state for channel 602 * 3. 0: Add carrier modulation on signals at all states for channel 3. States here 603 * include idle state (ST_IDLE), reading data from RAM (ST_RD_MEM), and sending data 604 * stored in RAM (ST_SEND). Only valid when RMT_CARRIER_EN_CH3 is set to 1. 605 */ 606 #define RMT_CARRIER_EFF_EN_CH0 (BIT(27)) 607 #define RMT_CARRIER_EFF_EN_CH0_M (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S) 608 #define RMT_CARRIER_EFF_EN_CH0_V 0x00000001U 609 #define RMT_CARRIER_EFF_EN_CH0_S 27 610 /** RMT_CARRIER_EN_CH0 : R/W; bitpos: [28]; default: 1; 611 * This bit is used to enable carrier modulation for channel 3. 1: Add carrier 612 * modulation on output signals. 0: No carrier modulation is added on output signals. 613 */ 614 #define RMT_CARRIER_EN_CH0 (BIT(28)) 615 #define RMT_CARRIER_EN_CH0_M (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S) 616 #define RMT_CARRIER_EN_CH0_V 0x00000001U 617 #define RMT_CARRIER_EN_CH0_S 28 618 /** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [29]; default: 1; 619 * This bit is used to configure the position of carrier wave for channel 3. 620 * 621 * 1'h0: Add carrier wave on low-level output signals. 622 * 623 * 1'h1: Add carrier wave on high-level output signals. 624 */ 625 #define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) 626 #define RMT_CARRIER_OUT_LV_CH0_M (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S) 627 #define RMT_CARRIER_OUT_LV_CH0_V 0x00000001U 628 #define RMT_CARRIER_OUT_LV_CH0_S 29 629 630 /** RMT_CH3CONF1_REG register 631 * Channel 3 configuration register 1 632 */ 633 #define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x2c) 634 /** RMT_TX_START_CH0 : R/W; bitpos: [0]; default: 0; 635 * Set this bit to start sending data on channel 3. 636 */ 637 #define RMT_TX_START_CH0 (BIT(0)) 638 #define RMT_TX_START_CH0_M (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S) 639 #define RMT_TX_START_CH0_V 0x00000001U 640 #define RMT_TX_START_CH0_S 0 641 /** RMT_RX_EN_CH0 : R/W; bitpos: [1]; default: 0; 642 * Set this bit to enable receiver to receive data on channel 3. 643 */ 644 #define RMT_RX_EN_CH0 (BIT(1)) 645 #define RMT_RX_EN_CH0_M (RMT_RX_EN_CH0_V << RMT_RX_EN_CH0_S) 646 #define RMT_RX_EN_CH0_V 0x00000001U 647 #define RMT_RX_EN_CH0_S 1 648 /** RMT_MEM_WR_RST_CH0 : WO; bitpos: [2]; default: 0; 649 * Set this bit to reset RAM write address accessed by the receiver for channel 3. 650 */ 651 #define RMT_MEM_WR_RST_CH0 (BIT(2)) 652 #define RMT_MEM_WR_RST_CH0_M (RMT_MEM_WR_RST_CH0_V << RMT_MEM_WR_RST_CH0_S) 653 #define RMT_MEM_WR_RST_CH0_V 0x00000001U 654 #define RMT_MEM_WR_RST_CH0_S 2 655 /** RMT_MEM_RD_RST_CH0 : WO; bitpos: [3]; default: 0; 656 * Set this bit to reset RAM read address accessed by the transmitter for channel 3. 657 */ 658 #define RMT_MEM_RD_RST_CH0 (BIT(3)) 659 #define RMT_MEM_RD_RST_CH0_M (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S) 660 #define RMT_MEM_RD_RST_CH0_V 0x00000001U 661 #define RMT_MEM_RD_RST_CH0_S 3 662 /** RMT_APB_MEM_RST_CH0 : WO; bitpos: [4]; default: 0; 663 * Set this bit to reset W/R ram address for channel 3 by accessing apb fifo. 664 */ 665 #define RMT_APB_MEM_RST_CH0 (BIT(4)) 666 #define RMT_APB_MEM_RST_CH0_M (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S) 667 #define RMT_APB_MEM_RST_CH0_V 0x00000001U 668 #define RMT_APB_MEM_RST_CH0_S 4 669 /** RMT_MEM_OWNER_CH0 : R/W; bitpos: [5]; default: 1; 670 * This bit marks the ownership of channel 3's RAM block. 671 * 672 * 1'h1: Receiver is using the RAM. 673 * 674 * 1'h0: Transmitter is using the RAM. 675 */ 676 #define RMT_MEM_OWNER_CH0 (BIT(5)) 677 #define RMT_MEM_OWNER_CH0_M (RMT_MEM_OWNER_CH0_V << RMT_MEM_OWNER_CH0_S) 678 #define RMT_MEM_OWNER_CH0_V 0x00000001U 679 #define RMT_MEM_OWNER_CH0_S 5 680 /** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [6]; default: 0; 681 * Set this bit to restart transmission in continuous node from the first data in 682 * channel 3. 683 */ 684 #define RMT_TX_CONTI_MODE_CH0 (BIT(6)) 685 #define RMT_TX_CONTI_MODE_CH0_M (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S) 686 #define RMT_TX_CONTI_MODE_CH0_V 0x00000001U 687 #define RMT_TX_CONTI_MODE_CH0_S 6 688 /** RMT_RX_FILTER_EN_CH0 : R/W; bitpos: [7]; default: 0; 689 * Set this bit to enable the receiver's filter for channel 3. 690 */ 691 #define RMT_RX_FILTER_EN_CH0 (BIT(7)) 692 #define RMT_RX_FILTER_EN_CH0_M (RMT_RX_FILTER_EN_CH0_V << RMT_RX_FILTER_EN_CH0_S) 693 #define RMT_RX_FILTER_EN_CH0_V 0x00000001U 694 #define RMT_RX_FILTER_EN_CH0_S 7 695 /** RMT_RX_FILTER_THRES_CH0 : R/W; bitpos: [15:8]; default: 15; 696 * Set this field to ignore the input pulse when its width is less than 697 * RMT_RX_FILTER_THRES_CH3 APB clock cycles in receive mode. 698 */ 699 #define RMT_RX_FILTER_THRES_CH0 0x000000FFU 700 #define RMT_RX_FILTER_THRES_CH0_M (RMT_RX_FILTER_THRES_CH0_V << RMT_RX_FILTER_THRES_CH0_S) 701 #define RMT_RX_FILTER_THRES_CH0_V 0x000000FFU 702 #define RMT_RX_FILTER_THRES_CH0_S 8 703 /** RMT_CHK_RX_CARRIER_EN_CH0 : R/W; bitpos: [16]; default: 0; 704 * Set this bit to enable memory loop read mode when carrier modulation is enabled for 705 * channel 3. 706 */ 707 #define RMT_CHK_RX_CARRIER_EN_CH0 (BIT(16)) 708 #define RMT_CHK_RX_CARRIER_EN_CH0_M (RMT_CHK_RX_CARRIER_EN_CH0_V << RMT_CHK_RX_CARRIER_EN_CH0_S) 709 #define RMT_CHK_RX_CARRIER_EN_CH0_V 0x00000001U 710 #define RMT_CHK_RX_CARRIER_EN_CH0_S 16 711 /** RMT_REF_ALWAYS_ON_CH0 : R/W; bitpos: [17]; default: 0; 712 * Set this bit to select a base clock for channel 3. 713 * 714 * 1'h1: APB_CLK 1'h0: REF_TICK 715 */ 716 #define RMT_REF_ALWAYS_ON_CH0 (BIT(17)) 717 #define RMT_REF_ALWAYS_ON_CH0_M (RMT_REF_ALWAYS_ON_CH0_V << RMT_REF_ALWAYS_ON_CH0_S) 718 #define RMT_REF_ALWAYS_ON_CH0_V 0x00000001U 719 #define RMT_REF_ALWAYS_ON_CH0_S 17 720 /** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [18]; default: 0; 721 * This bit configures the level of output signals in channel 3 when the transmitter 722 * is in idle state. 723 */ 724 #define RMT_IDLE_OUT_LV_CH0 (BIT(18)) 725 #define RMT_IDLE_OUT_LV_CH0_M (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S) 726 #define RMT_IDLE_OUT_LV_CH0_V 0x00000001U 727 #define RMT_IDLE_OUT_LV_CH0_S 18 728 /** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [19]; default: 0; 729 * This is the output enable bit for channel 3 in idle state. 730 */ 731 #define RMT_IDLE_OUT_EN_CH0 (BIT(19)) 732 #define RMT_IDLE_OUT_EN_CH0_M (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S) 733 #define RMT_IDLE_OUT_EN_CH0_V 0x00000001U 734 #define RMT_IDLE_OUT_EN_CH0_S 19 735 /** RMT_TX_STOP_CH0 : R/W; bitpos: [20]; default: 0; 736 * Set this bit to stop the transmitter of channel 3 sending data out. 737 */ 738 #define RMT_TX_STOP_CH0 (BIT(20)) 739 #define RMT_TX_STOP_CH0_M (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S) 740 #define RMT_TX_STOP_CH0_V 0x00000001U 741 #define RMT_TX_STOP_CH0_S 20 742 743 /** RMT_CH0STATUS_REG register 744 * Channel 0 status register 745 */ 746 #define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x30) 747 /** RMT_MEM_WADDR_EX_CH0 : RO; bitpos: [8:0]; default: 0; 748 * This field records the memory address offset when receiver of channel 0 is using 749 * the RAM. 750 */ 751 #define RMT_MEM_WADDR_EX_CH0 0x000001FFU 752 #define RMT_MEM_WADDR_EX_CH0_M (RMT_MEM_WADDR_EX_CH0_V << RMT_MEM_WADDR_EX_CH0_S) 753 #define RMT_MEM_WADDR_EX_CH0_V 0x000001FFU 754 #define RMT_MEM_WADDR_EX_CH0_S 0 755 /** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [18:10]; default: 0; 756 * This field records the memory address offset when transmitter of channel 0 is using 757 * the RAM. 758 */ 759 #define RMT_MEM_RADDR_EX_CH0 0x000001FFU 760 #define RMT_MEM_RADDR_EX_CH0_M (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S) 761 #define RMT_MEM_RADDR_EX_CH0_V 0x000001FFU 762 #define RMT_MEM_RADDR_EX_CH0_S 10 763 /** RMT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; 764 * This field records the FSM status of channel 0. 765 */ 766 #define RMT_STATE_CH0 0x00000007U 767 #define RMT_STATE_CH0_M (RMT_STATE_CH0_V << RMT_STATE_CH0_S) 768 #define RMT_STATE_CH0_V 0x00000007U 769 #define RMT_STATE_CH0_S 20 770 /** RMT_MEM_OWNER_ERR_CH0 : RO; bitpos: [23]; default: 0; 771 * This status bit will be set when the ownership of memory block is violated. 772 */ 773 #define RMT_MEM_OWNER_ERR_CH0 (BIT(23)) 774 #define RMT_MEM_OWNER_ERR_CH0_M (RMT_MEM_OWNER_ERR_CH0_V << RMT_MEM_OWNER_ERR_CH0_S) 775 #define RMT_MEM_OWNER_ERR_CH0_V 0x00000001U 776 #define RMT_MEM_OWNER_ERR_CH0_S 23 777 /** RMT_MEM_FULL_CH0 : RO; bitpos: [24]; default: 0; 778 * This status bit will be set if the receiver receives more data than the memory 779 * allows. 780 */ 781 #define RMT_MEM_FULL_CH0 (BIT(24)) 782 #define RMT_MEM_FULL_CH0_M (RMT_MEM_FULL_CH0_V << RMT_MEM_FULL_CH0_S) 783 #define RMT_MEM_FULL_CH0_V 0x00000001U 784 #define RMT_MEM_FULL_CH0_S 24 785 /** RMT_MEM_EMPTY_CH0 : RO; bitpos: [25]; default: 0; 786 * This status bit will be set when the data to be sent is more than memory allows and 787 * the wrap mode is disabled. 788 */ 789 #define RMT_MEM_EMPTY_CH0 (BIT(25)) 790 #define RMT_MEM_EMPTY_CH0_M (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S) 791 #define RMT_MEM_EMPTY_CH0_V 0x00000001U 792 #define RMT_MEM_EMPTY_CH0_S 25 793 /** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [26]; default: 0; 794 * This status bit will be set if the offset address out of memory size when writes 795 * RAM via APB bus. 796 */ 797 #define RMT_APB_MEM_WR_ERR_CH0 (BIT(26)) 798 #define RMT_APB_MEM_WR_ERR_CH0_M (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S) 799 #define RMT_APB_MEM_WR_ERR_CH0_V 0x00000001U 800 #define RMT_APB_MEM_WR_ERR_CH0_S 26 801 /** RMT_APB_MEM_RD_ERR_CH0 : RO; bitpos: [27]; default: 0; 802 * This status bit will be set if the offset address out of memory size when reads RAM 803 * via APB bus. 804 */ 805 #define RMT_APB_MEM_RD_ERR_CH0 (BIT(27)) 806 #define RMT_APB_MEM_RD_ERR_CH0_M (RMT_APB_MEM_RD_ERR_CH0_V << RMT_APB_MEM_RD_ERR_CH0_S) 807 #define RMT_APB_MEM_RD_ERR_CH0_V 0x00000001U 808 #define RMT_APB_MEM_RD_ERR_CH0_S 27 809 810 /** RMT_CH1STATUS_REG register 811 * Channel 1 status register 812 */ 813 #define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x34) 814 /** RMT_MEM_WADDR_EX_CH0 : RO; bitpos: [8:0]; default: 0; 815 * This field records the memory address offset when receiver of channel 1 is using 816 * the RAM. 817 */ 818 #define RMT_MEM_WADDR_EX_CH0 0x000001FFU 819 #define RMT_MEM_WADDR_EX_CH0_M (RMT_MEM_WADDR_EX_CH0_V << RMT_MEM_WADDR_EX_CH0_S) 820 #define RMT_MEM_WADDR_EX_CH0_V 0x000001FFU 821 #define RMT_MEM_WADDR_EX_CH0_S 0 822 /** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [18:10]; default: 0; 823 * This field records the memory address offset when transmitter of channel 1 is using 824 * the RAM. 825 */ 826 #define RMT_MEM_RADDR_EX_CH0 0x000001FFU 827 #define RMT_MEM_RADDR_EX_CH0_M (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S) 828 #define RMT_MEM_RADDR_EX_CH0_V 0x000001FFU 829 #define RMT_MEM_RADDR_EX_CH0_S 10 830 /** RMT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; 831 * This field records the FSM status of channel 1. 832 */ 833 #define RMT_STATE_CH0 0x00000007U 834 #define RMT_STATE_CH0_M (RMT_STATE_CH0_V << RMT_STATE_CH0_S) 835 #define RMT_STATE_CH0_V 0x00000007U 836 #define RMT_STATE_CH0_S 20 837 /** RMT_MEM_OWNER_ERR_CH0 : RO; bitpos: [23]; default: 0; 838 * This status bit will be set when the ownership of memory block is violated. 839 */ 840 #define RMT_MEM_OWNER_ERR_CH0 (BIT(23)) 841 #define RMT_MEM_OWNER_ERR_CH0_M (RMT_MEM_OWNER_ERR_CH0_V << RMT_MEM_OWNER_ERR_CH0_S) 842 #define RMT_MEM_OWNER_ERR_CH0_V 0x00000001U 843 #define RMT_MEM_OWNER_ERR_CH0_S 23 844 /** RMT_MEM_FULL_CH0 : RO; bitpos: [24]; default: 0; 845 * This status bit will be set if the receiver receives more data than the memory 846 * allows. 847 */ 848 #define RMT_MEM_FULL_CH0 (BIT(24)) 849 #define RMT_MEM_FULL_CH0_M (RMT_MEM_FULL_CH0_V << RMT_MEM_FULL_CH0_S) 850 #define RMT_MEM_FULL_CH0_V 0x00000001U 851 #define RMT_MEM_FULL_CH0_S 24 852 /** RMT_MEM_EMPTY_CH0 : RO; bitpos: [25]; default: 0; 853 * This status bit will be set when the data to be sent is more than memory allows and 854 * the wrap mode is disabled. 855 */ 856 #define RMT_MEM_EMPTY_CH0 (BIT(25)) 857 #define RMT_MEM_EMPTY_CH0_M (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S) 858 #define RMT_MEM_EMPTY_CH0_V 0x00000001U 859 #define RMT_MEM_EMPTY_CH0_S 25 860 /** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [26]; default: 0; 861 * This status bit will be set if the offset address out of memory size when writes 862 * RAM via APB bus. 863 */ 864 #define RMT_APB_MEM_WR_ERR_CH0 (BIT(26)) 865 #define RMT_APB_MEM_WR_ERR_CH0_M (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S) 866 #define RMT_APB_MEM_WR_ERR_CH0_V 0x00000001U 867 #define RMT_APB_MEM_WR_ERR_CH0_S 26 868 /** RMT_APB_MEM_RD_ERR_CH0 : RO; bitpos: [27]; default: 0; 869 * This status bit will be set if the offset address out of memory size when reads RAM 870 * via APB bus. 871 */ 872 #define RMT_APB_MEM_RD_ERR_CH0 (BIT(27)) 873 #define RMT_APB_MEM_RD_ERR_CH0_M (RMT_APB_MEM_RD_ERR_CH0_V << RMT_APB_MEM_RD_ERR_CH0_S) 874 #define RMT_APB_MEM_RD_ERR_CH0_V 0x00000001U 875 #define RMT_APB_MEM_RD_ERR_CH0_S 27 876 877 /** RMT_CH2STATUS_REG register 878 * Channel 2 status register 879 */ 880 #define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x38) 881 /** RMT_MEM_WADDR_EX_CH0 : RO; bitpos: [8:0]; default: 0; 882 * This field records the memory address offset when receiver of channel 2 is using 883 * the RAM. 884 */ 885 #define RMT_MEM_WADDR_EX_CH0 0x000001FFU 886 #define RMT_MEM_WADDR_EX_CH0_M (RMT_MEM_WADDR_EX_CH0_V << RMT_MEM_WADDR_EX_CH0_S) 887 #define RMT_MEM_WADDR_EX_CH0_V 0x000001FFU 888 #define RMT_MEM_WADDR_EX_CH0_S 0 889 /** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [18:10]; default: 0; 890 * This field records the memory address offset when transmitter of channel 2 is using 891 * the RAM. 892 */ 893 #define RMT_MEM_RADDR_EX_CH0 0x000001FFU 894 #define RMT_MEM_RADDR_EX_CH0_M (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S) 895 #define RMT_MEM_RADDR_EX_CH0_V 0x000001FFU 896 #define RMT_MEM_RADDR_EX_CH0_S 10 897 /** RMT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; 898 * This field records the FSM status of channel 2. 899 */ 900 #define RMT_STATE_CH0 0x00000007U 901 #define RMT_STATE_CH0_M (RMT_STATE_CH0_V << RMT_STATE_CH0_S) 902 #define RMT_STATE_CH0_V 0x00000007U 903 #define RMT_STATE_CH0_S 20 904 /** RMT_MEM_OWNER_ERR_CH0 : RO; bitpos: [23]; default: 0; 905 * This status bit will be set when the ownership of memory block is violated. 906 */ 907 #define RMT_MEM_OWNER_ERR_CH0 (BIT(23)) 908 #define RMT_MEM_OWNER_ERR_CH0_M (RMT_MEM_OWNER_ERR_CH0_V << RMT_MEM_OWNER_ERR_CH0_S) 909 #define RMT_MEM_OWNER_ERR_CH0_V 0x00000001U 910 #define RMT_MEM_OWNER_ERR_CH0_S 23 911 /** RMT_MEM_FULL_CH0 : RO; bitpos: [24]; default: 0; 912 * This status bit will be set if the receiver receives more data than the memory 913 * allows. 914 */ 915 #define RMT_MEM_FULL_CH0 (BIT(24)) 916 #define RMT_MEM_FULL_CH0_M (RMT_MEM_FULL_CH0_V << RMT_MEM_FULL_CH0_S) 917 #define RMT_MEM_FULL_CH0_V 0x00000001U 918 #define RMT_MEM_FULL_CH0_S 24 919 /** RMT_MEM_EMPTY_CH0 : RO; bitpos: [25]; default: 0; 920 * This status bit will be set when the data to be sent is more than memory allows and 921 * the wrap mode is disabled. 922 */ 923 #define RMT_MEM_EMPTY_CH0 (BIT(25)) 924 #define RMT_MEM_EMPTY_CH0_M (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S) 925 #define RMT_MEM_EMPTY_CH0_V 0x00000001U 926 #define RMT_MEM_EMPTY_CH0_S 25 927 /** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [26]; default: 0; 928 * This status bit will be set if the offset address out of memory size when writes 929 * RAM via APB bus. 930 */ 931 #define RMT_APB_MEM_WR_ERR_CH0 (BIT(26)) 932 #define RMT_APB_MEM_WR_ERR_CH0_M (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S) 933 #define RMT_APB_MEM_WR_ERR_CH0_V 0x00000001U 934 #define RMT_APB_MEM_WR_ERR_CH0_S 26 935 /** RMT_APB_MEM_RD_ERR_CH0 : RO; bitpos: [27]; default: 0; 936 * This status bit will be set if the offset address out of memory size when reads RAM 937 * via APB bus. 938 */ 939 #define RMT_APB_MEM_RD_ERR_CH0 (BIT(27)) 940 #define RMT_APB_MEM_RD_ERR_CH0_M (RMT_APB_MEM_RD_ERR_CH0_V << RMT_APB_MEM_RD_ERR_CH0_S) 941 #define RMT_APB_MEM_RD_ERR_CH0_V 0x00000001U 942 #define RMT_APB_MEM_RD_ERR_CH0_S 27 943 944 /** RMT_CH3STATUS_REG register 945 * Channel 3 status register 946 */ 947 #define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x3c) 948 /** RMT_MEM_WADDR_EX_CH0 : RO; bitpos: [8:0]; default: 0; 949 * This field records the memory address offset when receiver of channel 3 is using 950 * the RAM. 951 */ 952 #define RMT_MEM_WADDR_EX_CH0 0x000001FFU 953 #define RMT_MEM_WADDR_EX_CH0_M (RMT_MEM_WADDR_EX_CH0_V << RMT_MEM_WADDR_EX_CH0_S) 954 #define RMT_MEM_WADDR_EX_CH0_V 0x000001FFU 955 #define RMT_MEM_WADDR_EX_CH0_S 0 956 /** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [18:10]; default: 0; 957 * This field records the memory address offset when transmitter of channel 3 is using 958 * the RAM. 959 */ 960 #define RMT_MEM_RADDR_EX_CH0 0x000001FFU 961 #define RMT_MEM_RADDR_EX_CH0_M (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S) 962 #define RMT_MEM_RADDR_EX_CH0_V 0x000001FFU 963 #define RMT_MEM_RADDR_EX_CH0_S 10 964 /** RMT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; 965 * This field records the FSM status of channel 3. 966 */ 967 #define RMT_STATE_CH0 0x00000007U 968 #define RMT_STATE_CH0_M (RMT_STATE_CH0_V << RMT_STATE_CH0_S) 969 #define RMT_STATE_CH0_V 0x00000007U 970 #define RMT_STATE_CH0_S 20 971 /** RMT_MEM_OWNER_ERR_CH0 : RO; bitpos: [23]; default: 0; 972 * This status bit will be set when the ownership of memory block is violated. 973 */ 974 #define RMT_MEM_OWNER_ERR_CH0 (BIT(23)) 975 #define RMT_MEM_OWNER_ERR_CH0_M (RMT_MEM_OWNER_ERR_CH0_V << RMT_MEM_OWNER_ERR_CH0_S) 976 #define RMT_MEM_OWNER_ERR_CH0_V 0x00000001U 977 #define RMT_MEM_OWNER_ERR_CH0_S 23 978 /** RMT_MEM_FULL_CH0 : RO; bitpos: [24]; default: 0; 979 * This status bit will be set if the receiver receives more data than the memory 980 * allows. 981 */ 982 #define RMT_MEM_FULL_CH0 (BIT(24)) 983 #define RMT_MEM_FULL_CH0_M (RMT_MEM_FULL_CH0_V << RMT_MEM_FULL_CH0_S) 984 #define RMT_MEM_FULL_CH0_V 0x00000001U 985 #define RMT_MEM_FULL_CH0_S 24 986 /** RMT_MEM_EMPTY_CH0 : RO; bitpos: [25]; default: 0; 987 * This status bit will be set when the data to be sent is more than memory allows and 988 * the wrap mode is disabled. 989 */ 990 #define RMT_MEM_EMPTY_CH0 (BIT(25)) 991 #define RMT_MEM_EMPTY_CH0_M (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S) 992 #define RMT_MEM_EMPTY_CH0_V 0x00000001U 993 #define RMT_MEM_EMPTY_CH0_S 25 994 /** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [26]; default: 0; 995 * This status bit will be set if the offset address out of memory size when writes 996 * RAM via APB bus. 997 */ 998 #define RMT_APB_MEM_WR_ERR_CH0 (BIT(26)) 999 #define RMT_APB_MEM_WR_ERR_CH0_M (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S) 1000 #define RMT_APB_MEM_WR_ERR_CH0_V 0x00000001U 1001 #define RMT_APB_MEM_WR_ERR_CH0_S 26 1002 /** RMT_APB_MEM_RD_ERR_CH0 : RO; bitpos: [27]; default: 0; 1003 * This status bit will be set if the offset address out of memory size when reads RAM 1004 * via APB bus. 1005 */ 1006 #define RMT_APB_MEM_RD_ERR_CH0 (BIT(27)) 1007 #define RMT_APB_MEM_RD_ERR_CH0_M (RMT_APB_MEM_RD_ERR_CH0_V << RMT_APB_MEM_RD_ERR_CH0_S) 1008 #define RMT_APB_MEM_RD_ERR_CH0_V 0x00000001U 1009 #define RMT_APB_MEM_RD_ERR_CH0_S 27 1010 1011 /** RMT_CH0ADDR_REG register 1012 * Channel 0 address register 1013 */ 1014 #define RMT_CH0ADDR_REG (DR_REG_RMT_BASE + 0x40) 1015 /** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [8:0]; default: 0; 1016 * This field records the memory address offset when channel 0 writes RAM via APB bus. 1017 */ 1018 #define RMT_APB_MEM_WADDR_CH0 0x000001FFU 1019 #define RMT_APB_MEM_WADDR_CH0_M (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S) 1020 #define RMT_APB_MEM_WADDR_CH0_V 0x000001FFU 1021 #define RMT_APB_MEM_WADDR_CH0_S 0 1022 /** RMT_APB_MEM_RADDR_CH0 : RO; bitpos: [18:10]; default: 0; 1023 * This field records the memory address offset when channel 0 reads RAM via APB bus. 1024 */ 1025 #define RMT_APB_MEM_RADDR_CH0 0x000001FFU 1026 #define RMT_APB_MEM_RADDR_CH0_M (RMT_APB_MEM_RADDR_CH0_V << RMT_APB_MEM_RADDR_CH0_S) 1027 #define RMT_APB_MEM_RADDR_CH0_V 0x000001FFU 1028 #define RMT_APB_MEM_RADDR_CH0_S 10 1029 1030 /** RMT_CH1ADDR_REG register 1031 * Channel 1 address register 1032 */ 1033 #define RMT_CH1ADDR_REG (DR_REG_RMT_BASE + 0x44) 1034 /** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [8:0]; default: 0; 1035 * This field records the memory address offset when channel 1 writes RAM via APB bus. 1036 */ 1037 #define RMT_APB_MEM_WADDR_CH0 0x000001FFU 1038 #define RMT_APB_MEM_WADDR_CH0_M (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S) 1039 #define RMT_APB_MEM_WADDR_CH0_V 0x000001FFU 1040 #define RMT_APB_MEM_WADDR_CH0_S 0 1041 /** RMT_APB_MEM_RADDR_CH0 : RO; bitpos: [18:10]; default: 0; 1042 * This field records the memory address offset when channel 1 reads RAM via APB bus. 1043 */ 1044 #define RMT_APB_MEM_RADDR_CH0 0x000001FFU 1045 #define RMT_APB_MEM_RADDR_CH0_M (RMT_APB_MEM_RADDR_CH0_V << RMT_APB_MEM_RADDR_CH0_S) 1046 #define RMT_APB_MEM_RADDR_CH0_V 0x000001FFU 1047 #define RMT_APB_MEM_RADDR_CH0_S 10 1048 1049 /** RMT_CH2ADDR_REG register 1050 * Channel 2 address register 1051 */ 1052 #define RMT_CH2ADDR_REG (DR_REG_RMT_BASE + 0x48) 1053 /** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [8:0]; default: 0; 1054 * This field records the memory address offset when channel 2 writes RAM via APB bus. 1055 */ 1056 #define RMT_APB_MEM_WADDR_CH0 0x000001FFU 1057 #define RMT_APB_MEM_WADDR_CH0_M (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S) 1058 #define RMT_APB_MEM_WADDR_CH0_V 0x000001FFU 1059 #define RMT_APB_MEM_WADDR_CH0_S 0 1060 /** RMT_APB_MEM_RADDR_CH0 : RO; bitpos: [18:10]; default: 0; 1061 * This field records the memory address offset when channel 2 reads RAM via APB bus. 1062 */ 1063 #define RMT_APB_MEM_RADDR_CH0 0x000001FFU 1064 #define RMT_APB_MEM_RADDR_CH0_M (RMT_APB_MEM_RADDR_CH0_V << RMT_APB_MEM_RADDR_CH0_S) 1065 #define RMT_APB_MEM_RADDR_CH0_V 0x000001FFU 1066 #define RMT_APB_MEM_RADDR_CH0_S 10 1067 1068 /** RMT_CH3ADDR_REG register 1069 * Channel 3 address register 1070 */ 1071 #define RMT_CH3ADDR_REG (DR_REG_RMT_BASE + 0x4c) 1072 /** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [8:0]; default: 0; 1073 * This field records the memory address offset when channel 3 writes RAM via APB bus. 1074 */ 1075 #define RMT_APB_MEM_WADDR_CH0 0x000001FFU 1076 #define RMT_APB_MEM_WADDR_CH0_M (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S) 1077 #define RMT_APB_MEM_WADDR_CH0_V 0x000001FFU 1078 #define RMT_APB_MEM_WADDR_CH0_S 0 1079 /** RMT_APB_MEM_RADDR_CH0 : RO; bitpos: [18:10]; default: 0; 1080 * This field records the memory address offset when channel 3 reads RAM via APB bus. 1081 */ 1082 #define RMT_APB_MEM_RADDR_CH0 0x000001FFU 1083 #define RMT_APB_MEM_RADDR_CH0_M (RMT_APB_MEM_RADDR_CH0_V << RMT_APB_MEM_RADDR_CH0_S) 1084 #define RMT_APB_MEM_RADDR_CH0_V 0x000001FFU 1085 #define RMT_APB_MEM_RADDR_CH0_S 10 1086 1087 /** RMT_INT_RAW_REG register 1088 * Raw interrupt status register 1089 */ 1090 #define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x50) 1091 /** RMT_CH0_TX_END_INT_RAW : RO; bitpos: [0]; default: 0; 1092 * The interrupt raw bit for channel 0. Triggered when transmitting ends. 1093 */ 1094 #define RMT_CH0_TX_END_INT_RAW (BIT(0)) 1095 #define RMT_CH0_TX_END_INT_RAW_M (RMT_CH0_TX_END_INT_RAW_V << RMT_CH0_TX_END_INT_RAW_S) 1096 #define RMT_CH0_TX_END_INT_RAW_V 0x00000001U 1097 #define RMT_CH0_TX_END_INT_RAW_S 0 1098 /** RMT_CH0_RX_END_INT_RAW : RO; bitpos: [1]; default: 0; 1099 * The interrupt raw bit for channel 0. Triggered when receiving ends. 1100 */ 1101 #define RMT_CH0_RX_END_INT_RAW (BIT(1)) 1102 #define RMT_CH0_RX_END_INT_RAW_M (RMT_CH0_RX_END_INT_RAW_V << RMT_CH0_RX_END_INT_RAW_S) 1103 #define RMT_CH0_RX_END_INT_RAW_V 0x00000001U 1104 #define RMT_CH0_RX_END_INT_RAW_S 1 1105 /** RMT_CH0_ERR_INT_RAW : RO; bitpos: [2]; default: 0; 1106 * The interrupt raw bit for channel 0. Triggered when error occurs. 1107 */ 1108 #define RMT_CH0_ERR_INT_RAW (BIT(2)) 1109 #define RMT_CH0_ERR_INT_RAW_M (RMT_CH0_ERR_INT_RAW_V << RMT_CH0_ERR_INT_RAW_S) 1110 #define RMT_CH0_ERR_INT_RAW_V 0x00000001U 1111 #define RMT_CH0_ERR_INT_RAW_S 2 1112 /** RMT_CH1_TX_END_INT_RAW : RO; bitpos: [3]; default: 0; 1113 * The interrupt raw bit for channel 1. Triggered when transmitting ends. 1114 */ 1115 #define RMT_CH1_TX_END_INT_RAW (BIT(3)) 1116 #define RMT_CH1_TX_END_INT_RAW_M (RMT_CH1_TX_END_INT_RAW_V << RMT_CH1_TX_END_INT_RAW_S) 1117 #define RMT_CH1_TX_END_INT_RAW_V 0x00000001U 1118 #define RMT_CH1_TX_END_INT_RAW_S 3 1119 /** RMT_CH1_RX_END_INT_RAW : RO; bitpos: [4]; default: 0; 1120 * The interrupt raw bit for channel 1. Triggered when receiving ends. 1121 */ 1122 #define RMT_CH1_RX_END_INT_RAW (BIT(4)) 1123 #define RMT_CH1_RX_END_INT_RAW_M (RMT_CH1_RX_END_INT_RAW_V << RMT_CH1_RX_END_INT_RAW_S) 1124 #define RMT_CH1_RX_END_INT_RAW_V 0x00000001U 1125 #define RMT_CH1_RX_END_INT_RAW_S 4 1126 /** RMT_CH1_ERR_INT_RAW : RO; bitpos: [5]; default: 0; 1127 * The interrupt raw bit for channel 1. Triggered when error occurs. 1128 */ 1129 #define RMT_CH1_ERR_INT_RAW (BIT(5)) 1130 #define RMT_CH1_ERR_INT_RAW_M (RMT_CH1_ERR_INT_RAW_V << RMT_CH1_ERR_INT_RAW_S) 1131 #define RMT_CH1_ERR_INT_RAW_V 0x00000001U 1132 #define RMT_CH1_ERR_INT_RAW_S 5 1133 /** RMT_CH2_TX_END_INT_RAW : RO; bitpos: [6]; default: 0; 1134 * The interrupt raw bit for channel 2. Triggered when transmitting ends. 1135 */ 1136 #define RMT_CH2_TX_END_INT_RAW (BIT(6)) 1137 #define RMT_CH2_TX_END_INT_RAW_M (RMT_CH2_TX_END_INT_RAW_V << RMT_CH2_TX_END_INT_RAW_S) 1138 #define RMT_CH2_TX_END_INT_RAW_V 0x00000001U 1139 #define RMT_CH2_TX_END_INT_RAW_S 6 1140 /** RMT_CH2_RX_END_INT_RAW : RO; bitpos: [7]; default: 0; 1141 * The interrupt raw bit for channel 2. Triggered when receiving ends. 1142 */ 1143 #define RMT_CH2_RX_END_INT_RAW (BIT(7)) 1144 #define RMT_CH2_RX_END_INT_RAW_M (RMT_CH2_RX_END_INT_RAW_V << RMT_CH2_RX_END_INT_RAW_S) 1145 #define RMT_CH2_RX_END_INT_RAW_V 0x00000001U 1146 #define RMT_CH2_RX_END_INT_RAW_S 7 1147 /** RMT_CH2_ERR_INT_RAW : RO; bitpos: [8]; default: 0; 1148 * The interrupt raw bit for channel 2. Triggered when error occurs. 1149 */ 1150 #define RMT_CH2_ERR_INT_RAW (BIT(8)) 1151 #define RMT_CH2_ERR_INT_RAW_M (RMT_CH2_ERR_INT_RAW_V << RMT_CH2_ERR_INT_RAW_S) 1152 #define RMT_CH2_ERR_INT_RAW_V 0x00000001U 1153 #define RMT_CH2_ERR_INT_RAW_S 8 1154 /** RMT_CH3_TX_END_INT_RAW : RO; bitpos: [9]; default: 0; 1155 * The interrupt raw bit for channel 3. Triggered when transmitting ends. 1156 */ 1157 #define RMT_CH3_TX_END_INT_RAW (BIT(9)) 1158 #define RMT_CH3_TX_END_INT_RAW_M (RMT_CH3_TX_END_INT_RAW_V << RMT_CH3_TX_END_INT_RAW_S) 1159 #define RMT_CH3_TX_END_INT_RAW_V 0x00000001U 1160 #define RMT_CH3_TX_END_INT_RAW_S 9 1161 /** RMT_CH3_RX_END_INT_RAW : RO; bitpos: [10]; default: 0; 1162 * The interrupt raw bit for channel 3. Triggered when receiving ends. 1163 */ 1164 #define RMT_CH3_RX_END_INT_RAW (BIT(10)) 1165 #define RMT_CH3_RX_END_INT_RAW_M (RMT_CH3_RX_END_INT_RAW_V << RMT_CH3_RX_END_INT_RAW_S) 1166 #define RMT_CH3_RX_END_INT_RAW_V 0x00000001U 1167 #define RMT_CH3_RX_END_INT_RAW_S 10 1168 /** RMT_CH3_ERR_INT_RAW : RO; bitpos: [11]; default: 0; 1169 * The interrupt raw bit for channel 3. Triggered when error occurs. 1170 */ 1171 #define RMT_CH3_ERR_INT_RAW (BIT(11)) 1172 #define RMT_CH3_ERR_INT_RAW_M (RMT_CH3_ERR_INT_RAW_V << RMT_CH3_ERR_INT_RAW_S) 1173 #define RMT_CH3_ERR_INT_RAW_V 0x00000001U 1174 #define RMT_CH3_ERR_INT_RAW_S 11 1175 /** RMT_CH0_TX_THR_EVENT_INT_RAW : RO; bitpos: [12]; default: 0; 1176 * The interrupt raw bit for channel 0. Triggered when transmitter sends more data 1177 * than configured value. 1178 */ 1179 #define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(12)) 1180 #define RMT_CH0_TX_THR_EVENT_INT_RAW_M (RMT_CH0_TX_THR_EVENT_INT_RAW_V << RMT_CH0_TX_THR_EVENT_INT_RAW_S) 1181 #define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x00000001U 1182 #define RMT_CH0_TX_THR_EVENT_INT_RAW_S 12 1183 /** RMT_CH1_TX_THR_EVENT_INT_RAW : RO; bitpos: [13]; default: 0; 1184 * The interrupt raw bit for channel 1. Triggered when transmitter sends more data 1185 * than configured value. 1186 */ 1187 #define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(13)) 1188 #define RMT_CH1_TX_THR_EVENT_INT_RAW_M (RMT_CH1_TX_THR_EVENT_INT_RAW_V << RMT_CH1_TX_THR_EVENT_INT_RAW_S) 1189 #define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x00000001U 1190 #define RMT_CH1_TX_THR_EVENT_INT_RAW_S 13 1191 /** RMT_CH2_TX_THR_EVENT_INT_RAW : RO; bitpos: [14]; default: 0; 1192 * The interrupt raw bit for channel 2. Triggered when transmitter sends more data 1193 * than configured value. 1194 */ 1195 #define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(14)) 1196 #define RMT_CH2_TX_THR_EVENT_INT_RAW_M (RMT_CH2_TX_THR_EVENT_INT_RAW_V << RMT_CH2_TX_THR_EVENT_INT_RAW_S) 1197 #define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x00000001U 1198 #define RMT_CH2_TX_THR_EVENT_INT_RAW_S 14 1199 /** RMT_CH3_TX_THR_EVENT_INT_RAW : RO; bitpos: [15]; default: 0; 1200 * The interrupt raw bit for channel 3. Triggered when transmitter sends more data 1201 * than configured value. 1202 */ 1203 #define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(15)) 1204 #define RMT_CH3_TX_THR_EVENT_INT_RAW_M (RMT_CH3_TX_THR_EVENT_INT_RAW_V << RMT_CH3_TX_THR_EVENT_INT_RAW_S) 1205 #define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x00000001U 1206 #define RMT_CH3_TX_THR_EVENT_INT_RAW_S 15 1207 /** RMT_CH0_TX_LOOP_INT_RAW : RO; bitpos: [16]; default: 0; 1208 * The interrupt raw bit for channel 0. Triggered when loop counting reaches the 1209 * configured threshold value. 1210 */ 1211 #define RMT_CH0_TX_LOOP_INT_RAW (BIT(16)) 1212 #define RMT_CH0_TX_LOOP_INT_RAW_M (RMT_CH0_TX_LOOP_INT_RAW_V << RMT_CH0_TX_LOOP_INT_RAW_S) 1213 #define RMT_CH0_TX_LOOP_INT_RAW_V 0x00000001U 1214 #define RMT_CH0_TX_LOOP_INT_RAW_S 16 1215 /** RMT_CH1_TX_LOOP_INT_RAW : RO; bitpos: [17]; default: 0; 1216 * The interrupt raw bit for channel 1. Triggered when loop counting reaches the 1217 * configured threshold value. 1218 */ 1219 #define RMT_CH1_TX_LOOP_INT_RAW (BIT(17)) 1220 #define RMT_CH1_TX_LOOP_INT_RAW_M (RMT_CH1_TX_LOOP_INT_RAW_V << RMT_CH1_TX_LOOP_INT_RAW_S) 1221 #define RMT_CH1_TX_LOOP_INT_RAW_V 0x00000001U 1222 #define RMT_CH1_TX_LOOP_INT_RAW_S 17 1223 /** RMT_CH2_TX_LOOP_INT_RAW : RO; bitpos: [18]; default: 0; 1224 * The interrupt raw bit for channel 2. Triggered when loop counting reaches the 1225 * configured threshold value. 1226 */ 1227 #define RMT_CH2_TX_LOOP_INT_RAW (BIT(18)) 1228 #define RMT_CH2_TX_LOOP_INT_RAW_M (RMT_CH2_TX_LOOP_INT_RAW_V << RMT_CH2_TX_LOOP_INT_RAW_S) 1229 #define RMT_CH2_TX_LOOP_INT_RAW_V 0x00000001U 1230 #define RMT_CH2_TX_LOOP_INT_RAW_S 18 1231 /** RMT_CH3_TX_LOOP_INT_RAW : RO; bitpos: [19]; default: 0; 1232 * The interrupt raw bit for channel 3. Triggered when loop counting reaches the 1233 * configured threshold value. 1234 */ 1235 #define RMT_CH3_TX_LOOP_INT_RAW (BIT(19)) 1236 #define RMT_CH3_TX_LOOP_INT_RAW_M (RMT_CH3_TX_LOOP_INT_RAW_V << RMT_CH3_TX_LOOP_INT_RAW_S) 1237 #define RMT_CH3_TX_LOOP_INT_RAW_V 0x00000001U 1238 #define RMT_CH3_TX_LOOP_INT_RAW_S 19 1239 1240 /** RMT_INT_ST_REG register 1241 * Masked interrupt status register 1242 */ 1243 #define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x54) 1244 /** RMT_CH0_TX_END_INT_ST : RO; bitpos: [0]; default: 0; 1245 * The masked interrupt status bit for RMT_CH0_TX_END_INT. 1246 */ 1247 #define RMT_CH0_TX_END_INT_ST (BIT(0)) 1248 #define RMT_CH0_TX_END_INT_ST_M (RMT_CH0_TX_END_INT_ST_V << RMT_CH0_TX_END_INT_ST_S) 1249 #define RMT_CH0_TX_END_INT_ST_V 0x00000001U 1250 #define RMT_CH0_TX_END_INT_ST_S 0 1251 /** RMT_CH0_RX_END_INT_ST : RO; bitpos: [1]; default: 0; 1252 * The masked interrupt status bit for RMT_CH0_RX_END_INT. 1253 */ 1254 #define RMT_CH0_RX_END_INT_ST (BIT(1)) 1255 #define RMT_CH0_RX_END_INT_ST_M (RMT_CH0_RX_END_INT_ST_V << RMT_CH0_RX_END_INT_ST_S) 1256 #define RMT_CH0_RX_END_INT_ST_V 0x00000001U 1257 #define RMT_CH0_RX_END_INT_ST_S 1 1258 /** RMT_CH0_ERR_INT_ST : RO; bitpos: [2]; default: 0; 1259 * The masked interrupt status bit for RMT_CH0_ERR_INT. 1260 */ 1261 #define RMT_CH0_ERR_INT_ST (BIT(2)) 1262 #define RMT_CH0_ERR_INT_ST_M (RMT_CH0_ERR_INT_ST_V << RMT_CH0_ERR_INT_ST_S) 1263 #define RMT_CH0_ERR_INT_ST_V 0x00000001U 1264 #define RMT_CH0_ERR_INT_ST_S 2 1265 /** RMT_CH1_TX_END_INT_ST : RO; bitpos: [3]; default: 0; 1266 * The masked interrupt status bit for RMT_CH1_TX_END_INT. 1267 */ 1268 #define RMT_CH1_TX_END_INT_ST (BIT(3)) 1269 #define RMT_CH1_TX_END_INT_ST_M (RMT_CH1_TX_END_INT_ST_V << RMT_CH1_TX_END_INT_ST_S) 1270 #define RMT_CH1_TX_END_INT_ST_V 0x00000001U 1271 #define RMT_CH1_TX_END_INT_ST_S 3 1272 /** RMT_CH1_RX_END_INT_ST : RO; bitpos: [4]; default: 0; 1273 * The masked interrupt status bit for RMT_CH1_RX_END_INT. 1274 */ 1275 #define RMT_CH1_RX_END_INT_ST (BIT(4)) 1276 #define RMT_CH1_RX_END_INT_ST_M (RMT_CH1_RX_END_INT_ST_V << RMT_CH1_RX_END_INT_ST_S) 1277 #define RMT_CH1_RX_END_INT_ST_V 0x00000001U 1278 #define RMT_CH1_RX_END_INT_ST_S 4 1279 /** RMT_CH1_ERR_INT_ST : RO; bitpos: [5]; default: 0; 1280 * The masked interrupt status bit for RMT_CH1_ERR_INT. 1281 */ 1282 #define RMT_CH1_ERR_INT_ST (BIT(5)) 1283 #define RMT_CH1_ERR_INT_ST_M (RMT_CH1_ERR_INT_ST_V << RMT_CH1_ERR_INT_ST_S) 1284 #define RMT_CH1_ERR_INT_ST_V 0x00000001U 1285 #define RMT_CH1_ERR_INT_ST_S 5 1286 /** RMT_CH2_TX_END_INT_ST : RO; bitpos: [6]; default: 0; 1287 * The masked interrupt status bit for RMT_CH2_TX_END_INT. 1288 */ 1289 #define RMT_CH2_TX_END_INT_ST (BIT(6)) 1290 #define RMT_CH2_TX_END_INT_ST_M (RMT_CH2_TX_END_INT_ST_V << RMT_CH2_TX_END_INT_ST_S) 1291 #define RMT_CH2_TX_END_INT_ST_V 0x00000001U 1292 #define RMT_CH2_TX_END_INT_ST_S 6 1293 /** RMT_CH2_RX_END_INT_ST : RO; bitpos: [7]; default: 0; 1294 * The masked interrupt status bit for RMT_CH2_RX_END_INT. 1295 */ 1296 #define RMT_CH2_RX_END_INT_ST (BIT(7)) 1297 #define RMT_CH2_RX_END_INT_ST_M (RMT_CH2_RX_END_INT_ST_V << RMT_CH2_RX_END_INT_ST_S) 1298 #define RMT_CH2_RX_END_INT_ST_V 0x00000001U 1299 #define RMT_CH2_RX_END_INT_ST_S 7 1300 /** RMT_CH2_ERR_INT_ST : RO; bitpos: [8]; default: 0; 1301 * The masked interrupt status bit for RMT_CH2_ERR_INT. 1302 */ 1303 #define RMT_CH2_ERR_INT_ST (BIT(8)) 1304 #define RMT_CH2_ERR_INT_ST_M (RMT_CH2_ERR_INT_ST_V << RMT_CH2_ERR_INT_ST_S) 1305 #define RMT_CH2_ERR_INT_ST_V 0x00000001U 1306 #define RMT_CH2_ERR_INT_ST_S 8 1307 /** RMT_CH3_TX_END_INT_ST : RO; bitpos: [9]; default: 0; 1308 * The masked interrupt status bit for RMT_CH3_TX_END_INT. 1309 */ 1310 #define RMT_CH3_TX_END_INT_ST (BIT(9)) 1311 #define RMT_CH3_TX_END_INT_ST_M (RMT_CH3_TX_END_INT_ST_V << RMT_CH3_TX_END_INT_ST_S) 1312 #define RMT_CH3_TX_END_INT_ST_V 0x00000001U 1313 #define RMT_CH3_TX_END_INT_ST_S 9 1314 /** RMT_CH3_RX_END_INT_ST : RO; bitpos: [10]; default: 0; 1315 * The masked interrupt status bit for RMT_CH3_RX_END_INT. 1316 */ 1317 #define RMT_CH3_RX_END_INT_ST (BIT(10)) 1318 #define RMT_CH3_RX_END_INT_ST_M (RMT_CH3_RX_END_INT_ST_V << RMT_CH3_RX_END_INT_ST_S) 1319 #define RMT_CH3_RX_END_INT_ST_V 0x00000001U 1320 #define RMT_CH3_RX_END_INT_ST_S 10 1321 /** RMT_CH3_ERR_INT_ST : RO; bitpos: [11]; default: 0; 1322 * The masked interrupt status bit for RMT_CH3_ERR_INT. 1323 */ 1324 #define RMT_CH3_ERR_INT_ST (BIT(11)) 1325 #define RMT_CH3_ERR_INT_ST_M (RMT_CH3_ERR_INT_ST_V << RMT_CH3_ERR_INT_ST_S) 1326 #define RMT_CH3_ERR_INT_ST_V 0x00000001U 1327 #define RMT_CH3_ERR_INT_ST_S 11 1328 /** RMT_CH0_TX_THR_EVENT_INT_ST : RO; bitpos: [12]; default: 0; 1329 * The masked interrupt status bit for RMT_CH0_TX_THR_EVENT_INT. 1330 */ 1331 #define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(12)) 1332 #define RMT_CH0_TX_THR_EVENT_INT_ST_M (RMT_CH0_TX_THR_EVENT_INT_ST_V << RMT_CH0_TX_THR_EVENT_INT_ST_S) 1333 #define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x00000001U 1334 #define RMT_CH0_TX_THR_EVENT_INT_ST_S 12 1335 /** RMT_CH1_TX_THR_EVENT_INT_ST : RO; bitpos: [13]; default: 0; 1336 * The masked interrupt status bit for RMT_CH1_TX_THR_EVENT_INT. 1337 */ 1338 #define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(13)) 1339 #define RMT_CH1_TX_THR_EVENT_INT_ST_M (RMT_CH1_TX_THR_EVENT_INT_ST_V << RMT_CH1_TX_THR_EVENT_INT_ST_S) 1340 #define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x00000001U 1341 #define RMT_CH1_TX_THR_EVENT_INT_ST_S 13 1342 /** RMT_CH2_TX_THR_EVENT_INT_ST : RO; bitpos: [14]; default: 0; 1343 * The masked interrupt status bit for RMT_CH2_TX_THR_EVENT_INT. 1344 */ 1345 #define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(14)) 1346 #define RMT_CH2_TX_THR_EVENT_INT_ST_M (RMT_CH2_TX_THR_EVENT_INT_ST_V << RMT_CH2_TX_THR_EVENT_INT_ST_S) 1347 #define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x00000001U 1348 #define RMT_CH2_TX_THR_EVENT_INT_ST_S 14 1349 /** RMT_CH3_TX_THR_EVENT_INT_ST : RO; bitpos: [15]; default: 0; 1350 * The masked interrupt status bit for RMT_CH3_TX_THR_EVENT_INT. 1351 */ 1352 #define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(15)) 1353 #define RMT_CH3_TX_THR_EVENT_INT_ST_M (RMT_CH3_TX_THR_EVENT_INT_ST_V << RMT_CH3_TX_THR_EVENT_INT_ST_S) 1354 #define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x00000001U 1355 #define RMT_CH3_TX_THR_EVENT_INT_ST_S 15 1356 /** RMT_CH0_TX_LOOP_INT_ST : RO; bitpos: [16]; default: 0; 1357 * The masked interrupt status bit for RMT_CH0_TX_LOOP_INT. 1358 */ 1359 #define RMT_CH0_TX_LOOP_INT_ST (BIT(16)) 1360 #define RMT_CH0_TX_LOOP_INT_ST_M (RMT_CH0_TX_LOOP_INT_ST_V << RMT_CH0_TX_LOOP_INT_ST_S) 1361 #define RMT_CH0_TX_LOOP_INT_ST_V 0x00000001U 1362 #define RMT_CH0_TX_LOOP_INT_ST_S 16 1363 /** RMT_CH1_TX_LOOP_INT_ST : RO; bitpos: [17]; default: 0; 1364 * The masked interrupt status bit for RMT_CH1_TX_LOOP_INT. 1365 */ 1366 #define RMT_CH1_TX_LOOP_INT_ST (BIT(17)) 1367 #define RMT_CH1_TX_LOOP_INT_ST_M (RMT_CH1_TX_LOOP_INT_ST_V << RMT_CH1_TX_LOOP_INT_ST_S) 1368 #define RMT_CH1_TX_LOOP_INT_ST_V 0x00000001U 1369 #define RMT_CH1_TX_LOOP_INT_ST_S 17 1370 /** RMT_CH2_TX_LOOP_INT_ST : RO; bitpos: [18]; default: 0; 1371 * The masked interrupt status bit for RMT_CH2_TX_LOOP_INT. 1372 */ 1373 #define RMT_CH2_TX_LOOP_INT_ST (BIT(18)) 1374 #define RMT_CH2_TX_LOOP_INT_ST_M (RMT_CH2_TX_LOOP_INT_ST_V << RMT_CH2_TX_LOOP_INT_ST_S) 1375 #define RMT_CH2_TX_LOOP_INT_ST_V 0x00000001U 1376 #define RMT_CH2_TX_LOOP_INT_ST_S 18 1377 /** RMT_CH3_TX_LOOP_INT_ST : RO; bitpos: [19]; default: 0; 1378 * The masked interrupt status bit for RMT_CH3_TX_LOOP_INT. 1379 */ 1380 #define RMT_CH3_TX_LOOP_INT_ST (BIT(19)) 1381 #define RMT_CH3_TX_LOOP_INT_ST_M (RMT_CH3_TX_LOOP_INT_ST_V << RMT_CH3_TX_LOOP_INT_ST_S) 1382 #define RMT_CH3_TX_LOOP_INT_ST_V 0x00000001U 1383 #define RMT_CH3_TX_LOOP_INT_ST_S 19 1384 1385 /** RMT_INT_ENA_REG register 1386 * Interrupt enable register 1387 */ 1388 #define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x58) 1389 /** RMT_CH0_TX_END_INT_ENA : R/W; bitpos: [0]; default: 0; 1390 * The interrupt enabled bit for RMT_CH0_TX_END_INT. 1391 */ 1392 #define RMT_CH0_TX_END_INT_ENA (BIT(0)) 1393 #define RMT_CH0_TX_END_INT_ENA_M (RMT_CH0_TX_END_INT_ENA_V << RMT_CH0_TX_END_INT_ENA_S) 1394 #define RMT_CH0_TX_END_INT_ENA_V 0x00000001U 1395 #define RMT_CH0_TX_END_INT_ENA_S 0 1396 /** RMT_CH0_RX_END_INT_ENA : R/W; bitpos: [1]; default: 0; 1397 * The interrupt enabled bit for RMT_CH0_RX_END_INT. 1398 */ 1399 #define RMT_CH0_RX_END_INT_ENA (BIT(1)) 1400 #define RMT_CH0_RX_END_INT_ENA_M (RMT_CH0_RX_END_INT_ENA_V << RMT_CH0_RX_END_INT_ENA_S) 1401 #define RMT_CH0_RX_END_INT_ENA_V 0x00000001U 1402 #define RMT_CH0_RX_END_INT_ENA_S 1 1403 /** RMT_CH0_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; 1404 * The interrupt enabled bit for RMT_CH0_ERR_INT. 1405 */ 1406 #define RMT_CH0_ERR_INT_ENA (BIT(2)) 1407 #define RMT_CH0_ERR_INT_ENA_M (RMT_CH0_ERR_INT_ENA_V << RMT_CH0_ERR_INT_ENA_S) 1408 #define RMT_CH0_ERR_INT_ENA_V 0x00000001U 1409 #define RMT_CH0_ERR_INT_ENA_S 2 1410 /** RMT_CH1_TX_END_INT_ENA : R/W; bitpos: [3]; default: 0; 1411 * The interrupt enabled bit for RMT_CH1_TX_END_INT. 1412 */ 1413 #define RMT_CH1_TX_END_INT_ENA (BIT(3)) 1414 #define RMT_CH1_TX_END_INT_ENA_M (RMT_CH1_TX_END_INT_ENA_V << RMT_CH1_TX_END_INT_ENA_S) 1415 #define RMT_CH1_TX_END_INT_ENA_V 0x00000001U 1416 #define RMT_CH1_TX_END_INT_ENA_S 3 1417 /** RMT_CH1_RX_END_INT_ENA : R/W; bitpos: [4]; default: 0; 1418 * The interrupt enabled bit for RMT_CH1_RX_END_INT. 1419 */ 1420 #define RMT_CH1_RX_END_INT_ENA (BIT(4)) 1421 #define RMT_CH1_RX_END_INT_ENA_M (RMT_CH1_RX_END_INT_ENA_V << RMT_CH1_RX_END_INT_ENA_S) 1422 #define RMT_CH1_RX_END_INT_ENA_V 0x00000001U 1423 #define RMT_CH1_RX_END_INT_ENA_S 4 1424 /** RMT_CH1_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; 1425 * The interrupt enabled bit for RMT_CH1_ERR_INT. 1426 */ 1427 #define RMT_CH1_ERR_INT_ENA (BIT(5)) 1428 #define RMT_CH1_ERR_INT_ENA_M (RMT_CH1_ERR_INT_ENA_V << RMT_CH1_ERR_INT_ENA_S) 1429 #define RMT_CH1_ERR_INT_ENA_V 0x00000001U 1430 #define RMT_CH1_ERR_INT_ENA_S 5 1431 /** RMT_CH2_TX_END_INT_ENA : R/W; bitpos: [6]; default: 0; 1432 * The interrupt enabled bit for RMT_CH2_TX_END_INT. 1433 */ 1434 #define RMT_CH2_TX_END_INT_ENA (BIT(6)) 1435 #define RMT_CH2_TX_END_INT_ENA_M (RMT_CH2_TX_END_INT_ENA_V << RMT_CH2_TX_END_INT_ENA_S) 1436 #define RMT_CH2_TX_END_INT_ENA_V 0x00000001U 1437 #define RMT_CH2_TX_END_INT_ENA_S 6 1438 /** RMT_CH2_RX_END_INT_ENA : R/W; bitpos: [7]; default: 0; 1439 * The interrupt enabled bit for RMT_CH2_RX_END_INT. 1440 */ 1441 #define RMT_CH2_RX_END_INT_ENA (BIT(7)) 1442 #define RMT_CH2_RX_END_INT_ENA_M (RMT_CH2_RX_END_INT_ENA_V << RMT_CH2_RX_END_INT_ENA_S) 1443 #define RMT_CH2_RX_END_INT_ENA_V 0x00000001U 1444 #define RMT_CH2_RX_END_INT_ENA_S 7 1445 /** RMT_CH2_ERR_INT_ENA : R/W; bitpos: [8]; default: 0; 1446 * The interrupt enabled bit for RMT_CH2_ERR_INT. 1447 */ 1448 #define RMT_CH2_ERR_INT_ENA (BIT(8)) 1449 #define RMT_CH2_ERR_INT_ENA_M (RMT_CH2_ERR_INT_ENA_V << RMT_CH2_ERR_INT_ENA_S) 1450 #define RMT_CH2_ERR_INT_ENA_V 0x00000001U 1451 #define RMT_CH2_ERR_INT_ENA_S 8 1452 /** RMT_CH3_TX_END_INT_ENA : R/W; bitpos: [9]; default: 0; 1453 * The interrupt enabled bit for RMT_CH3_TX_END_INT. 1454 */ 1455 #define RMT_CH3_TX_END_INT_ENA (BIT(9)) 1456 #define RMT_CH3_TX_END_INT_ENA_M (RMT_CH3_TX_END_INT_ENA_V << RMT_CH3_TX_END_INT_ENA_S) 1457 #define RMT_CH3_TX_END_INT_ENA_V 0x00000001U 1458 #define RMT_CH3_TX_END_INT_ENA_S 9 1459 /** RMT_CH3_RX_END_INT_ENA : R/W; bitpos: [10]; default: 0; 1460 * The interrupt enabled bit for RMT_CH3_RX_END_INT. 1461 */ 1462 #define RMT_CH3_RX_END_INT_ENA (BIT(10)) 1463 #define RMT_CH3_RX_END_INT_ENA_M (RMT_CH3_RX_END_INT_ENA_V << RMT_CH3_RX_END_INT_ENA_S) 1464 #define RMT_CH3_RX_END_INT_ENA_V 0x00000001U 1465 #define RMT_CH3_RX_END_INT_ENA_S 10 1466 /** RMT_CH3_ERR_INT_ENA : R/W; bitpos: [11]; default: 0; 1467 * The interrupt enabled bit for RMT_CH3_ERR_INT. 1468 */ 1469 #define RMT_CH3_ERR_INT_ENA (BIT(11)) 1470 #define RMT_CH3_ERR_INT_ENA_M (RMT_CH3_ERR_INT_ENA_V << RMT_CH3_ERR_INT_ENA_S) 1471 #define RMT_CH3_ERR_INT_ENA_V 0x00000001U 1472 #define RMT_CH3_ERR_INT_ENA_S 11 1473 /** RMT_CH0_TX_THR_EVENT_INT_ENA : R/W; bitpos: [12]; default: 0; 1474 * The interrupt enabled bit for RMT_CH0_TX_THR_EVENT_INT. 1475 */ 1476 #define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(12)) 1477 #define RMT_CH0_TX_THR_EVENT_INT_ENA_M (RMT_CH0_TX_THR_EVENT_INT_ENA_V << RMT_CH0_TX_THR_EVENT_INT_ENA_S) 1478 #define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x00000001U 1479 #define RMT_CH0_TX_THR_EVENT_INT_ENA_S 12 1480 /** RMT_CH1_TX_THR_EVENT_INT_ENA : R/W; bitpos: [13]; default: 0; 1481 * The interrupt enabled bit for RMT_CH1_TX_THR_EVENT_INT. 1482 */ 1483 #define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(13)) 1484 #define RMT_CH1_TX_THR_EVENT_INT_ENA_M (RMT_CH1_TX_THR_EVENT_INT_ENA_V << RMT_CH1_TX_THR_EVENT_INT_ENA_S) 1485 #define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x00000001U 1486 #define RMT_CH1_TX_THR_EVENT_INT_ENA_S 13 1487 /** RMT_CH2_TX_THR_EVENT_INT_ENA : R/W; bitpos: [14]; default: 0; 1488 * The interrupt enabled bit for RMT_CH2_TX_THR_EVENT_INT. 1489 */ 1490 #define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(14)) 1491 #define RMT_CH2_TX_THR_EVENT_INT_ENA_M (RMT_CH2_TX_THR_EVENT_INT_ENA_V << RMT_CH2_TX_THR_EVENT_INT_ENA_S) 1492 #define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x00000001U 1493 #define RMT_CH2_TX_THR_EVENT_INT_ENA_S 14 1494 /** RMT_CH3_TX_THR_EVENT_INT_ENA : R/W; bitpos: [15]; default: 0; 1495 * The interrupt enabled bit for RMT_CH3_TX_THR_EVENT_INT. 1496 */ 1497 #define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(15)) 1498 #define RMT_CH3_TX_THR_EVENT_INT_ENA_M (RMT_CH3_TX_THR_EVENT_INT_ENA_V << RMT_CH3_TX_THR_EVENT_INT_ENA_S) 1499 #define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x00000001U 1500 #define RMT_CH3_TX_THR_EVENT_INT_ENA_S 15 1501 /** RMT_CH0_TX_LOOP_INT_ENA : R/W; bitpos: [16]; default: 0; 1502 * The interrupt enabled bit for RMT_CH0_TX_LOOP_INT. 1503 */ 1504 #define RMT_CH0_TX_LOOP_INT_ENA (BIT(16)) 1505 #define RMT_CH0_TX_LOOP_INT_ENA_M (RMT_CH0_TX_LOOP_INT_ENA_V << RMT_CH0_TX_LOOP_INT_ENA_S) 1506 #define RMT_CH0_TX_LOOP_INT_ENA_V 0x00000001U 1507 #define RMT_CH0_TX_LOOP_INT_ENA_S 16 1508 /** RMT_CH1_TX_LOOP_INT_ENA : R/W; bitpos: [17]; default: 0; 1509 * The interrupt enabled bit for RMT_CH1_TX_LOOP_INT. 1510 */ 1511 #define RMT_CH1_TX_LOOP_INT_ENA (BIT(17)) 1512 #define RMT_CH1_TX_LOOP_INT_ENA_M (RMT_CH1_TX_LOOP_INT_ENA_V << RMT_CH1_TX_LOOP_INT_ENA_S) 1513 #define RMT_CH1_TX_LOOP_INT_ENA_V 0x00000001U 1514 #define RMT_CH1_TX_LOOP_INT_ENA_S 17 1515 /** RMT_CH2_TX_LOOP_INT_ENA : R/W; bitpos: [18]; default: 0; 1516 * The interrupt enabled bit for RMT_CH2_TX_LOOP_INT. 1517 */ 1518 #define RMT_CH2_TX_LOOP_INT_ENA (BIT(18)) 1519 #define RMT_CH2_TX_LOOP_INT_ENA_M (RMT_CH2_TX_LOOP_INT_ENA_V << RMT_CH2_TX_LOOP_INT_ENA_S) 1520 #define RMT_CH2_TX_LOOP_INT_ENA_V 0x00000001U 1521 #define RMT_CH2_TX_LOOP_INT_ENA_S 18 1522 /** RMT_CH3_TX_LOOP_INT_ENA : R/W; bitpos: [19]; default: 0; 1523 * The interrupt enabled bit for RMT_CH3_TX_LOOP_INT. 1524 */ 1525 #define RMT_CH3_TX_LOOP_INT_ENA (BIT(19)) 1526 #define RMT_CH3_TX_LOOP_INT_ENA_M (RMT_CH3_TX_LOOP_INT_ENA_V << RMT_CH3_TX_LOOP_INT_ENA_S) 1527 #define RMT_CH3_TX_LOOP_INT_ENA_V 0x00000001U 1528 #define RMT_CH3_TX_LOOP_INT_ENA_S 19 1529 1530 /** RMT_INT_CLR_REG register 1531 * Interrupt clear register 1532 */ 1533 #define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x5c) 1534 /** RMT_CH0_TX_END_INT_CLR : WO; bitpos: [0]; default: 0; 1535 * Set this bit to clear RMT_CH0_TX_END_INT interrupt. 1536 */ 1537 #define RMT_CH0_TX_END_INT_CLR (BIT(0)) 1538 #define RMT_CH0_TX_END_INT_CLR_M (RMT_CH0_TX_END_INT_CLR_V << RMT_CH0_TX_END_INT_CLR_S) 1539 #define RMT_CH0_TX_END_INT_CLR_V 0x00000001U 1540 #define RMT_CH0_TX_END_INT_CLR_S 0 1541 /** RMT_CH0_RX_END_INT_CLR : WO; bitpos: [1]; default: 0; 1542 * Set this bit to clear RMT_CH0_RX_END_INT interrupt. 1543 */ 1544 #define RMT_CH0_RX_END_INT_CLR (BIT(1)) 1545 #define RMT_CH0_RX_END_INT_CLR_M (RMT_CH0_RX_END_INT_CLR_V << RMT_CH0_RX_END_INT_CLR_S) 1546 #define RMT_CH0_RX_END_INT_CLR_V 0x00000001U 1547 #define RMT_CH0_RX_END_INT_CLR_S 1 1548 /** RMT_CH0_ERR_INT_CLR : WO; bitpos: [2]; default: 0; 1549 * Set this bit to clear RMT_CH0_ERR_INT interrupt. 1550 */ 1551 #define RMT_CH0_ERR_INT_CLR (BIT(2)) 1552 #define RMT_CH0_ERR_INT_CLR_M (RMT_CH0_ERR_INT_CLR_V << RMT_CH0_ERR_INT_CLR_S) 1553 #define RMT_CH0_ERR_INT_CLR_V 0x00000001U 1554 #define RMT_CH0_ERR_INT_CLR_S 2 1555 /** RMT_CH1_TX_END_INT_CLR : WO; bitpos: [3]; default: 0; 1556 * Set this bit to clear RMT_CH1_TX_END_INT interrupt. 1557 */ 1558 #define RMT_CH1_TX_END_INT_CLR (BIT(3)) 1559 #define RMT_CH1_TX_END_INT_CLR_M (RMT_CH1_TX_END_INT_CLR_V << RMT_CH1_TX_END_INT_CLR_S) 1560 #define RMT_CH1_TX_END_INT_CLR_V 0x00000001U 1561 #define RMT_CH1_TX_END_INT_CLR_S 3 1562 /** RMT_CH1_RX_END_INT_CLR : WO; bitpos: [4]; default: 0; 1563 * Set this bit to clear RMT_CH1_RX_END_INT interrupt. 1564 */ 1565 #define RMT_CH1_RX_END_INT_CLR (BIT(4)) 1566 #define RMT_CH1_RX_END_INT_CLR_M (RMT_CH1_RX_END_INT_CLR_V << RMT_CH1_RX_END_INT_CLR_S) 1567 #define RMT_CH1_RX_END_INT_CLR_V 0x00000001U 1568 #define RMT_CH1_RX_END_INT_CLR_S 4 1569 /** RMT_CH1_ERR_INT_CLR : WO; bitpos: [5]; default: 0; 1570 * Set this bit to clear RMT_CH1_ERR_INT interrupt. 1571 */ 1572 #define RMT_CH1_ERR_INT_CLR (BIT(5)) 1573 #define RMT_CH1_ERR_INT_CLR_M (RMT_CH1_ERR_INT_CLR_V << RMT_CH1_ERR_INT_CLR_S) 1574 #define RMT_CH1_ERR_INT_CLR_V 0x00000001U 1575 #define RMT_CH1_ERR_INT_CLR_S 5 1576 /** RMT_CH2_TX_END_INT_CLR : WO; bitpos: [6]; default: 0; 1577 * Set this bit to clear RMT_CH2_TX_END_INT interrupt. 1578 */ 1579 #define RMT_CH2_TX_END_INT_CLR (BIT(6)) 1580 #define RMT_CH2_TX_END_INT_CLR_M (RMT_CH2_TX_END_INT_CLR_V << RMT_CH2_TX_END_INT_CLR_S) 1581 #define RMT_CH2_TX_END_INT_CLR_V 0x00000001U 1582 #define RMT_CH2_TX_END_INT_CLR_S 6 1583 /** RMT_CH2_RX_END_INT_CLR : WO; bitpos: [7]; default: 0; 1584 * Set this bit to clear RMT_CH2_RX_END_INT interrupt. 1585 */ 1586 #define RMT_CH2_RX_END_INT_CLR (BIT(7)) 1587 #define RMT_CH2_RX_END_INT_CLR_M (RMT_CH2_RX_END_INT_CLR_V << RMT_CH2_RX_END_INT_CLR_S) 1588 #define RMT_CH2_RX_END_INT_CLR_V 0x00000001U 1589 #define RMT_CH2_RX_END_INT_CLR_S 7 1590 /** RMT_CH2_ERR_INT_CLR : WO; bitpos: [8]; default: 0; 1591 * Set this bit to clear RMT_CH2_ERR_INT interrupt. 1592 */ 1593 #define RMT_CH2_ERR_INT_CLR (BIT(8)) 1594 #define RMT_CH2_ERR_INT_CLR_M (RMT_CH2_ERR_INT_CLR_V << RMT_CH2_ERR_INT_CLR_S) 1595 #define RMT_CH2_ERR_INT_CLR_V 0x00000001U 1596 #define RMT_CH2_ERR_INT_CLR_S 8 1597 /** RMT_CH3_TX_END_INT_CLR : WO; bitpos: [9]; default: 0; 1598 * Set this bit to clear RMT_CH3_TX_END_INT interrupt. 1599 */ 1600 #define RMT_CH3_TX_END_INT_CLR (BIT(9)) 1601 #define RMT_CH3_TX_END_INT_CLR_M (RMT_CH3_TX_END_INT_CLR_V << RMT_CH3_TX_END_INT_CLR_S) 1602 #define RMT_CH3_TX_END_INT_CLR_V 0x00000001U 1603 #define RMT_CH3_TX_END_INT_CLR_S 9 1604 /** RMT_CH3_RX_END_INT_CLR : WO; bitpos: [10]; default: 0; 1605 * Set this bit to clear RMT_CH3_RX_END_INT interrupt. 1606 */ 1607 #define RMT_CH3_RX_END_INT_CLR (BIT(10)) 1608 #define RMT_CH3_RX_END_INT_CLR_M (RMT_CH3_RX_END_INT_CLR_V << RMT_CH3_RX_END_INT_CLR_S) 1609 #define RMT_CH3_RX_END_INT_CLR_V 0x00000001U 1610 #define RMT_CH3_RX_END_INT_CLR_S 10 1611 /** RMT_CH3_ERR_INT_CLR : WO; bitpos: [11]; default: 0; 1612 * Set this bit to clear RMT_CH3_ERR_INT interrupt. 1613 */ 1614 #define RMT_CH3_ERR_INT_CLR (BIT(11)) 1615 #define RMT_CH3_ERR_INT_CLR_M (RMT_CH3_ERR_INT_CLR_V << RMT_CH3_ERR_INT_CLR_S) 1616 #define RMT_CH3_ERR_INT_CLR_V 0x00000001U 1617 #define RMT_CH3_ERR_INT_CLR_S 11 1618 /** RMT_CH0_TX_THR_EVENT_INT_CLR : WO; bitpos: [12]; default: 0; 1619 * Set this bit to clear RMT_CH0_TX_THR_EVENT_INT interrupt. 1620 */ 1621 #define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(12)) 1622 #define RMT_CH0_TX_THR_EVENT_INT_CLR_M (RMT_CH0_TX_THR_EVENT_INT_CLR_V << RMT_CH0_TX_THR_EVENT_INT_CLR_S) 1623 #define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x00000001U 1624 #define RMT_CH0_TX_THR_EVENT_INT_CLR_S 12 1625 /** RMT_CH1_TX_THR_EVENT_INT_CLR : WO; bitpos: [13]; default: 0; 1626 * Set this bit to clear RMT_CH1_TX_THR_EVENT_INT interrupt. 1627 */ 1628 #define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(13)) 1629 #define RMT_CH1_TX_THR_EVENT_INT_CLR_M (RMT_CH1_TX_THR_EVENT_INT_CLR_V << RMT_CH1_TX_THR_EVENT_INT_CLR_S) 1630 #define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x00000001U 1631 #define RMT_CH1_TX_THR_EVENT_INT_CLR_S 13 1632 /** RMT_CH2_TX_THR_EVENT_INT_CLR : WO; bitpos: [14]; default: 0; 1633 * Set this bit to clear RMT_CH2_TX_THR_EVENT_INT interrupt. 1634 */ 1635 #define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(14)) 1636 #define RMT_CH2_TX_THR_EVENT_INT_CLR_M (RMT_CH2_TX_THR_EVENT_INT_CLR_V << RMT_CH2_TX_THR_EVENT_INT_CLR_S) 1637 #define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x00000001U 1638 #define RMT_CH2_TX_THR_EVENT_INT_CLR_S 14 1639 /** RMT_CH3_TX_THR_EVENT_INT_CLR : WO; bitpos: [15]; default: 0; 1640 * Set this bit to clear RMT_CH3_TX_THR_EVENT_INT interrupt. 1641 */ 1642 #define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(15)) 1643 #define RMT_CH3_TX_THR_EVENT_INT_CLR_M (RMT_CH3_TX_THR_EVENT_INT_CLR_V << RMT_CH3_TX_THR_EVENT_INT_CLR_S) 1644 #define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x00000001U 1645 #define RMT_CH3_TX_THR_EVENT_INT_CLR_S 15 1646 /** RMT_CH0_TX_LOOP_INT_CLR : WO; bitpos: [16]; default: 0; 1647 * Set this bit to clear RMT_CH0_TX_LOOP_INT interrupt. 1648 */ 1649 #define RMT_CH0_TX_LOOP_INT_CLR (BIT(16)) 1650 #define RMT_CH0_TX_LOOP_INT_CLR_M (RMT_CH0_TX_LOOP_INT_CLR_V << RMT_CH0_TX_LOOP_INT_CLR_S) 1651 #define RMT_CH0_TX_LOOP_INT_CLR_V 0x00000001U 1652 #define RMT_CH0_TX_LOOP_INT_CLR_S 16 1653 /** RMT_CH1_TX_LOOP_INT_CLR : WO; bitpos: [17]; default: 0; 1654 * Set this bit to clear RMT_CH1_TX_LOOP_INT interrupt. 1655 */ 1656 #define RMT_CH1_TX_LOOP_INT_CLR (BIT(17)) 1657 #define RMT_CH1_TX_LOOP_INT_CLR_M (RMT_CH1_TX_LOOP_INT_CLR_V << RMT_CH1_TX_LOOP_INT_CLR_S) 1658 #define RMT_CH1_TX_LOOP_INT_CLR_V 0x00000001U 1659 #define RMT_CH1_TX_LOOP_INT_CLR_S 17 1660 /** RMT_CH2_TX_LOOP_INT_CLR : WO; bitpos: [18]; default: 0; 1661 * Set this bit to clear RMT_CH2_TX_LOOP_INT interrupt. 1662 */ 1663 #define RMT_CH2_TX_LOOP_INT_CLR (BIT(18)) 1664 #define RMT_CH2_TX_LOOP_INT_CLR_M (RMT_CH2_TX_LOOP_INT_CLR_V << RMT_CH2_TX_LOOP_INT_CLR_S) 1665 #define RMT_CH2_TX_LOOP_INT_CLR_V 0x00000001U 1666 #define RMT_CH2_TX_LOOP_INT_CLR_S 18 1667 /** RMT_CH3_TX_LOOP_INT_CLR : WO; bitpos: [19]; default: 0; 1668 * Set this bit to clear RMT_CH3_TX_LOOP_INT interrupt. 1669 */ 1670 #define RMT_CH3_TX_LOOP_INT_CLR (BIT(19)) 1671 #define RMT_CH3_TX_LOOP_INT_CLR_M (RMT_CH3_TX_LOOP_INT_CLR_V << RMT_CH3_TX_LOOP_INT_CLR_S) 1672 #define RMT_CH3_TX_LOOP_INT_CLR_V 0x00000001U 1673 #define RMT_CH3_TX_LOOP_INT_CLR_S 19 1674 1675 /** RMT_CH0CARRIER_DUTY_REG register 1676 * Channel 0 duty cycle configuration register 1677 */ 1678 #define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x60) 1679 /** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64; 1680 * This field is used to configure the clock cycles of carrier wave at low level for 1681 * channel 0. 1682 */ 1683 #define RMT_CARRIER_LOW_CH0 0x0000FFFFU 1684 #define RMT_CARRIER_LOW_CH0_M (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S) 1685 #define RMT_CARRIER_LOW_CH0_V 0x0000FFFFU 1686 #define RMT_CARRIER_LOW_CH0_S 0 1687 /** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64; 1688 * This field is used to configure the clock cycles of carrier wave at high level for 1689 * channel 0. 1690 */ 1691 #define RMT_CARRIER_HIGH_CH0 0x0000FFFFU 1692 #define RMT_CARRIER_HIGH_CH0_M (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S) 1693 #define RMT_CARRIER_HIGH_CH0_V 0x0000FFFFU 1694 #define RMT_CARRIER_HIGH_CH0_S 16 1695 1696 /** RMT_CH1CARRIER_DUTY_REG register 1697 * Channel 1 duty cycle configuration register 1698 */ 1699 #define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x64) 1700 /** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64; 1701 * This field is used to configure the clock cycles of carrier wave at low level for 1702 * channel 1. 1703 */ 1704 #define RMT_CARRIER_LOW_CH0 0x0000FFFFU 1705 #define RMT_CARRIER_LOW_CH0_M (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S) 1706 #define RMT_CARRIER_LOW_CH0_V 0x0000FFFFU 1707 #define RMT_CARRIER_LOW_CH0_S 0 1708 /** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64; 1709 * This field is used to configure the clock cycles of carrier wave at high level for 1710 * channel 1. 1711 */ 1712 #define RMT_CARRIER_HIGH_CH0 0x0000FFFFU 1713 #define RMT_CARRIER_HIGH_CH0_M (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S) 1714 #define RMT_CARRIER_HIGH_CH0_V 0x0000FFFFU 1715 #define RMT_CARRIER_HIGH_CH0_S 16 1716 1717 /** RMT_CH2CARRIER_DUTY_REG register 1718 * Channel 2 duty cycle configuration register 1719 */ 1720 #define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x68) 1721 /** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64; 1722 * This field is used to configure the clock cycles of carrier wave at low level for 1723 * channel 2. 1724 */ 1725 #define RMT_CARRIER_LOW_CH0 0x0000FFFFU 1726 #define RMT_CARRIER_LOW_CH0_M (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S) 1727 #define RMT_CARRIER_LOW_CH0_V 0x0000FFFFU 1728 #define RMT_CARRIER_LOW_CH0_S 0 1729 /** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64; 1730 * This field is used to configure the clock cycles of carrier wave at high level for 1731 * channel 2. 1732 */ 1733 #define RMT_CARRIER_HIGH_CH0 0x0000FFFFU 1734 #define RMT_CARRIER_HIGH_CH0_M (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S) 1735 #define RMT_CARRIER_HIGH_CH0_V 0x0000FFFFU 1736 #define RMT_CARRIER_HIGH_CH0_S 16 1737 1738 /** RMT_CH3CARRIER_DUTY_REG register 1739 * Channel 3 duty cycle configuration register 1740 */ 1741 #define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x6c) 1742 /** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64; 1743 * This field is used to configure the clock cycles of carrier wave at low level for 1744 * channel 3. 1745 */ 1746 #define RMT_CARRIER_LOW_CH0 0x0000FFFFU 1747 #define RMT_CARRIER_LOW_CH0_M (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S) 1748 #define RMT_CARRIER_LOW_CH0_V 0x0000FFFFU 1749 #define RMT_CARRIER_LOW_CH0_S 0 1750 /** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64; 1751 * This field is used to configure the clock cycles of carrier wave at high level for 1752 * channel 3. 1753 */ 1754 #define RMT_CARRIER_HIGH_CH0 0x0000FFFFU 1755 #define RMT_CARRIER_HIGH_CH0_M (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S) 1756 #define RMT_CARRIER_HIGH_CH0_V 0x0000FFFFU 1757 #define RMT_CARRIER_HIGH_CH0_S 16 1758 1759 /** RMT_CH0_TX_LIM_REG register 1760 * Channel 0 Tx event configuration register 1761 */ 1762 #define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x70) 1763 /** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128; 1764 * This field is used to configure the maximum entries that channel 0 can send out. 1765 * When RMT_MEM_SIZE_CH0 = 1, this field can be set to any value among 0 ~ 128 1766 * (64*32/16 = 128). When RMT_MEM_SIZE_CH0 > 1, this field can be set to any value 1767 * among (0 ~ 128)*RMT_MEM_SIZE_CH0. 1768 */ 1769 #define RMT_TX_LIM_CH0 0x000001FFU 1770 #define RMT_TX_LIM_CH0_M (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S) 1771 #define RMT_TX_LIM_CH0_V 0x000001FFU 1772 #define RMT_TX_LIM_CH0_S 0 1773 /** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0; 1774 * This field is used to configure the maximum loop times when continuous transmission 1775 * mode is enabled. 1776 */ 1777 #define RMT_TX_LOOP_NUM_CH0 0x000003FFU 1778 #define RMT_TX_LOOP_NUM_CH0_M (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S) 1779 #define RMT_TX_LOOP_NUM_CH0_V 0x000003FFU 1780 #define RMT_TX_LOOP_NUM_CH0_S 9 1781 /** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0; 1782 * This bit is used to enable loop counting. 1783 */ 1784 #define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) 1785 #define RMT_TX_LOOP_CNT_EN_CH0_M (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S) 1786 #define RMT_TX_LOOP_CNT_EN_CH0_V 0x00000001U 1787 #define RMT_TX_LOOP_CNT_EN_CH0_S 19 1788 /** RMT_LOOP_COUNT_RESET_CH0 : WO; bitpos: [20]; default: 0; 1789 * This bit is used to reset loop counting when continuous transmission mode is valid. 1790 */ 1791 #define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) 1792 #define RMT_LOOP_COUNT_RESET_CH0_M (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S) 1793 #define RMT_LOOP_COUNT_RESET_CH0_V 0x00000001U 1794 #define RMT_LOOP_COUNT_RESET_CH0_S 20 1795 1796 /** RMT_CH1_TX_LIM_REG register 1797 * Channel 1 Tx event configuration register 1798 */ 1799 #define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x74) 1800 /** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128; 1801 * This field is used to configure the maximum entries that channel 1 can send out. 1802 * When RMT_MEM_SIZE_CH1 = 1, this field can be set to any value among 0 ~ 128 1803 * (64*32/16 = 128). When RMT_MEM_SIZE_CH1 > 1, this field can be set to any value 1804 * among (0 ~ 128)*RMT_MEM_SIZE_CH1. 1805 */ 1806 #define RMT_TX_LIM_CH0 0x000001FFU 1807 #define RMT_TX_LIM_CH0_M (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S) 1808 #define RMT_TX_LIM_CH0_V 0x000001FFU 1809 #define RMT_TX_LIM_CH0_S 0 1810 /** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0; 1811 * This field is used to configure the maximum loop times when continuous transmission 1812 * mode is enabled. 1813 */ 1814 #define RMT_TX_LOOP_NUM_CH0 0x000003FFU 1815 #define RMT_TX_LOOP_NUM_CH0_M (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S) 1816 #define RMT_TX_LOOP_NUM_CH0_V 0x000003FFU 1817 #define RMT_TX_LOOP_NUM_CH0_S 9 1818 /** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0; 1819 * This bit is used to enable loop counting. 1820 */ 1821 #define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) 1822 #define RMT_TX_LOOP_CNT_EN_CH0_M (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S) 1823 #define RMT_TX_LOOP_CNT_EN_CH0_V 0x00000001U 1824 #define RMT_TX_LOOP_CNT_EN_CH0_S 19 1825 /** RMT_LOOP_COUNT_RESET_CH0 : WO; bitpos: [20]; default: 0; 1826 * This bit is used to reset loop counting when continuous transmission mode is valid. 1827 */ 1828 #define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) 1829 #define RMT_LOOP_COUNT_RESET_CH0_M (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S) 1830 #define RMT_LOOP_COUNT_RESET_CH0_V 0x00000001U 1831 #define RMT_LOOP_COUNT_RESET_CH0_S 20 1832 1833 /** RMT_CH2_TX_LIM_REG register 1834 * Channel 2 Tx event configuration register 1835 */ 1836 #define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x78) 1837 /** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128; 1838 * This field is used to configure the maximum entries that channel 2 can send out. 1839 * When RMT_MEM_SIZE_CH2 = 1, this field can be set to any value among 0 ~ 128 1840 * (64*32/16 = 128). When RMT_MEM_SIZE_CH2 > 1, this field can be set to any value 1841 * among (0 ~ 128)*RMT_MEM_SIZE_CH2. 1842 */ 1843 #define RMT_TX_LIM_CH0 0x000001FFU 1844 #define RMT_TX_LIM_CH0_M (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S) 1845 #define RMT_TX_LIM_CH0_V 0x000001FFU 1846 #define RMT_TX_LIM_CH0_S 0 1847 /** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0; 1848 * This field is used to configure the maximum loop times when continuous transmission 1849 * mode is enabled. 1850 */ 1851 #define RMT_TX_LOOP_NUM_CH0 0x000003FFU 1852 #define RMT_TX_LOOP_NUM_CH0_M (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S) 1853 #define RMT_TX_LOOP_NUM_CH0_V 0x000003FFU 1854 #define RMT_TX_LOOP_NUM_CH0_S 9 1855 /** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0; 1856 * This bit is used to enable loop counting. 1857 */ 1858 #define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) 1859 #define RMT_TX_LOOP_CNT_EN_CH0_M (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S) 1860 #define RMT_TX_LOOP_CNT_EN_CH0_V 0x00000001U 1861 #define RMT_TX_LOOP_CNT_EN_CH0_S 19 1862 /** RMT_LOOP_COUNT_RESET_CH0 : WO; bitpos: [20]; default: 0; 1863 * This bit is used to reset loop counting when continuous transmission mode is valid. 1864 */ 1865 #define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) 1866 #define RMT_LOOP_COUNT_RESET_CH0_M (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S) 1867 #define RMT_LOOP_COUNT_RESET_CH0_V 0x00000001U 1868 #define RMT_LOOP_COUNT_RESET_CH0_S 20 1869 1870 /** RMT_CH3_TX_LIM_REG register 1871 * Channel 3 Tx event configuration register 1872 */ 1873 #define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x7c) 1874 /** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128; 1875 * This field is used to configure the maximum entries that channel 3 can send out. 1876 * When RMT_MEM_SIZE_CH3 = 1, this field can be set to any value among 0 ~ 128 1877 * (64*32/16 = 128). When RMT_MEM_SIZE_CH3 > 1, this field can be set to any value 1878 * among (0 ~ 128)*RMT_MEM_SIZE_CH3. 1879 */ 1880 #define RMT_TX_LIM_CH0 0x000001FFU 1881 #define RMT_TX_LIM_CH0_M (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S) 1882 #define RMT_TX_LIM_CH0_V 0x000001FFU 1883 #define RMT_TX_LIM_CH0_S 0 1884 /** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0; 1885 * This field is used to configure the maximum loop times when continuous transmission 1886 * mode is enabled. 1887 */ 1888 #define RMT_TX_LOOP_NUM_CH0 0x000003FFU 1889 #define RMT_TX_LOOP_NUM_CH0_M (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S) 1890 #define RMT_TX_LOOP_NUM_CH0_V 0x000003FFU 1891 #define RMT_TX_LOOP_NUM_CH0_S 9 1892 /** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0; 1893 * This bit is used to enable loop counting. 1894 */ 1895 #define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) 1896 #define RMT_TX_LOOP_CNT_EN_CH0_M (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S) 1897 #define RMT_TX_LOOP_CNT_EN_CH0_V 0x00000001U 1898 #define RMT_TX_LOOP_CNT_EN_CH0_S 19 1899 /** RMT_LOOP_COUNT_RESET_CH0 : WO; bitpos: [20]; default: 0; 1900 * This bit is used to reset loop counting when continuous transmission mode is valid. 1901 */ 1902 #define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) 1903 #define RMT_LOOP_COUNT_RESET_CH0_M (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S) 1904 #define RMT_LOOP_COUNT_RESET_CH0_V 0x00000001U 1905 #define RMT_LOOP_COUNT_RESET_CH0_S 20 1906 1907 /** RMT_APB_CONF_REG register 1908 * RMT APB configuration register 1909 */ 1910 #define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x80) 1911 /** RMT_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0; 1912 * 1'h1: Access memory directly. 1'h0: access memory via APB FIFO. 1913 */ 1914 #define RMT_APB_FIFO_MASK (BIT(0)) 1915 #define RMT_APB_FIFO_MASK_M (RMT_APB_FIFO_MASK_V << RMT_APB_FIFO_MASK_S) 1916 #define RMT_APB_FIFO_MASK_V 0x00000001U 1917 #define RMT_APB_FIFO_MASK_S 0 1918 /** RMT_MEM_TX_WRAP_EN : R/W; bitpos: [1]; default: 0; 1919 * Set this bit to enable wrap mode. 1920 */ 1921 #define RMT_MEM_TX_WRAP_EN (BIT(1)) 1922 #define RMT_MEM_TX_WRAP_EN_M (RMT_MEM_TX_WRAP_EN_V << RMT_MEM_TX_WRAP_EN_S) 1923 #define RMT_MEM_TX_WRAP_EN_V 0x00000001U 1924 #define RMT_MEM_TX_WRAP_EN_S 1 1925 /** RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [2]; default: 1; 1926 * Set this bit to enable the clock for RAM when RMT module starts working, disable 1927 * this clock when RMT stops working, to achieve low-power scheme. 1928 */ 1929 #define RMT_MEM_CLK_FORCE_ON (BIT(2)) 1930 #define RMT_MEM_CLK_FORCE_ON_M (RMT_MEM_CLK_FORCE_ON_V << RMT_MEM_CLK_FORCE_ON_S) 1931 #define RMT_MEM_CLK_FORCE_ON_V 0x00000001U 1932 #define RMT_MEM_CLK_FORCE_ON_S 2 1933 /** RMT_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; 1934 * Set this bit to power down RMT memory. 1935 */ 1936 #define RMT_MEM_FORCE_PD (BIT(3)) 1937 #define RMT_MEM_FORCE_PD_M (RMT_MEM_FORCE_PD_V << RMT_MEM_FORCE_PD_S) 1938 #define RMT_MEM_FORCE_PD_V 0x00000001U 1939 #define RMT_MEM_FORCE_PD_S 3 1940 /** RMT_MEM_FORCE_PU : R/W; bitpos: [4]; default: 0; 1941 * 1: Disable RAM's Light-sleep power down function. 0: power down RMT RAM when RMT is 1942 * in Light-sleep mode. 1943 */ 1944 #define RMT_MEM_FORCE_PU (BIT(4)) 1945 #define RMT_MEM_FORCE_PU_M (RMT_MEM_FORCE_PU_V << RMT_MEM_FORCE_PU_S) 1946 #define RMT_MEM_FORCE_PU_V 0x00000001U 1947 #define RMT_MEM_FORCE_PU_S 4 1948 /** RMT_CLK_EN : R/W; bitpos: [31]; default: 0; 1949 * Clock gating enable bit for RMT registers to achieve low-power scheme. 1: Power up 1950 * drive clock for RMT registers. 0: Power down drive clock for RMT registers. 1951 */ 1952 #define RMT_CLK_EN (BIT(31)) 1953 #define RMT_CLK_EN_M (RMT_CLK_EN_V << RMT_CLK_EN_S) 1954 #define RMT_CLK_EN_V 0x00000001U 1955 #define RMT_CLK_EN_S 31 1956 1957 /** RMT_TX_SIM_REG register 1958 * Enable RMT simultaneous transmission 1959 */ 1960 #define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0x84) 1961 /** RMT_TX_SIM_CH0 : R/W; bitpos: [0]; default: 0; 1962 * Set this bit to enable channel 0 to start sending data simultaneously with other 1963 * enabled channels. 1964 */ 1965 #define RMT_TX_SIM_CH0 (BIT(0)) 1966 #define RMT_TX_SIM_CH0_M (RMT_TX_SIM_CH0_V << RMT_TX_SIM_CH0_S) 1967 #define RMT_TX_SIM_CH0_V 0x00000001U 1968 #define RMT_TX_SIM_CH0_S 0 1969 /** RMT_TX_SIM_CH1 : R/W; bitpos: [1]; default: 0; 1970 * Set this bit to enable channel 1 to start sending data simultaneously with other 1971 * enabled channels. 1972 */ 1973 #define RMT_TX_SIM_CH1 (BIT(1)) 1974 #define RMT_TX_SIM_CH1_M (RMT_TX_SIM_CH1_V << RMT_TX_SIM_CH1_S) 1975 #define RMT_TX_SIM_CH1_V 0x00000001U 1976 #define RMT_TX_SIM_CH1_S 1 1977 /** RMT_TX_SIM_CH2 : R/W; bitpos: [2]; default: 0; 1978 * Set this bit to enable channel 2 to start sending data simultaneously with other 1979 * enabled channels. 1980 */ 1981 #define RMT_TX_SIM_CH2 (BIT(2)) 1982 #define RMT_TX_SIM_CH2_M (RMT_TX_SIM_CH2_V << RMT_TX_SIM_CH2_S) 1983 #define RMT_TX_SIM_CH2_V 0x00000001U 1984 #define RMT_TX_SIM_CH2_S 2 1985 /** RMT_TX_SIM_CH3 : R/W; bitpos: [3]; default: 0; 1986 * Set this bit to enable channel 3 to start sending data simultaneously with other 1987 * enabled channels. 1988 */ 1989 #define RMT_TX_SIM_CH3 (BIT(3)) 1990 #define RMT_TX_SIM_CH3_M (RMT_TX_SIM_CH3_V << RMT_TX_SIM_CH3_S) 1991 #define RMT_TX_SIM_CH3_V 0x00000001U 1992 #define RMT_TX_SIM_CH3_S 3 1993 /** RMT_TX_SIM_EN : R/W; bitpos: [4]; default: 0; 1994 * This bit is used to enable multiple channels to start sending data simultaneously. 1995 */ 1996 #define RMT_TX_SIM_EN (BIT(4)) 1997 #define RMT_TX_SIM_EN_M (RMT_TX_SIM_EN_V << RMT_TX_SIM_EN_S) 1998 #define RMT_TX_SIM_EN_V 0x00000001U 1999 #define RMT_TX_SIM_EN_S 4 2000 2001 /** RMT_REF_CNT_RST_REG register 2002 * RMT clock divider reset register 2003 */ 2004 #define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0x88) 2005 /** RMT_REF_CNT_RST_CH0 : R/W; bitpos: [0]; default: 0; 2006 * This bit is used to reset the clock divider of channel 0. 2007 */ 2008 #define RMT_REF_CNT_RST_CH0 (BIT(0)) 2009 #define RMT_REF_CNT_RST_CH0_M (RMT_REF_CNT_RST_CH0_V << RMT_REF_CNT_RST_CH0_S) 2010 #define RMT_REF_CNT_RST_CH0_V 0x00000001U 2011 #define RMT_REF_CNT_RST_CH0_S 0 2012 /** RMT_REF_CNT_RST_CH1 : R/W; bitpos: [1]; default: 0; 2013 * This bit is used to reset the clock divider of channel 1. 2014 */ 2015 #define RMT_REF_CNT_RST_CH1 (BIT(1)) 2016 #define RMT_REF_CNT_RST_CH1_M (RMT_REF_CNT_RST_CH1_V << RMT_REF_CNT_RST_CH1_S) 2017 #define RMT_REF_CNT_RST_CH1_V 0x00000001U 2018 #define RMT_REF_CNT_RST_CH1_S 1 2019 /** RMT_REF_CNT_RST_CH2 : R/W; bitpos: [2]; default: 0; 2020 * This bit is used to reset the clock divider of channel 2. 2021 */ 2022 #define RMT_REF_CNT_RST_CH2 (BIT(2)) 2023 #define RMT_REF_CNT_RST_CH2_M (RMT_REF_CNT_RST_CH2_V << RMT_REF_CNT_RST_CH2_S) 2024 #define RMT_REF_CNT_RST_CH2_V 0x00000001U 2025 #define RMT_REF_CNT_RST_CH2_S 2 2026 /** RMT_REF_CNT_RST_CH3 : R/W; bitpos: [3]; default: 0; 2027 * This bit is used to reset the clock divider of channel 3. 2028 */ 2029 #define RMT_REF_CNT_RST_CH3 (BIT(3)) 2030 #define RMT_REF_CNT_RST_CH3_M (RMT_REF_CNT_RST_CH3_V << RMT_REF_CNT_RST_CH3_S) 2031 #define RMT_REF_CNT_RST_CH3_V 0x00000001U 2032 #define RMT_REF_CNT_RST_CH3_S 3 2033 2034 /** RMT_CH0_RX_CARRIER_RM_REG register 2035 * Channel 0 carrier remove register 2036 */ 2037 #define RMT_CH0_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x8c) 2038 /** RMT_CARRIER_LOW_THRES_CH0 : R/W; bitpos: [15:0]; default: 0; 2039 * The low level period in carrier modulation mode is (RMT_CARRIER_LOW_THRES_CH0 + 1) 2040 * clock cycles for channel 0. 2041 */ 2042 #define RMT_CARRIER_LOW_THRES_CH0 0x0000FFFFU 2043 #define RMT_CARRIER_LOW_THRES_CH0_M (RMT_CARRIER_LOW_THRES_CH0_V << RMT_CARRIER_LOW_THRES_CH0_S) 2044 #define RMT_CARRIER_LOW_THRES_CH0_V 0x0000FFFFU 2045 #define RMT_CARRIER_LOW_THRES_CH0_S 0 2046 /** RMT_CARRIER_HIGH_THRES_CH0 : R/W; bitpos: [31:16]; default: 0; 2047 * The high level period in carrier modulation mode is (RMT_CARRIER_HIGH_THRES_CH0 + 2048 * 1) clock cycles for channel 0. 2049 */ 2050 #define RMT_CARRIER_HIGH_THRES_CH0 0x0000FFFFU 2051 #define RMT_CARRIER_HIGH_THRES_CH0_M (RMT_CARRIER_HIGH_THRES_CH0_V << RMT_CARRIER_HIGH_THRES_CH0_S) 2052 #define RMT_CARRIER_HIGH_THRES_CH0_V 0x0000FFFFU 2053 #define RMT_CARRIER_HIGH_THRES_CH0_S 16 2054 2055 /** RMT_CH1_RX_CARRIER_RM_REG register 2056 * Channel 1 carrier remove register 2057 */ 2058 #define RMT_CH1_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x90) 2059 /** RMT_CARRIER_LOW_THRES_CH0 : R/W; bitpos: [15:0]; default: 0; 2060 * The low level period in carrier modulation mode is (RMT_CARRIER_LOW_THRES_CH1 + 1) 2061 * clock cycles for channel 1. 2062 */ 2063 #define RMT_CARRIER_LOW_THRES_CH0 0x0000FFFFU 2064 #define RMT_CARRIER_LOW_THRES_CH0_M (RMT_CARRIER_LOW_THRES_CH0_V << RMT_CARRIER_LOW_THRES_CH0_S) 2065 #define RMT_CARRIER_LOW_THRES_CH0_V 0x0000FFFFU 2066 #define RMT_CARRIER_LOW_THRES_CH0_S 0 2067 /** RMT_CARRIER_HIGH_THRES_CH0 : R/W; bitpos: [31:16]; default: 0; 2068 * The high level period in carrier modulation mode is (RMT_CARRIER_HIGH_THRES_CH1 + 2069 * 1) clock cycles for channel 1. 2070 */ 2071 #define RMT_CARRIER_HIGH_THRES_CH0 0x0000FFFFU 2072 #define RMT_CARRIER_HIGH_THRES_CH0_M (RMT_CARRIER_HIGH_THRES_CH0_V << RMT_CARRIER_HIGH_THRES_CH0_S) 2073 #define RMT_CARRIER_HIGH_THRES_CH0_V 0x0000FFFFU 2074 #define RMT_CARRIER_HIGH_THRES_CH0_S 16 2075 2076 /** RMT_CH2_RX_CARRIER_RM_REG register 2077 * Channel 2 carrier remove register 2078 */ 2079 #define RMT_CH2_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x94) 2080 /** RMT_CARRIER_LOW_THRES_CH0 : R/W; bitpos: [15:0]; default: 0; 2081 * The low level period in carrier modulation mode is (RMT_CARRIER_LOW_THRES_CH2 + 1) 2082 * clock cycles for channel 2. 2083 */ 2084 #define RMT_CARRIER_LOW_THRES_CH0 0x0000FFFFU 2085 #define RMT_CARRIER_LOW_THRES_CH0_M (RMT_CARRIER_LOW_THRES_CH0_V << RMT_CARRIER_LOW_THRES_CH0_S) 2086 #define RMT_CARRIER_LOW_THRES_CH0_V 0x0000FFFFU 2087 #define RMT_CARRIER_LOW_THRES_CH0_S 0 2088 /** RMT_CARRIER_HIGH_THRES_CH0 : R/W; bitpos: [31:16]; default: 0; 2089 * The high level period in carrier modulation mode is (RMT_CARRIER_HIGH_THRES_CH2 + 2090 * 1) clock cycles for channel 2. 2091 */ 2092 #define RMT_CARRIER_HIGH_THRES_CH0 0x0000FFFFU 2093 #define RMT_CARRIER_HIGH_THRES_CH0_M (RMT_CARRIER_HIGH_THRES_CH0_V << RMT_CARRIER_HIGH_THRES_CH0_S) 2094 #define RMT_CARRIER_HIGH_THRES_CH0_V 0x0000FFFFU 2095 #define RMT_CARRIER_HIGH_THRES_CH0_S 16 2096 2097 /** RMT_CH3_RX_CARRIER_RM_REG register 2098 * Channel 3 carrier remove register 2099 */ 2100 #define RMT_CH3_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x98) 2101 /** RMT_CARRIER_LOW_THRES_CH0 : R/W; bitpos: [15:0]; default: 0; 2102 * The low level period in carrier modulation mode is (RMT_CARRIER_LOW_THRES_CH3 + 1) 2103 * clock cycles for channel 3. 2104 */ 2105 #define RMT_CARRIER_LOW_THRES_CH0 0x0000FFFFU 2106 #define RMT_CARRIER_LOW_THRES_CH0_M (RMT_CARRIER_LOW_THRES_CH0_V << RMT_CARRIER_LOW_THRES_CH0_S) 2107 #define RMT_CARRIER_LOW_THRES_CH0_V 0x0000FFFFU 2108 #define RMT_CARRIER_LOW_THRES_CH0_S 0 2109 /** RMT_CARRIER_HIGH_THRES_CH0 : R/W; bitpos: [31:16]; default: 0; 2110 * The high level period in carrier modulation mode is (RMT_CARRIER_HIGH_THRES_CH3 + 2111 * 1) clock cycles for channel 3. 2112 */ 2113 #define RMT_CARRIER_HIGH_THRES_CH0 0x0000FFFFU 2114 #define RMT_CARRIER_HIGH_THRES_CH0_M (RMT_CARRIER_HIGH_THRES_CH0_V << RMT_CARRIER_HIGH_THRES_CH0_S) 2115 #define RMT_CARRIER_HIGH_THRES_CH0_V 0x0000FFFFU 2116 #define RMT_CARRIER_HIGH_THRES_CH0_S 16 2117 2118 /** RMT_DATE_REG register 2119 * Version control register 2120 */ 2121 #define RMT_DATE_REG (DR_REG_RMT_BASE + 0xfc) 2122 /** RMT_DATE : R/W; bitpos: [31:0]; default: 419898881; 2123 * Version control register 2124 */ 2125 #define RMT_DATE 0xFFFFFFFFU 2126 #define RMT_DATE_M (RMT_DATE_V << RMT_DATE_S) 2127 #define RMT_DATE_V 0xFFFFFFFFU 2128 #define RMT_DATE_S 0 2129 2130 #ifdef __cplusplus 2131 } 2132 #endif 2133
