1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_SPI_MEM_STRUCT_H_ 15 #define _SOC_SPI_MEM_STRUCT_H_ 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 typedef volatile struct spi_mem_dev_s { 21 union { 22 struct { 23 uint32_t mst_st: 4; /*The current status of SPI1 master FSM.*/ 24 uint32_t st: 4; /*The current status of SPI1 slave FSM: mspi_st. 0: idle state 1: preparation state 2: send command state 3: send address state 4: wait state 5: read data state 6:write data state 7: done state 8: read data end state.*/ 25 uint32_t reserved8: 9; /*reserved*/ 26 uint32_t flash_pe: 1; /*In user mode it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/ 27 uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 28 uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/ 29 uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ 30 uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 31 uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 32 uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 33 uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 34 uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ 35 uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 36 uint32_t flash_rdsr: 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 37 uint32_t flash_rdid: 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ 38 uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ 39 uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ 40 uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ 41 }; 42 uint32_t val; 43 } cmd; 44 uint32_t addr; /*SPI1 address register*/ 45 union { 46 struct { 47 uint32_t reserved0: 3; /*reserved*/ 48 uint32_t fdummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/ 49 uint32_t reserved4: 3; /*reserved*/ 50 uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/ 51 uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/ 52 uint32_t reserved9: 1; /*reserved*/ 53 uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/ 54 uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ 55 uint32_t reserved12: 1; /*reserved*/ 56 uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/ 57 uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ 58 uint32_t resandres: 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/ 59 uint32_t reserved16: 2; /*reserved*/ 60 uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low*/ 61 uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/ 62 uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ 63 uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ 64 uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/ 65 uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/ 66 uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/ 67 uint32_t reserved25: 7; /*reserved*/ 68 }; 69 uint32_t val; 70 } ctrl; 71 union { 72 struct { 73 uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ 74 uint32_t cs_hold_dly_res: 10; /*After RES/DP/HPM command is sent SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/ 75 uint32_t reserved2: 18; /*reserved*/ 76 uint32_t rxfifo_rst: 1; /*SPI0 RX FIFO reset signal.*/ 77 uint32_t rxfifo_wfull_err: 1; /*1: SPI0 RX FIFO write full error Cache/EDMA do not read all the data out. 0: Not error.*/ 78 }; 79 uint32_t val; 80 } ctrl1; 81 union { 82 struct { 83 uint32_t cs_setup_time: 5; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/ 84 uint32_t cs_hold_time: 5; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/ 85 uint32_t reserved10: 15; /*reserved*/ 86 uint32_t cs_hold_delay: 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ 87 uint32_t sync_reset: 1; /*The FSM will be reset.*/ 88 }; 89 uint32_t val; 90 } ctrl2; 91 union { 92 struct { 93 uint32_t clkcnt_l: 8; /*In the master mode it must be equal to spi_mem_clkcnt_N.*/ 94 uint32_t clkcnt_h: 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ 95 uint32_t clkcnt_n: 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ 96 uint32_t reserved24: 7; /*reserved*/ 97 uint32_t clk_equ_sysclk: 1; /*Set this bit in 1-division mode.*/ 98 }; 99 uint32_t val; 100 } clock; 101 union { 102 struct { 103 uint32_t reserved0: 6; /*reserved*/ 104 uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ 105 uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ 106 uint32_t reserved8: 1; /*reserved*/ 107 uint32_t ck_out_edge: 1; /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/ 108 uint32_t reserved10: 2; /*reserved*/ 109 uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/ 110 uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/ 111 uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ 112 uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ 113 uint32_t reserved16: 8; /*reserved*/ 114 uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/ 115 uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/ 116 uint32_t usr_dummy_idle: 1; /*SPI clock is disable in dummy phase when the bit is enable.*/ 117 uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/ 118 uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/ 119 uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/ 120 uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/ 121 uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/ 122 }; 123 uint32_t val; 124 } user; 125 union { 126 struct { 127 uint32_t usr_dummy_cyclelen: 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ 128 uint32_t reserved6: 20; /*reserved*/ 129 uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ 130 }; 131 uint32_t val; 132 } user1; 133 union { 134 struct { 135 uint32_t usr_command_value: 16; /*The value of command.*/ 136 uint32_t reserved16: 12; /*reserved*/ 137 uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ 138 }; 139 uint32_t val; 140 } user2; 141 union { 142 struct { 143 uint32_t usr_mosi_bit_len: 10; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ 144 uint32_t reserved10: 22; /*reserved*/ 145 }; 146 uint32_t val; 147 } mosi_dlen; 148 union { 149 struct { 150 uint32_t usr_miso_bit_len: 10; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ 151 uint32_t reserved10: 22; /*reserved*/ 152 }; 153 uint32_t val; 154 } miso_dlen; 155 union { 156 struct { 157 uint32_t status: 16; /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/ 158 uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/ 159 uint32_t reserved24: 8; /*reserved*/ 160 }; 161 uint32_t val; 162 } rd_status; 163 uint32_t reserved_30; 164 union { 165 struct { 166 uint32_t cs0_dis: 1; /*SPI_CS0 pin enable 1: disable SPI_CS0 0: SPI_CS0 pin is active to select SPI device such as flash external RAM and so on.*/ 167 uint32_t cs1_dis: 1; /*SPI_CS1 pin enable 1: disable SPI_CS1 0: SPI_CS1 pin is active to select SPI device such as flash external RAM and so on.*/ 168 uint32_t reserved2: 1; /*reserved*/ 169 uint32_t mst_st_trans_end: 1; /*The bit is used to indicate the spi0_mst_st controlled transmitting is done.*/ 170 uint32_t mst_st_trans_end_en: 1; /*The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done.*/ 171 uint32_t st_trans_end: 1; /*The bit is used to indicate the spi0_slv_st controlled transmitting is done.*/ 172 uint32_t st_trans_end_en: 1; /*The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.*/ 173 uint32_t reserved7: 2; /*reserved*/ 174 uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/ 175 uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/ 176 uint32_t reserved11: 21; /*reserved*/ 177 }; 178 uint32_t val; 179 } misc; 180 uint32_t tx_crc; /*SPI1 TX CRC data register.*/ 181 union { 182 struct { 183 uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/ 184 uint32_t usr_addr_4byte: 1; /*For SPI1 cache read flash with 4 bytes address 1: enable 0:disable.*/ 185 uint32_t flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/ 186 uint32_t fdin_dual: 1; /*For SPI1 din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ 187 uint32_t fdout_dual: 1; /*For SPI1 dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ 188 uint32_t faddr_dual: 1; /*For SPI1 address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ 189 uint32_t fdin_quad: 1; /*For SPI1 din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ 190 uint32_t fdout_quad: 1; /*For SPI1 dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ 191 uint32_t faddr_quad: 1; /*For SPI1 address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ 192 uint32_t reserved9: 23; /*reserved*/ 193 }; 194 uint32_t val; 195 } cache_fctrl; 196 uint32_t reserved_40; 197 uint32_t reserved_44; 198 uint32_t reserved_48; 199 uint32_t reserved_4c; 200 uint32_t reserved_50; 201 union { 202 struct { 203 uint32_t spi0_st: 4; /*The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state 1: preparation state 2: send command state 3: send address state 4: wait state 5: read data state 6:write data state 7: done state 8: read data end state.*/ 204 uint32_t spi0_mst_st: 3; /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state 1:EM_CACHE_GRANT 2: program/erase suspend state 3: SPI0 read data state 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO 5: SPI0 write data state.*/ 205 uint32_t cspi_lock_delay_time: 5; /*The lock delay time of SPI0/1 arbiter by spi0_slv_st after PER is sent by SPI1.*/ 206 uint32_t reserved12: 20; /*reserved*/ 207 }; 208 uint32_t val; 209 } fsm; 210 uint32_t data_buf[16]; 211 union { 212 struct { 213 uint32_t reserved0: 1; /*reserved*/ 214 uint32_t waiti_dummy: 1; /*The dummy phase enable when wait flash idle (RDSR)*/ 215 uint32_t waiti_cmd: 8; /*The command to wait flash idle(RDSR).*/ 216 uint32_t waiti_dummy_cyclelen: 6; /*The dummy cycle length when wait flash idle(RDSR).*/ 217 uint32_t reserved16: 16; /*reserved*/ 218 }; 219 uint32_t val; 220 } flash_waiti_ctrl; 221 union { 222 struct { 223 uint32_t flash_per: 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 224 uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 225 uint32_t flash_per_wait_en: 1; /*Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after program erase suspend.*/ 226 uint32_t flash_pes_wait_en: 1; /*Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after program erase suspend.*/ 227 uint32_t pes_per_en: 1; /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0 application should send PER after PES is done.*/ 228 uint32_t flash_pes_en: 1; /*Set this bit to enable Auto-suspending function.*/ 229 uint32_t pesr_end_msk: 16; /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out status_in[15:0] is valid when two bytes of data are read out) SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/ 230 uint32_t frd_sus_2b: 1; /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit*/ 231 uint32_t per_end_en: 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/ 232 uint32_t pes_end_en: 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/ 233 uint32_t sus_timeout_cnt: 7; /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times it will be treated as check pass.*/ 234 }; 235 uint32_t val; 236 } flash_sus_ctrl; 237 union { 238 struct { 239 uint32_t flash_per_command: 8; /*Program/Erase resume command.*/ 240 uint32_t flash_pes_command: 8; /*Program/Erase suspend command.*/ 241 uint32_t wait_pesr_command: 16; /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/ 242 }; 243 uint32_t val; 244 } flash_sus_cmd; 245 union { 246 struct { 247 uint32_t flash_sus: 1; /*The status of flash suspend only used in SPI1.*/ 248 uint32_t reserved1: 31; /*reserved*/ 249 }; 250 uint32_t val; 251 } sus_status; 252 union { 253 struct { 254 uint32_t timing_clk_ena: 1; /*The bit is used to enable timing adjust clock for all reading operations.*/ 255 uint32_t timing_cali: 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/ 256 uint32_t extra_dummy_cyclelen: 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/ 257 uint32_t reserved5: 27; /*reserved*/ 258 }; 259 uint32_t val; 260 } timing_cali; 261 union { 262 struct { 263 uint32_t din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ 264 uint32_t din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ 265 uint32_t din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ 266 uint32_t din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ 267 uint32_t reserved8: 24; /*reserved*/ 268 }; 269 uint32_t val; 270 } din_mode; 271 union { 272 struct { 273 uint32_t din0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ 274 uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ 275 uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ 276 uint32_t din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ 277 uint32_t reserved8: 24; /*reserved*/ 278 }; 279 uint32_t val; 280 } din_num; 281 union { 282 struct { 283 uint32_t dout0_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ 284 uint32_t dout1_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ 285 uint32_t dout2_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ 286 uint32_t dout3_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ 287 uint32_t reserved4: 28; /*reserved*/ 288 }; 289 uint32_t val; 290 } dout_mode; 291 uint32_t reserved_b8; 292 uint32_t reserved_bc; 293 union { 294 struct { 295 uint32_t per_end_int_ena: 1; /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/ 296 uint32_t pes_end_int_ena: 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/ 297 uint32_t wpe_end_int_ena: 1; /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/ 298 uint32_t st_end_int_ena: 1; /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ 299 uint32_t mst_st_end_int_ena: 1; /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/ 300 uint32_t reserved5: 27; /*reserved*/ 301 }; 302 uint32_t val; 303 } int_ena; 304 union { 305 struct { 306 uint32_t per_end: 1; /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/ 307 uint32_t pes_end: 1; /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/ 308 uint32_t wpe_end: 1; /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/ 309 uint32_t st_end: 1; /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ 310 uint32_t mst_st_end: 1; /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/ 311 uint32_t reserved5: 27; /*reserved*/ 312 }; 313 uint32_t val; 314 } int_clr; 315 union { 316 struct { 317 uint32_t per_end: 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/ 318 uint32_t pes_end: 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/ 319 uint32_t wpe_end: 1; /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/ 320 uint32_t st_end: 1; /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/ 321 uint32_t mst_st_end: 1; /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/ 322 uint32_t reserved5: 27; /*reserved*/ 323 }; 324 uint32_t val; 325 } int_raw; 326 union { 327 struct { 328 uint32_t per_end: 1; /*The status bit for SPI_MEM_PER_END_INT interrupt.*/ 329 uint32_t pes_end: 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/ 330 uint32_t wpe_end: 1; /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/ 331 uint32_t st_end: 1; /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ 332 uint32_t mst_st_end: 1; /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/ 333 uint32_t reserved5: 27; /*reserved*/ 334 }; 335 uint32_t val; 336 } int_st; 337 uint32_t reserved_d0; 338 uint32_t reserved_d4; 339 uint32_t reserved_d8; 340 union { 341 struct { 342 uint32_t clk_en: 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/ 343 uint32_t reserved1: 31; /*reserved*/ 344 }; 345 uint32_t val; 346 } clock_gate; 347 union { 348 struct { 349 uint32_t spi01_clk_sel: 2; /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/ 350 uint32_t reserved2: 30; /*reserved*/ 351 }; 352 uint32_t val; 353 } core_clk_sel; 354 uint32_t reserved_e4; 355 uint32_t reserved_e8; 356 uint32_t reserved_ec; 357 uint32_t reserved_f0; 358 uint32_t reserved_f4; 359 uint32_t reserved_f8; 360 uint32_t reserved_fc; 361 uint32_t reserved_100; 362 uint32_t reserved_104; 363 uint32_t reserved_108; 364 uint32_t reserved_10c; 365 uint32_t reserved_110; 366 uint32_t reserved_114; 367 uint32_t reserved_118; 368 uint32_t reserved_11c; 369 uint32_t reserved_120; 370 uint32_t reserved_124; 371 uint32_t reserved_128; 372 uint32_t reserved_12c; 373 uint32_t reserved_130; 374 uint32_t reserved_134; 375 uint32_t reserved_138; 376 uint32_t reserved_13c; 377 uint32_t reserved_140; 378 uint32_t reserved_144; 379 uint32_t reserved_148; 380 uint32_t reserved_14c; 381 uint32_t reserved_150; 382 uint32_t reserved_154; 383 uint32_t reserved_158; 384 uint32_t reserved_15c; 385 uint32_t reserved_160; 386 uint32_t reserved_164; 387 uint32_t reserved_168; 388 uint32_t reserved_16c; 389 uint32_t reserved_170; 390 uint32_t reserved_174; 391 uint32_t reserved_178; 392 uint32_t reserved_17c; 393 uint32_t reserved_180; 394 uint32_t reserved_184; 395 uint32_t reserved_188; 396 uint32_t reserved_18c; 397 uint32_t reserved_190; 398 uint32_t reserved_194; 399 uint32_t reserved_198; 400 uint32_t reserved_19c; 401 uint32_t reserved_1a0; 402 uint32_t reserved_1a4; 403 uint32_t reserved_1a8; 404 uint32_t reserved_1ac; 405 uint32_t reserved_1b0; 406 uint32_t reserved_1b4; 407 uint32_t reserved_1b8; 408 uint32_t reserved_1bc; 409 uint32_t reserved_1c0; 410 uint32_t reserved_1c4; 411 uint32_t reserved_1c8; 412 uint32_t reserved_1cc; 413 uint32_t reserved_1d0; 414 uint32_t reserved_1d4; 415 uint32_t reserved_1d8; 416 uint32_t reserved_1dc; 417 uint32_t reserved_1e0; 418 uint32_t reserved_1e4; 419 uint32_t reserved_1e8; 420 uint32_t reserved_1ec; 421 uint32_t reserved_1f0; 422 uint32_t reserved_1f4; 423 uint32_t reserved_1f8; 424 uint32_t reserved_1fc; 425 uint32_t reserved_200; 426 uint32_t reserved_204; 427 uint32_t reserved_208; 428 uint32_t reserved_20c; 429 uint32_t reserved_210; 430 uint32_t reserved_214; 431 uint32_t reserved_218; 432 uint32_t reserved_21c; 433 uint32_t reserved_220; 434 uint32_t reserved_224; 435 uint32_t reserved_228; 436 uint32_t reserved_22c; 437 uint32_t reserved_230; 438 uint32_t reserved_234; 439 uint32_t reserved_238; 440 uint32_t reserved_23c; 441 uint32_t reserved_240; 442 uint32_t reserved_244; 443 uint32_t reserved_248; 444 uint32_t reserved_24c; 445 uint32_t reserved_250; 446 uint32_t reserved_254; 447 uint32_t reserved_258; 448 uint32_t reserved_25c; 449 uint32_t reserved_260; 450 uint32_t reserved_264; 451 uint32_t reserved_268; 452 uint32_t reserved_26c; 453 uint32_t reserved_270; 454 uint32_t reserved_274; 455 uint32_t reserved_278; 456 uint32_t reserved_27c; 457 uint32_t reserved_280; 458 uint32_t reserved_284; 459 uint32_t reserved_288; 460 uint32_t reserved_28c; 461 uint32_t reserved_290; 462 uint32_t reserved_294; 463 uint32_t reserved_298; 464 uint32_t reserved_29c; 465 uint32_t reserved_2a0; 466 uint32_t reserved_2a4; 467 uint32_t reserved_2a8; 468 uint32_t reserved_2ac; 469 uint32_t reserved_2b0; 470 uint32_t reserved_2b4; 471 uint32_t reserved_2b8; 472 uint32_t reserved_2bc; 473 uint32_t reserved_2c0; 474 uint32_t reserved_2c4; 475 uint32_t reserved_2c8; 476 uint32_t reserved_2cc; 477 uint32_t reserved_2d0; 478 uint32_t reserved_2d4; 479 uint32_t reserved_2d8; 480 uint32_t reserved_2dc; 481 uint32_t reserved_2e0; 482 uint32_t reserved_2e4; 483 uint32_t reserved_2e8; 484 uint32_t reserved_2ec; 485 uint32_t reserved_2f0; 486 uint32_t reserved_2f4; 487 uint32_t reserved_2f8; 488 uint32_t reserved_2fc; 489 uint32_t reserved_300; 490 uint32_t reserved_304; 491 uint32_t reserved_308; 492 uint32_t reserved_30c; 493 uint32_t reserved_310; 494 uint32_t reserved_314; 495 uint32_t reserved_318; 496 uint32_t reserved_31c; 497 uint32_t reserved_320; 498 uint32_t reserved_324; 499 uint32_t reserved_328; 500 uint32_t reserved_32c; 501 uint32_t reserved_330; 502 uint32_t reserved_334; 503 uint32_t reserved_338; 504 uint32_t reserved_33c; 505 uint32_t reserved_340; 506 uint32_t reserved_344; 507 uint32_t reserved_348; 508 uint32_t reserved_34c; 509 uint32_t reserved_350; 510 uint32_t reserved_354; 511 uint32_t reserved_358; 512 uint32_t reserved_35c; 513 uint32_t reserved_360; 514 uint32_t reserved_364; 515 uint32_t reserved_368; 516 uint32_t reserved_36c; 517 uint32_t reserved_370; 518 uint32_t reserved_374; 519 uint32_t reserved_378; 520 uint32_t reserved_37c; 521 uint32_t reserved_380; 522 uint32_t reserved_384; 523 uint32_t reserved_388; 524 uint32_t reserved_38c; 525 uint32_t reserved_390; 526 uint32_t reserved_394; 527 uint32_t reserved_398; 528 uint32_t reserved_39c; 529 uint32_t reserved_3a0; 530 uint32_t reserved_3a4; 531 uint32_t reserved_3a8; 532 uint32_t reserved_3ac; 533 uint32_t reserved_3b0; 534 uint32_t reserved_3b4; 535 uint32_t reserved_3b8; 536 uint32_t reserved_3bc; 537 uint32_t reserved_3c0; 538 uint32_t reserved_3c4; 539 uint32_t reserved_3c8; 540 uint32_t reserved_3cc; 541 uint32_t reserved_3d0; 542 uint32_t reserved_3d4; 543 uint32_t reserved_3d8; 544 uint32_t reserved_3dc; 545 uint32_t reserved_3e0; 546 uint32_t reserved_3e4; 547 uint32_t reserved_3e8; 548 uint32_t reserved_3ec; 549 uint32_t reserved_3f0; 550 uint32_t reserved_3f4; 551 uint32_t reserved_3f8; 552 union { 553 struct { 554 uint32_t date: 28; /*Version control register*/ 555 uint32_t reserved28: 4; /*reserved*/ 556 }; 557 uint32_t val; 558 } date; 559 } spi_mem_dev_t; 560 extern spi_mem_dev_t SPIMEM0; 561 extern spi_mem_dev_t SPIMEM1; 562 563 _Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!"); 564 565 #ifdef __cplusplus 566 } 567 #endif 568 569 #endif /* _SOC_SPI_MEM_STRUCT_H_ */ 570
