1 // Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef BOOTLOADER_BUILD 15 16 #include <stdlib.h> 17 #include <stdint.h> 18 19 #include "soc/soc.h" 20 #include "heap_memory_layout.h" 21 #include "esp_heap_caps.h" 22 #include "sdkconfig.h" 23 24 #ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY 25 #define MALLOC_IRAM_CAP MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_IRAM_8BIT 26 #else 27 #define MALLOC_IRAM_CAP MALLOC_CAP_EXEC|MALLOC_CAP_32BIT 28 #endif 29 30 /* Memory layout for ESP32 SoC */ 31 32 /* 33 Memory type descriptors. These describe the capabilities of a type of memory in the SoC. Each type of memory 34 map consist of one or more regions in the address space. 35 36 Each type contains an array of prioritised capabilities; types with later entries are only taken if earlier 37 ones can't fulfill the memory request. 38 39 The prioritised capabilities work roughly like this: 40 - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, 41 finally eat into the application memory. 42 - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM. 43 - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM. 44 - Most other malloc caps only fit in one region anyway. 45 46 */ 47 const soc_memory_type_desc_t soc_memory_types[] = { 48 //Type 0: Plain ole D-port RAM 49 { "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, false}, 50 //Type 1: Plain ole D-port RAM which has an alias on the I-port 51 //(This DRAM is also the region used by ROM during startup) 52 { "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, true}, 53 //Type 2: IRAM 54 { "IRAM", { MALLOC_CAP_INTERNAL|MALLOC_IRAM_CAP, 0, 0 }, false, false}, 55 //Type 3-8: PID 2-7 IRAM 56 { "PID2IRAM", { MALLOC_CAP_PID2|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false}, 57 { "PID3IRAM", { MALLOC_CAP_PID3|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false}, 58 { "PID4IRAM", { MALLOC_CAP_PID4|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false}, 59 { "PID5IRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false}, 60 { "PID6IRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false}, 61 { "PID7IRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false}, 62 //Type 9-14: PID 2-7 DRAM 63 { "PID2DRAM", { MALLOC_CAP_PID2|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false}, 64 { "PID3DRAM", { MALLOC_CAP_PID3|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false}, 65 { "PID4DRAM", { MALLOC_CAP_PID4|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false}, 66 { "PID5DRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false}, 67 { "PID6DRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false}, 68 { "PID7DRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false}, 69 //Type 15: SPI SRAM data 70 { "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false}, 71 //Type 16: RTC Fast RAM 72 { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT }, false, false}, 73 }; 74 75 const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t); 76 77 /* 78 Region descriptors. These describe all regions of memory available, and map them to a type in the above type. 79 80 Because of requirements in the coalescing code which merges adjacent regions, this list should always be sorted 81 from low to high start address. 82 */ 83 const soc_memory_region_t soc_memory_regions[] = { 84 #ifdef CONFIG_SPIRAM 85 { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 15, 0}, //SPI SRAM, if available 86 #endif 87 { 0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code 88 { 0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- if BT is enabled, used as BT HW shared memory 89 { 0x3FFB8000, 0x8000, 0, 0}, //pool 14 <- if BT is enabled, used data memory for BT ROM functions. 90 { 0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0 91 { 0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1 92 { 0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2 93 { 0x3FFC6000, 0x2000, 0, 0}, //pool 10-13, mmu page 3 94 { 0x3FFC8000, 0x2000, 0, 0}, //pool 10-13, mmu page 4 95 { 0x3FFCA000, 0x2000, 0, 0}, //pool 10-13, mmu page 5 96 { 0x3FFCC000, 0x2000, 0, 0}, //pool 10-13, mmu page 6 97 { 0x3FFCE000, 0x2000, 0, 0}, //pool 10-13, mmu page 7 98 { 0x3FFD0000, 0x2000, 0, 0}, //pool 10-13, mmu page 8 99 { 0x3FFD2000, 0x2000, 0, 0}, //pool 10-13, mmu page 9 100 { 0x3FFD4000, 0x2000, 0, 0}, //pool 10-13, mmu page 10 101 { 0x3FFD6000, 0x2000, 0, 0}, //pool 10-13, mmu page 11 102 { 0x3FFD8000, 0x2000, 0, 0}, //pool 10-13, mmu page 12 103 { 0x3FFDA000, 0x2000, 0, 0}, //pool 10-13, mmu page 13 104 { 0x3FFDC000, 0x2000, 0, 0}, //pool 10-13, mmu page 14 105 { 0x3FFDE000, 0x2000, 0, 0}, //pool 10-13, mmu page 15 106 { 0x3FFE0000, 0x4000, 1, 0x400BC000}, //pool 9 blk 1 107 { 0x3FFE4000, 0x4000, 1, 0x400B8000}, //pool 9 blk 0 108 { 0x3FFE8000, 0x8000, 1, 0x400B0000}, //pool 8 <- can be remapped to ROM, used for MAC dump 109 { 0x3FFF0000, 0x8000, 1, 0x400A8000}, //pool 7 <- can be used for MAC dump 110 { 0x3FFF8000, 0x4000, 1, 0x400A4000}, //pool 6 blk 1 <- can be used as trace memory 111 { 0x3FFFC000, 0x4000, 1, 0x400A0000}, //pool 6 blk 0 <- can be used as trace memory 112 { 0x40070000, 0x8000, 2, 0}, //pool 0 113 { 0x40078000, 0x8000, 2, 0}, //pool 1 114 { 0x40080000, 0x2000, 2, 0}, //pool 2-5, mmu page 0 115 { 0x40082000, 0x2000, 2, 0}, //pool 2-5, mmu page 1 116 { 0x40084000, 0x2000, 2, 0}, //pool 2-5, mmu page 2 117 { 0x40086000, 0x2000, 2, 0}, //pool 2-5, mmu page 3 118 { 0x40088000, 0x2000, 2, 0}, //pool 2-5, mmu page 4 119 { 0x4008A000, 0x2000, 2, 0}, //pool 2-5, mmu page 5 120 { 0x4008C000, 0x2000, 2, 0}, //pool 2-5, mmu page 6 121 { 0x4008E000, 0x2000, 2, 0}, //pool 2-5, mmu page 7 122 { 0x40090000, 0x2000, 2, 0}, //pool 2-5, mmu page 8 123 { 0x40092000, 0x2000, 2, 0}, //pool 2-5, mmu page 9 124 { 0x40094000, 0x2000, 2, 0}, //pool 2-5, mmu page 10 125 { 0x40096000, 0x2000, 2, 0}, //pool 2-5, mmu page 11 126 { 0x40098000, 0x2000, 2, 0}, //pool 2-5, mmu page 12 127 { 0x4009A000, 0x2000, 2, 0}, //pool 2-5, mmu page 13 128 { 0x4009C000, 0x2000, 2, 0}, //pool 2-5, mmu page 14 129 { 0x4009E000, 0x2000, 2, 0}, //pool 2-5, mmu page 15 130 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 131 { SOC_RTC_DRAM_LOW, 0x2000, 16, 0}, //RTC Fast Memory 132 #endif 133 }; 134 135 const size_t soc_memory_region_count = sizeof(soc_memory_regions)/sizeof(soc_memory_region_t); 136 137 138 /* Reserved memory regions 139 140 These are removed from the soc_memory_regions array when heaps are created. 141 */ 142 SOC_RESERVE_MEMORY_REGION(SOC_CACHE_PRO_LOW, SOC_CACHE_PRO_HIGH, cpu0_cache); 143 #ifndef CONFIG_FREERTOS_UNICORE 144 SOC_RESERVE_MEMORY_REGION(SOC_CACHE_APP_LOW, SOC_CACHE_APP_HIGH, cpu1_cache); 145 #endif 146 147 /* Warning: The ROM stack is located in the 0x3ffe0000 area. We do not specifically disable that area here because 148 after the scheduler has started, the ROM stack is not used anymore by anything. We handle it instead by not allowing 149 any mallocs memory regions with the startup_stack flag set (these are the IRAM/DRAM region) until the 150 scheduler has started. 151 152 The 0x3ffe0000 region also contains static RAM for various ROM functions. The following lines 153 reserve the regions for UART and ETSC, so these functions are usable. Libraries like xtos, which are 154 not usable in FreeRTOS anyway, are commented out in the linker script so they cannot be used; we 155 do not disable their memory regions here and they will be used as general purpose heap memory. 156 157 Enabling the heap allocator for this region but disabling allocation here until FreeRTOS is started up 158 is a somewhat risky action in theory, because on initializing the allocator, the multi_heap implementation 159 will go and write metadata at the start and end of all regions. For the ESP32, these linked 160 list entries happen to end up in a region that is not touched by the stack; they can be placed safely there. 161 */ 162 163 SOC_RESERVE_MEMORY_REGION(0x3ffe0000, 0x3ffe0440, rom_pro_data); //Reserve ROM PRO data region 164 #ifndef CONFIG_FREERTOS_UNICORE 165 SOC_RESERVE_MEMORY_REGION(0x3ffe3f20, 0x3ffe4350, rom_app_data); //Reserve ROM APP data region 166 #endif 167 168 SOC_RESERVE_MEMORY_REGION(0x3ffae000, 0x3ffae6e0, rom_data); 169 170 #if CONFIG_ESP32_MEMMAP_TRACEMEM 171 #if CONFIG_ESP32_MEMMAP_TRACEMEM_TWOBANKS 172 SOC_RESERVE_MEMORY_REGION(0x3fff8000, 0x40000000, trace_mem); //Reserve trace mem region, 32K for both cpu 173 #else 174 SOC_RESERVE_MEMORY_REGION(0x3fffc000, 0x40000000, trace_mem); //Reserve trace mem region, 16K (upper-half) for pro cpu 175 #endif 176 #endif 177 178 #ifdef CONFIG_SPIRAM 179 /* Reserve the whole possible SPIRAM region here, spiram.c will add some or all of this 180 * memory to heap depending on the actual SPIRAM chip size. */ 181 SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, spi_ram); 182 #endif 183 184 extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_fast_end, _rtc_noinit_end; 185 // Static data region. DRAM used by data+bss and possibly rodata 186 SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data); 187 188 // IRAM code region 189 // ESP32 has an IRAM-only region 0x4008_0000 - 0x4009_FFFF, reserve the used part 190 SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code); 191 192 // RTC Fast RAM region 193 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 194 #ifdef CONFIG_ESP32_RTCDATA_IN_FAST_MEM 195 SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_noinit_end, rtcram_data); 196 #else 197 SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_fast_end, rtcram_data); 198 #endif 199 #endif 200 201 #endif /* BOOTLOADER_BUILD */ 202
