1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "soc/soc_caps.h"
16 #include "hal/cp_dma_hal.h"
17 #include "hal/cp_dma_ll.h"
18
cp_dma_hal_init(cp_dma_hal_context_t * hal,const cp_dma_hal_config_t * config)19 void cp_dma_hal_init(cp_dma_hal_context_t *hal, const cp_dma_hal_config_t *config)
20 {
21 hal->dev = &CP_DMA;
22 cp_dma_ll_enable_clock(hal->dev, true);
23 cp_dma_ll_reset_in_link(hal->dev);
24 cp_dma_ll_reset_out_link(hal->dev);
25 cp_dma_ll_reset_cmd_fifo(hal->dev);
26 cp_dma_ll_reset_fifo(hal->dev);
27 cp_dma_ll_enable_intr(hal->dev, UINT32_MAX, false);
28 cp_dma_ll_clear_intr_status(hal->dev, UINT32_MAX);
29 cp_dma_ll_enable_owner_check(hal->dev, true);
30 }
31
cp_dma_hal_set_desc_base_addr(cp_dma_hal_context_t * hal,intptr_t outlink_base,intptr_t inlink_base)32 void cp_dma_hal_set_desc_base_addr(cp_dma_hal_context_t *hal, intptr_t outlink_base, intptr_t inlink_base)
33 {
34 /* set base address of the first descriptor */
35 cp_dma_ll_tx_set_descriptor_base_addr(hal->dev, outlink_base);
36 cp_dma_ll_rx_set_descriptor_base_addr(hal->dev, inlink_base);
37 }
38
cp_dma_hal_deinit(cp_dma_hal_context_t * hal)39 void cp_dma_hal_deinit(cp_dma_hal_context_t *hal)
40 {
41 cp_dma_ll_enable_clock(hal->dev, false);
42 hal->dev = NULL;
43 }
44
cp_dma_hal_start(cp_dma_hal_context_t * hal)45 void cp_dma_hal_start(cp_dma_hal_context_t *hal)
46 {
47 // enable DMA engine
48 cp_dma_ll_start_rx(hal->dev, true);
49 cp_dma_ll_start_tx(hal->dev, true);
50 // enable RX EOF interrupt
51 cp_dma_ll_enable_intr(hal->dev, CP_DMA_LL_EVENT_RX_EOF, true);
52 }
53
cp_dma_hal_stop(cp_dma_hal_context_t * hal)54 void cp_dma_hal_stop(cp_dma_hal_context_t *hal)
55 {
56 // disable interrupt
57 cp_dma_ll_enable_intr(hal->dev, CP_DMA_LL_EVENT_RX_EOF, false);
58
59 // disable DMA
60 cp_dma_ll_start_rx(hal->dev, false);
61 cp_dma_ll_start_tx(hal->dev, false);
62 }
63
cp_dma_hal_get_intr_status(cp_dma_hal_context_t * hal)64 uint32_t cp_dma_hal_get_intr_status(cp_dma_hal_context_t *hal)
65 {
66 return cp_dma_ll_get_intr_status(hal->dev);
67 }
68
cp_dma_hal_clear_intr_status(cp_dma_hal_context_t * hal,uint32_t mask)69 void cp_dma_hal_clear_intr_status(cp_dma_hal_context_t *hal, uint32_t mask)
70 {
71 cp_dma_ll_clear_intr_status(hal->dev, mask);
72 }
73
cp_dma_hal_restart_tx(cp_dma_hal_context_t * hal)74 void cp_dma_hal_restart_tx(cp_dma_hal_context_t *hal)
75 {
76 cp_dma_ll_restart_tx(hal->dev);
77 }
78
cp_dma_hal_restart_rx(cp_dma_hal_context_t * hal)79 void cp_dma_hal_restart_rx(cp_dma_hal_context_t *hal)
80 {
81 cp_dma_ll_restart_rx(hal->dev);
82 }
83
