1 /*
2 * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include <string.h>
9 #include <stdbool.h>
10
11 #include "esp_attr.h"
12 #include "esp_err.h"
13
14 #include "esp_log.h"
15 #include "esp_system.h"
16
17 #include "esp_efuse.h"
18 #include "cache_err_int.h"
19 #include "esp_clk_internal.h"
20
21 #include "esp_rom_efuse.h"
22 #include "esp_rom_uart.h"
23 #include "esp_rom_sys.h"
24 #include "sdkconfig.h"
25
26 #if CONFIG_IDF_TARGET_ESP32
27 #include "soc/dport_reg.h"
28 #include "esp32/rtc.h"
29 #include "esp32/rom/cache.h"
30 #include "esp32/spiram.h"
31 #elif CONFIG_IDF_TARGET_ESP32S2
32 #include "esp32s2/rtc.h"
33 #include "esp32s2/rom/cache.h"
34 #include "esp32s2/spiram.h"
35 #include "esp32s2/dport_access.h"
36 #elif CONFIG_IDF_TARGET_ESP32S3
37 #include "esp32s3/rtc.h"
38 #include "esp32s3/rom/cache.h"
39 #include "esp32s3/spiram.h"
40 #include "esp32s3/dport_access.h"
41 #include "soc/assist_debug_reg.h"
42 #include "soc/cache_memory.h"
43 #include "soc/system_reg.h"
44 #include "esp32s3/rom/opi_flash.h"
45 #elif CONFIG_IDF_TARGET_ESP32C3
46 #include "esp32c3/rtc.h"
47 #include "esp32c3/rom/cache.h"
48 #include "soc/cache_memory.h"
49 #elif CONFIG_IDF_TARGET_ESP32H2
50 #include "esp32h2/rtc.h"
51 #include "esp32h2/rom/cache.h"
52 #include "soc/cache_memory.h"
53 #endif
54
55 #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
56 #if CONFIG_IDF_TARGET_ESP32S2
57 #include "esp32s2/memprot.h"
58 #else
59 #include "esp_memprot.h"
60 #endif
61 #endif
62
63 #include "esp_private/spi_flash_os.h"
64 #include "bootloader_flash_config.h"
65 #include "bootloader_flash.h"
66 #include "esp_private/crosscore_int.h"
67 #include "esp_flash_encrypt.h"
68
69 #include "hal/rtc_io_hal.h"
70 #include "hal/gpio_hal.h"
71 #include "hal/wdt_hal.h"
72 #include "soc/rtc.h"
73 #include "soc/efuse_reg.h"
74 #include "soc/periph_defs.h"
75 #include "soc/cpu.h"
76 #include "soc/rtc.h"
77 #include "soc/spinlock.h"
78
79 #if CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX || CONFIG_ESP32S3_TRAX
80 #include "trax.h"
81 #endif
82
83 #include "bootloader_mem.h"
84
85 #if CONFIG_APP_BUILD_TYPE_ELF_RAM
86 #if CONFIG_IDF_TARGET_ESP32
87 #include "esp32/rom/spi_flash.h"
88 #elif CONFIG_IDF_TARGET_ESP32S2
89 #include "esp32s2/rom/spi_flash.h"
90 #elif CONFIG_IDF_TARGET_ESP32S3
91 #include "esp32s3/rom/spi_flash.h"
92 #elif CONFIG_IDF_TARGET_ESP32C3
93 #include "esp32c3/rom/spi_flash.h"
94 #elif CONFIG_IDF_TARGET_ESP32H2
95 #include "esp32h2/rom/spi_flash.h"
96 #endif
97 #endif // CONFIG_APP_BUILD_TYPE_ELF_RAM
98
99 // Set efuse ROM_LOG_MODE on first boot
100 //
101 // For CONFIG_BOOT_ROM_LOG_ALWAYS_ON (default) or undefined (ESP32), leave
102 // ROM_LOG_MODE undefined (no need to call this function during startup)
103 #if CONFIG_BOOT_ROM_LOG_ALWAYS_OFF
104 #define ROM_LOG_MODE ESP_EFUSE_ROM_LOG_ALWAYS_OFF
105 #elif CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW
106 #define ROM_LOG_MODE ESP_EFUSE_ROM_LOG_ON_GPIO_LOW
107 #elif CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH
108 #define ROM_LOG_MODE ESP_EFUSE_ROM_LOG_ON_GPIO_HIGH
109 #endif
110
111
112 #include "esp_private/startup_internal.h"
113 #include "esp_private/system_internal.h"
114
115 extern int _bss_start;
116 extern int _bss_end;
117 extern int _rtc_bss_start;
118 extern int _rtc_bss_end;
119
120 extern int _vector_table;
121
122 static const char *TAG = "cpu_start";
123
124 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
125 extern int _ext_ram_bss_start;
126 extern int _ext_ram_bss_end;
127 #endif
128
129 #ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
130 extern int _iram_bss_start;
131 extern int _iram_bss_end;
132 #endif
133
134 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
135 static volatile bool s_cpu_up[SOC_CPU_CORES_NUM] = { false };
136 static volatile bool s_cpu_inited[SOC_CPU_CORES_NUM] = { false };
137
138 static volatile bool s_resume_cores;
139 #endif
140
141 // If CONFIG_SPIRAM_IGNORE_NOTFOUND is set and external RAM is not found or errors out on testing, this is set to false.
142 bool g_spiram_ok = true;
143
core_intr_matrix_clear(void)144 static void core_intr_matrix_clear(void)
145 {
146 uint32_t core_id = cpu_hal_get_core_id();
147
148 for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
149 intr_matrix_set(core_id, i, ETS_INVALID_INUM);
150 }
151 }
152
153 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
startup_resume_other_cores(void)154 void startup_resume_other_cores(void)
155 {
156 s_resume_cores = true;
157 }
158
call_start_cpu1(void)159 void IRAM_ATTR call_start_cpu1(void)
160 {
161 cpu_hal_set_vecbase(&_vector_table);
162
163 ets_set_appcpu_boot_addr(0);
164
165 bootloader_init_mem();
166
167 #if CONFIG_ESP_CONSOLE_UART_NONE
168 esp_rom_install_channel_putc(1, NULL);
169 esp_rom_install_channel_putc(2, NULL);
170 #else // CONFIG_ESP_CONSOLE_UART_NONE
171 esp_rom_install_uart_printf();
172 esp_rom_uart_set_as_console(CONFIG_ESP_CONSOLE_UART_NUM);
173 #endif
174
175 #if CONFIG_IDF_TARGET_ESP32
176 DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
177 DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
178 #else
179 REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_REG, 1);
180 REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG, 1);
181 #endif
182
183 s_cpu_up[1] = true;
184 ESP_EARLY_LOGI(TAG, "App cpu up.");
185
186 // Clear interrupt matrix for APP CPU core
187 core_intr_matrix_clear();
188
189 //Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
190 //has started, but it isn't active *on this CPU* yet.
191 esp_cache_err_int_init();
192
193 #if (CONFIG_IDF_TARGET_ESP32 && CONFIG_ESP32_TRAX_TWOBANKS) || \
194 (CONFIG_IDF_TARGET_ESP32S3 && CONFIG_ESP32S3_TRAX_TWOBANKS)
195 trax_start_trace(TRAX_DOWNCOUNT_WORDS);
196 #endif
197
198 s_cpu_inited[1] = true;
199
200 while (!s_resume_cores) {
201 esp_rom_delay_us(100);
202 }
203
204 SYS_STARTUP_FN();
205 }
206
start_other_core(void)207 static void start_other_core(void)
208 {
209 esp_chip_info_t chip_info;
210 esp_chip_info(&chip_info);
211
212 // If not the single core variant of a target - check this since there is
213 // no separate soc_caps.h for the single core variant.
214 if (!(chip_info.cores > 1)) {
215 ESP_EARLY_LOGE(TAG, "Running on single core variant of a chip, but app is built with multi-core support.");
216 ESP_EARLY_LOGE(TAG, "Check that CONFIG_FREERTOS_UNICORE is enabled in menuconfig");
217 abort();
218 }
219
220 ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
221
222 #if CONFIG_IDF_TARGET_ESP32
223 Cache_Flush(1);
224 Cache_Read_Enable(1);
225 #endif
226
227 esp_cpu_unstall(1);
228
229 // Enable clock and reset APP CPU. Note that OpenOCD may have already
230 // enabled clock and taken APP CPU out of reset. In this case don't reset
231 // APP CPU again, as that will clear the breakpoints which may have already
232 // been set.
233 #if CONFIG_IDF_TARGET_ESP32
234 if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
235 DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
236 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
237 DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
238 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
239 }
240 #elif CONFIG_IDF_TARGET_ESP32S3
241 if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) {
242 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
243 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
244 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
245 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
246 }
247 #endif
248 ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
249
250 bool cpus_up = false;
251
252 while (!cpus_up) {
253 cpus_up = true;
254 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
255 cpus_up &= s_cpu_up[i];
256 }
257 esp_rom_delay_us(100);
258 }
259 }
260 #endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
261
262 /*
263 * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
264 * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
265 */
call_start_cpu0(void)266 void IRAM_ATTR call_start_cpu0(void)
267 {
268 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
269 soc_reset_reason_t rst_reas[SOC_CPU_CORES_NUM];
270 #else
271 soc_reset_reason_t rst_reas[1];
272 #endif
273
274 #ifdef __riscv
275 if (cpu_hal_is_debugger_attached()) {
276 /* Let debugger some time to detect that target started, halt it, enable ebreaks and resume.
277 500ms should be enough. */
278 for (uint32_t ms_num = 0; ms_num < 2; ms_num++) {
279 esp_rom_delay_us(100000);
280 }
281 }
282 // Configure the global pointer register
283 // (This should be the first thing IDF app does, as any other piece of code could be
284 // relaxed by the linker to access something relative to __global_pointer$)
285 __asm__ __volatile__ (
286 ".option push\n"
287 ".option norelax\n"
288 "la gp, __global_pointer$\n"
289 ".option pop"
290 );
291 #endif
292
293 // Move exception vectors to IRAM
294 cpu_hal_set_vecbase(&_vector_table);
295
296 rst_reas[0] = esp_rom_get_reset_reason(0);
297 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
298 rst_reas[1] = esp_rom_get_reset_reason(1);
299 #endif
300
301 #ifndef CONFIG_BOOTLOADER_WDT_ENABLE
302 // from panic handler we can be reset by RWDT or TG0WDT
303 if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0
304 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
305 || rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0
306 #endif
307 ) {
308 wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
309 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
310 wdt_hal_disable(&rtc_wdt_ctx);
311 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
312 }
313 #endif
314
315 //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
316 memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
317
318 #if defined(CONFIG_IDF_TARGET_ESP32) && defined(CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY)
319 // Clear IRAM BSS
320 memset(&_iram_bss_start, 0, (&_iram_bss_end - &_iram_bss_start) * sizeof(_iram_bss_start));
321 #endif
322
323 /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
324 if (rst_reas[0] != RESET_REASON_CORE_DEEP_SLEEP) {
325 memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
326 }
327
328 #if CONFIG_IDF_TARGET_ESP32S2
329 /* Configure the mode of instruction cache : cache size, cache associated ways, cache line size. */
330 extern void esp_config_instruction_cache_mode(void);
331 esp_config_instruction_cache_mode();
332
333 /* If we need use SPIRAM, we should use data cache, or if we want to access rodata, we also should use data cache.
334 Configure the mode of data : cache size, cache associated ways, cache line size.
335 Enable data cache, so if we don't use SPIRAM, it just works. */
336 #if CONFIG_SPIRAM_BOOT_INIT
337 extern void esp_config_data_cache_mode(void);
338 esp_config_data_cache_mode();
339 Cache_Enable_DCache(0);
340 #endif
341 #endif
342
343 #if CONFIG_IDF_TARGET_ESP32S3
344 /* Configure the mode of instruction cache : cache size, cache line size. */
345 extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size);
346 rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE, CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE);
347
348 /* If we need use SPIRAM, we should use data cache.
349 Configure the mode of data : cache size, cache line size.*/
350 Cache_Suspend_DCache();
351 extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size);
352 rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE, CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
353 Cache_Resume_DCache(0);
354 #endif // CONFIG_IDF_TARGET_ESP32S3
355
356 #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
357 /* Configure the Cache MMU size for instruction and rodata in flash. */
358 extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
359 extern int _rodata_reserved_start;
360 uint32_t rodata_reserved_start_align = (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
361 uint32_t cache_mmu_irom_size = ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t);
362
363 #if CONFIG_IDF_TARGET_ESP32S3
364 extern int _rodata_reserved_end;
365 uint32_t cache_mmu_drom_size = (((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE) * sizeof(uint32_t);
366 #endif
367
368 Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
369 #endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
370
371 #if CONFIG_ESPTOOLPY_OCT_FLASH
372 bool efuse_opflash_en = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA3_REG, EFUSE_FLASH_TYPE);
373 if (!efuse_opflash_en) {
374 ESP_EARLY_LOGE(TAG, "Octal Flash option selected, but EFUSE not configured!");
375 abort();
376 }
377 #endif
378 esp_mspi_pin_init();
379 // For Octal flash, it's hard to implement a read_id function in OPI mode for all vendors.
380 // So we have to read it here in SPI mode, before entering the OPI mode.
381 bootloader_flash_update_id();
382 /**
383 * This function initialise the Flash chip to the user-defined settings.
384 *
385 * In bootloader, we only init Flash (and MSPI) to a preliminary state, for being flexible to
386 * different chips.
387 * In this stage, we re-configure the Flash (and MSPI) to required configuration
388 */
389 spi_flash_init_chip_state();
390 #if CONFIG_IDF_TARGET_ESP32S3
391 //On other chips, this feature is not provided by HW, or hasn't been tested yet.
392 spi_timing_flash_tuning();
393 #endif
394
395 bootloader_init_mem();
396 #if CONFIG_SPIRAM_BOOT_INIT
397 if (esp_spiram_init() != ESP_OK) {
398 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
399 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
400 ESP_EARLY_LOGE(TAG, "Failed to init external RAM, needed for external .bss segment");
401 abort();
402 #endif
403 #endif
404
405 #if CONFIG_SPIRAM_IGNORE_NOTFOUND
406 ESP_EARLY_LOGI(TAG, "Failed to init external RAM; continuing without it.");
407 g_spiram_ok = false;
408 #else
409 ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
410 abort();
411 #endif
412 }
413 if (g_spiram_ok) {
414 esp_spiram_init_cache();
415 }
416 #endif
417
418 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
419 s_cpu_up[0] = true;
420 #endif
421
422 ESP_EARLY_LOGI(TAG, "Pro cpu up.");
423
424 #if SOC_CPU_CORES_NUM > 1 // there is no 'single-core mode' for natively single-core processors
425 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
426 start_other_core();
427 #else
428 ESP_EARLY_LOGI(TAG, "Single core mode");
429 #if CONFIG_IDF_TARGET_ESP32
430 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); // stop the other core
431 #elif CONFIG_IDF_TARGET_ESP32S3
432 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
433 #if SOC_APPCPU_HAS_CLOCK_GATING_BUG
434 /* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETTING
435 signals to ensure that the App core stops running in single-core mode. */
436 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
437 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
438 #endif
439 #endif // CONFIG_IDF_TARGET_ESP32
440 #endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
441 #endif // SOC_CPU_CORES_NUM > 1
442
443 #if CONFIG_SPIRAM_MEMTEST
444 if (g_spiram_ok) {
445 bool ext_ram_ok = esp_spiram_test();
446 if (!ext_ram_ok) {
447 ESP_EARLY_LOGE(TAG, "External RAM failed memory test!");
448 abort();
449 }
450 }
451 #endif
452
453 #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
454 extern void instruction_flash_page_info_init(void);
455 instruction_flash_page_info_init();
456 #endif
457 #if CONFIG_SPIRAM_RODATA
458 extern void rodata_flash_page_info_init(void);
459 rodata_flash_page_info_init();
460 #endif
461
462 #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
463 extern void esp_spiram_enable_instruction_access(void);
464 esp_spiram_enable_instruction_access();
465 #endif
466 #if CONFIG_SPIRAM_RODATA
467 extern void esp_spiram_enable_rodata_access(void);
468 esp_spiram_enable_rodata_access();
469 #endif
470
471 #if CONFIG_IDF_TARGET_ESP32S3
472 int s_instr_flash2spiram_off = 0;
473 int s_rodata_flash2spiram_off = 0;
474 #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
475 s_instr_flash2spiram_off = instruction_flash2spiram_offset();
476 #endif
477 #if CONFIG_SPIRAM_RODATA
478 s_rodata_flash2spiram_off = rodata_flash2spiram_offset();
479 #endif
480
481 extern void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num, uint32_t rodata_start, uint32_t rodata_end, int i_off, int ro_off);
482 Cache_Set_IDROM_MMU_Info(cache_mmu_irom_size / sizeof(uint32_t), \
483 cache_mmu_drom_size / sizeof(uint32_t), \
484 (uint32_t)&_rodata_reserved_start, \
485 (uint32_t)&_rodata_reserved_end, \
486 s_instr_flash2spiram_off, \
487 s_rodata_flash2spiram_off);
488 #endif
489
490 #if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S2_DATA_CACHE_WRAP || \
491 CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S3_DATA_CACHE_WRAP
492 uint32_t icache_wrap_enable = 0, dcache_wrap_enable = 0;
493 #if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP
494 icache_wrap_enable = 1;
495 #endif
496 #if CONFIG_ESP32S2_DATA_CACHE_WRAP || CONFIG_ESP32S3_DATA_CACHE_WRAP
497 dcache_wrap_enable = 1;
498 #endif
499 extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable, uint32_t dcache_wrap_enable);
500 esp_enable_cache_wrap(icache_wrap_enable, dcache_wrap_enable);
501 #endif
502
503 #if CONFIG_ESP32S3_DATA_CACHE_16KB
504 Cache_Invalidate_DCache_All();
505 Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000);
506 #endif
507
508 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
509 memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
510 #endif
511
512 //Enable trace memory and immediately start trace.
513 #if CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX || CONFIG_ESP32S3_TRAX
514 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S3
515 #if CONFIG_ESP32_TRAX_TWOBANKS || CONFIG_ESP32S3_TRAX_TWOBANKS
516 trax_enable(TRAX_ENA_PRO_APP);
517 #else
518 trax_enable(TRAX_ENA_PRO);
519 #endif
520 #elif CONFIG_IDF_TARGET_ESP32S2
521 trax_enable(TRAX_ENA_PRO);
522 #endif
523 trax_start_trace(TRAX_DOWNCOUNT_WORDS);
524 #endif // CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX || CONFIG_ESP32S3_TRAX
525
526 esp_clk_init();
527 esp_perip_clk_init();
528
529 // Now that the clocks have been set-up, set the startup time from RTC
530 // and default RTC-backed system time provider.
531 g_startup_time = esp_rtc_get_time_us();
532
533 // Clear interrupt matrix for PRO CPU core
534 core_intr_matrix_clear();
535
536 #ifndef CONFIG_IDF_ENV_FPGA // TODO: on FPGA it should be possible to configure this, not currently working with APB_CLK_FREQ changed
537 #ifdef CONFIG_ESP_CONSOLE_UART
538 uint32_t clock_hz = rtc_clk_apb_freq_get();
539 #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
540 clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM
541 #endif
542 esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
543 esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
544 #endif
545 #endif
546
547 #if SOC_RTCIO_HOLD_SUPPORTED
548 rtcio_hal_unhold_all();
549 #else
550 gpio_hal_force_unhold_all();
551 #endif
552
553 esp_cache_err_int_init();
554
555 #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE && !CONFIG_ESP_SYSTEM_MEMPROT_TEST
556 // Memprot cannot be locked during OS startup as the lock-on prevents any PMS changes until a next reboot
557 // If such a situation appears, it is likely an malicious attempt to bypass the system safety setup -> print error & reset
558
559 #if CONFIG_IDF_TARGET_ESP32S2
560 if (esp_memprot_is_locked_any()) {
561 #else
562 bool is_locked = false;
563 if (esp_mprot_is_conf_locked_any(&is_locked) != ESP_OK || is_locked) {
564 #endif
565 ESP_EARLY_LOGE(TAG, "Memprot feature locked after the system reset! Potential safety corruption, rebooting.");
566 esp_restart_noos_dig();
567 }
568
569 //default configuration of PMS Memprot
570 esp_err_t memp_err = ESP_OK;
571 #if CONFIG_IDF_TARGET_ESP32S2 //specific for ESP32S2 unless IDF-3024 is merged
572 #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
573 memp_err = esp_memprot_set_prot(PANIC_HNDL_ON, MEMPROT_LOCK, NULL);
574 #else
575 memp_err = esp_memprot_set_prot(PANIC_HNDL_ON, MEMPROT_UNLOCK, NULL);
576 #endif
577 #else //CONFIG_IDF_TARGET_ESP32S2 specific end
578 esp_memp_config_t memp_cfg = ESP_MEMPROT_DEFAULT_CONFIG();
579 #if !CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
580 memp_cfg.lock_feature = false;
581 #endif
582 memp_err = esp_mprot_set_prot(&memp_cfg);
583 #endif //other IDF_TARGETS end
584
585 if (memp_err != ESP_OK) {
586 ESP_EARLY_LOGE(TAG, "Failed to set Memprot feature (0x%08X: %s), rebooting.", memp_err, esp_err_to_name(memp_err));
587 esp_restart_noos_dig();
588 }
589 #endif //CONFIG_ESP_SYSTEM_MEMPROT_FEATURE && !CONFIG_ESP_SYSTEM_MEMPROT_TEST
590
591 // Read the application binary image header. This will also decrypt the header if the image is encrypted.
592 __attribute__((unused)) esp_image_header_t fhdr = {0};
593 #ifdef CONFIG_APP_BUILD_TYPE_ELF_RAM
594 fhdr.spi_mode = ESP_IMAGE_SPI_MODE_DIO;
595 fhdr.spi_speed = ESP_IMAGE_SPI_SPEED_40M;
596 fhdr.spi_size = ESP_IMAGE_FLASH_SIZE_4MB;
597
598 extern void esp_rom_spiflash_attach(uint32_t, bool);
599 esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false);
600 bootloader_flash_unlock();
601 #else
602 // This assumes that DROM is the first segment in the application binary, i.e. that we can read
603 // the binary header through cache by accessing SOC_DROM_LOW address.
604 memcpy(&fhdr, (void *) SOC_DROM_LOW, sizeof(fhdr));
605 #endif // CONFIG_APP_BUILD_TYPE_ELF_RAM
606
607 #if CONFIG_IDF_TARGET_ESP32
608 #if !CONFIG_SPIRAM_BOOT_INIT
609 // If psram is uninitialized, we need to improve some flash configuration.
610 bootloader_flash_clock_config(&fhdr);
611 bootloader_flash_gpio_config(&fhdr);
612 bootloader_flash_dummy_config(&fhdr);
613 bootloader_flash_cs_timing_config();
614 #endif //!CONFIG_SPIRAM_BOOT_INIT
615 #endif //CONFIG_IDF_TARGET_ESP32
616
617 #if CONFIG_SPI_FLASH_SIZE_OVERRIDE
618 int app_flash_size = esp_image_get_flash_size(fhdr.spi_size);
619 if (app_flash_size < 1 * 1024 * 1024) {
620 ESP_LOGE(TAG, "Invalid flash size in app image header.");
621 abort();
622 }
623 bootloader_flash_update_size(app_flash_size);
624 #endif //CONFIG_SPI_FLASH_SIZE_OVERRIDE
625
626 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
627 s_cpu_inited[0] = true;
628
629 volatile bool cpus_inited = false;
630
631 while (!cpus_inited) {
632 cpus_inited = true;
633 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
634 cpus_inited &= s_cpu_inited[i];
635 }
636 esp_rom_delay_us(100);
637 }
638 #endif
639
640 #ifdef ROM_LOG_MODE
641 esp_efuse_set_rom_log_scheme(ROM_LOG_MODE);
642 #endif
643
644 SYS_STARTUP_FN();
645 }
646
