1 /*
2 * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include <stdlib.h>
9 #include "soc/soc.h"
10 #include "soc/rtc.h"
11 #include "soc/rtc_cntl_reg.h"
12 #include "soc/syscon_reg.h"
13 #include "soc/rtc.h"
14 #include "soc/i2s_reg.h"
15 #include "soc/bb_reg.h"
16 #include "soc/nrx_reg.h"
17 #include "soc/fe_reg.h"
18 #include "soc/timer_group_reg.h"
19 #include "soc/system_reg.h"
20 #include "soc/rtc.h"
21 #include "esp32c3/rom/ets_sys.h"
22 #include "esp32c3/rom/rtc.h"
23 #include "regi2c_ctrl.h"
24 #include "esp_efuse.h"
25
26 /**
27 * Configure whether certain peripherals are powered down in deep sleep
28 * @param cfg power down flags as rtc_sleep_pu_config_t structure
29 */
rtc_sleep_pu(rtc_sleep_pu_config_t cfg)30 void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
31 {
32 REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
33 REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
34 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu);
35 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
36 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu);
37 REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
38 REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
39 REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
40 REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu);
41 REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
42 REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
43 REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
44 if (cfg.sram_fpu) {
45 REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
46 } else {
47 REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, 0);
48 }
49 if (cfg.rom_ram_fpu) {
50 REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, SYSCON_ROM_POWER_UP);
51 } else {
52 REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, 0);
53 }
54 }
55
rtc_sleep_init(rtc_sleep_config_t cfg)56 void rtc_sleep_init(rtc_sleep_config_t cfg)
57 {
58 if (cfg.lslp_mem_inf_fpu) {
59 rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
60 rtc_sleep_pu(pu_cfg);
61 }
62 if (cfg.wifi_pd_en) {
63 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
64 } else {
65 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
66 }
67 if (cfg.bt_pd_en) {
68 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
69 } else {
70 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
71 }
72 if (cfg.cpu_pd_en) {
73 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN);
74 } else {
75 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN);
76 }
77 if (cfg.dig_peri_pd_en) {
78 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
79 } else {
80 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
81 }
82
83 REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT);
84 REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT);
85 REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP,
86 (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT);
87 REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT);
88 REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP,
89 (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT);
90 if (cfg.deep_slp) {
91 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
92 CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
93 unsigned atten_deep_sleep = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
94 #if CONFIG_ESP32C3_REV_MIN < 3
95 if (esp_efuse_get_chip_ver() < 3) {
96 atten_deep_sleep = 0; /* workaround for deep sleep issue in high temp on ECO2 and below */
97 }
98 #endif
99 REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, atten_deep_sleep);
100 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
101 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
102 RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
103 RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
104 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
105 } else {
106 SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN);
107 REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
108 SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
109 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
110 REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP,
111 cfg.int_8m_pd_en ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP);
112 }
113
114 //Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK.
115 if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) {
116 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD);
117 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
118 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
119 } else {
120 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
121 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
122 }
123
124 /* enable VDDSDIO control by state machine */
125 REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
126 REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);
127
128 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp);
129 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp);
130
131 REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
132 REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
133
134 REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
135 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
136 }
137
rtc_sleep_low_init(uint32_t slowclk_period)138 void rtc_sleep_low_init(uint32_t slowclk_period)
139 {
140 // set 5 PWC state machine times to fit in main state machine time
141 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
142 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
143 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
144 }
145
rtc_sleep_set_wakeup_time(uint64_t t)146 void rtc_sleep_set_wakeup_time(uint64_t t)
147 {
148 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
149 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
150 }
151
152 static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);
153
rtc_sleep_start(uint32_t wakeup_opt,uint32_t reject_opt,uint32_t lslp_mem_inf_fpu)154 uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
155 {
156 REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
157 REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt);
158
159 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
160 RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
161
162 /* Start entry into sleep mode */
163 SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
164
165 while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG,
166 RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) {
167 ;
168 }
169
170 return rtc_sleep_finish(lslp_mem_inf_fpu);
171 }
172
173 #define STR2(X) #X
174 #define STR(X) STR2(X)
175
rtc_deep_sleep_start(uint32_t wakeup_opt,uint32_t reject_opt)176 uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
177 {
178 REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
179 WRITE_PERI_REG(RTC_CNTL_SLP_REJECT_CONF_REG, reject_opt);
180
181 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
182 RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
183
184 /* Calculate RTC Fast Memory CRC (for wake stub) & go to deep sleep
185
186 Because we may be running from RTC memory as stack, we can't easily call any
187 functions to do this (as registers will spill to stack, corrupting the CRC).
188
189 Instead, load all the values we need into registers then use register ops only to calculate
190 the CRC value, write it to the RTC CRC value register, and immediately go into deep sleep.
191 */
192
193 /* Values used to set the SYSTEM_RTC_FASTMEM_CONFIG_REG value */
194 const unsigned CRC_START_ADDR = 0;
195 const unsigned CRC_LEN = 0x7ff;
196
197 __asm__ volatile(
198 /* Start CRC calculation */
199 "sw %1, 0(%0)\n" // set RTC_MEM_CRC_ADDR & RTC_MEM_CRC_LEN
200 "or t0, %1, %2\n"
201 "sw t0, 0(%0)\n" // set RTC_MEM_CRC_START
202
203 /* Wait for the CRC calculation to finish */
204 ".Lwaitcrc:\n"
205 "fence\n"
206 "lw t0, 0(%0)\n"
207 "li t1, "STR(SYSTEM_RTC_MEM_CRC_FINISH)"\n"
208 "and t0, t0, t1\n"
209 "beqz t0, .Lwaitcrc\n"
210 "not %2, %2\n" // %2 -> ~DPORT_RTC_MEM_CRC_START
211 "and t0, t0, %2\n"
212 "sw t0, 0(%0)\n" // clear RTC_MEM_CRC_START
213 "fence\n"
214 "not %2, %2\n" // %2 -> DPORT_RTC_MEM_CRC_START, probably unnecessary but gcc assumes inputs unchanged
215
216 /* Store the calculated value in RTC_MEM_CRC_REG */
217 "lw t0, 0(%3)\n"
218 "sw t0, 0(%4)\n"
219 "fence\n"
220
221 /* Set register bit to go into deep sleep */
222 "lw t0, 0(%5)\n"
223 "or t0, t0, %6\n"
224 "sw t0, 0(%5)\n"
225 "fence\n"
226
227 /* Wait for sleep reject interrupt (never finishes if successful) */
228 ".Lwaitsleep:"
229 "fence\n"
230 "lw t0, 0(%7)\n"
231 "and t0, t0, %8\n"
232 "beqz t0, .Lwaitsleep\n"
233
234 :
235 :
236 "r" (SYSTEM_RTC_FASTMEM_CONFIG_REG), // %0
237 "r" ( (CRC_START_ADDR << SYSTEM_RTC_MEM_CRC_START_S)
238 | (CRC_LEN << SYSTEM_RTC_MEM_CRC_LEN_S)), // %1
239 "r" (SYSTEM_RTC_MEM_CRC_START), // %2
240 "r" (SYSTEM_RTC_FASTMEM_CRC_REG), // %3
241 "r" (RTC_MEMORY_CRC_REG), // %4
242 "r" (RTC_CNTL_STATE0_REG), // %5
243 "r" (RTC_CNTL_SLEEP_EN), // %6
244 "r" (RTC_CNTL_INT_RAW_REG), // %7
245 "r" (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) // %8
246 : "t0", "t1" // working registers
247 );
248
249 return rtc_sleep_finish(0);
250 }
251
rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)252 static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)
253 {
254 /* In deep sleep mode, we never get here */
255 uint32_t reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW);
256 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
257 RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
258
259 /* restore config if it is a light sleep */
260 if (lslp_mem_inf_fpu) {
261 rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
262 rtc_sleep_pu(pu_cfg);
263 }
264 return reject;
265 }
266
