1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdbool.h>
8 #include <stdint.h>
9 #include <stddef.h>
10 #include <stdlib.h>
11 #include "esp32/rom/ets_sys.h" // for ets_update_cpu_frequency
12 #include "esp32/rom/rtc.h"
13 #include "esp_rom_gpio.h"
14 #include "esp_efuse.h"
15 #include "soc/rtc.h"
16 #include "soc/rtc_periph.h"
17 #include "soc/sens_periph.h"
18 #include "soc/dport_reg.h"
19 #include "soc/efuse_periph.h"
20 #include "soc/syscon_reg.h"
21 #include "soc/gpio_struct.h"
22 #include "hal/cpu_hal.h"
23 #include "hal/gpio_ll.h"
24 #include "esp_rom_sys.h"
25 #include "regi2c_ctrl.h"
26 #include "soc_log.h"
27 #include "sdkconfig.h"
28 #include "rtc_clk_common.h"
29
30 /* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting */
31 #define RTC_FAST_CLK_FREQ_8M 8500000
32 #define RTC_SLOW_CLK_FREQ_150K 150000
33 #define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256)
34 #define RTC_SLOW_CLK_FREQ_32K 32768
35
36 /* BBPLL configuration values */
37 #define BBPLL_ENDIV5_VAL_320M 0x43
38 #define BBPLL_BBADC_DSMP_VAL_320M 0x84
39 #define BBPLL_ENDIV5_VAL_480M 0xc3
40 #define BBPLL_BBADC_DSMP_VAL_480M 0x74
41 #define BBPLL_IR_CAL_DELAY_VAL 0x18
42 #define BBPLL_IR_CAL_EXT_CAP_VAL 0x20
43 #define BBPLL_OC_ENB_FCAL_VAL 0x9a
44 #define BBPLL_OC_ENB_VCON_VAL 0x00
45 #define BBPLL_BBADC_CAL_7_0_VAL 0x00
46
47 #define APLL_SDM_STOP_VAL_1 0x09
48 #define APLL_SDM_STOP_VAL_2_REV0 0x69
49 #define APLL_SDM_STOP_VAL_2_REV1 0x49
50
51 #define APLL_CAL_DELAY_1 0x0f
52 #define APLL_CAL_DELAY_2 0x3f
53 #define APLL_CAL_DELAY_3 0x1f
54
55 #define XTAL_32K_DAC_VAL 1
56 #define XTAL_32K_DRES_VAL 3
57 #define XTAL_32K_DBIAS_VAL 0
58
59 #define XTAL_32K_BOOTSTRAP_DAC_VAL 3
60 #define XTAL_32K_BOOTSTRAP_DRES_VAL 3
61 #define XTAL_32K_BOOTSTRAP_DBIAS_VAL 0
62 #define XTAL_32K_BOOTSTRAP_TIME_US 7
63
64 #define XTAL_32K_EXT_DAC_VAL 2
65 #define XTAL_32K_EXT_DRES_VAL 3
66 #define XTAL_32K_EXT_DBIAS_VAL 1
67
68 /* Delays for various clock sources to be enabled/switched.
69 * All values are in microseconds.
70 * TODO: some of these are excessive, and should be reduced.
71 */
72 #define DELAY_PLL_DBIAS_RAISE 3
73 #define DELAY_PLL_ENABLE_WITH_150K 80
74 #define DELAY_PLL_ENABLE_WITH_32K 160
75 #define DELAY_FAST_CLK_SWITCH 3
76 #define DELAY_SLOW_CLK_SWITCH 300
77 #define DELAY_8M_ENABLE 50
78
79 /* Core voltage needs to be increased in two cases:
80 * 1. running at 240 MHz
81 * 2. running with 80MHz Flash frequency
82 *
83 * There is a record in efuse which indicates the proper voltage for these two cases.
84 */
85 #define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV)))
86 #ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
87 #define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT
88 #else
89 #define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
90 #endif
91 #define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT
92 #define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
93 #define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
94
95 #define RTC_PLL_FREQ_320M 320
96 #define RTC_PLL_FREQ_480M 480
97 #define DELAY_RTC_CLK_SWITCH 5
98
99 static void rtc_clk_cpu_freq_to_8m(void);
100 static void rtc_clk_bbpll_disable(void);
101 static void rtc_clk_bbpll_enable(void);
102 static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz);
103
104 // Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
105 static uint32_t s_cur_pll_freq;
106
107 static const char* TAG = "rtc_clk";
108
rtc_clk_32k_enable_common(int dac,int dres,int dbias)109 static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
110 {
111 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG,
112 RTC_IO_X32P_RDE | RTC_IO_X32P_RUE | RTC_IO_X32N_RUE |
113 RTC_IO_X32N_RDE | RTC_IO_X32N_FUN_IE | RTC_IO_X32P_FUN_IE);
114 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
115 /* Set the parameters of xtal
116 dac --> current
117 dres --> resistance
118 dbias --> bais voltage
119 */
120 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DAC_XTAL_32K, dac);
121 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, dres);
122 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, dbias);
123
124 #ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
125 uint8_t chip_ver = esp_efuse_get_chip_ver();
126 // version0 and version1 need provide additional current to external XTAL.
127 if(chip_ver == 0 || chip_ver == 1) {
128 /* TOUCH sensor can provide additional current to external XTAL.
129 In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */
130 SET_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
131 /* Tie PAD Touch8 to VDD
132 NOTE: TOUCH8 and TOUCH9 register settings are reversed except for DAC, so we set RTC_IO_TOUCH_PAD9_REG here instead*/
133 SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_TIE_OPT_M);
134 /* Set the current used to compensate TOUCH PAD8 */
135 SET_PERI_REG_BITS(RTC_IO_TOUCH_PAD8_REG, RTC_IO_TOUCH_PAD8_DAC, 4, RTC_IO_TOUCH_PAD8_DAC_S);
136 /* Power up TOUCH8
137 So the Touch DAC start to drive some current from VDD to TOUCH8(which is also XTAL-N)*/
138 SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
139 }
140 #elif defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2
141 uint8_t chip_ver = esp_efuse_get_chip_ver();
142 if(chip_ver == 0 || chip_ver == 1) {
143 /* TOUCH sensor can provide additional current to external XTAL.
144 In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */
145 SET_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
146 SET_PERI_REG_BITS(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_DCUR, 3, RTC_IO_TOUCH_DCUR_S);
147 CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_START_FSM_EN_M);
148 /* Tie PAD Touch8 to VDD
149 NOTE: TOUCH8 and TOUCH9 register settings are reversed except for DAC, so we set RTC_IO_TOUCH_PAD9_REG here instead
150 */
151 SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_TIE_OPT_M);
152 /* Set the current used to compensate TOUCH PAD8 */
153 SET_PERI_REG_BITS(RTC_IO_TOUCH_PAD8_REG, RTC_IO_TOUCH_PAD8_DAC, 1, RTC_IO_TOUCH_PAD8_DAC_S);
154 /* Power up TOUCH8
155 So the Touch DAC start to drive some current from VDD to TOUCH8(which is also XTAL-N)
156 */
157 SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
158 CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_START_M);
159 }
160 #endif
161 /* Power up external xtal */
162 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M);
163 }
164
rtc_clk_32k_enable(bool enable)165 void rtc_clk_32k_enable(bool enable)
166 {
167 if (enable) {
168 rtc_clk_32k_enable_common(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DBIAS_VAL);
169 } else {
170 /* Disable X32N and X32P pad drive external xtal */
171 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M);
172 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
173
174 #ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
175 uint8_t chip_ver = esp_efuse_get_chip_ver();
176 if(chip_ver == 0 || chip_ver == 1) {
177 /* Power down TOUCH */
178 CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
179 }
180 #elif defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2
181 uint8_t chip_ver = esp_efuse_get_chip_ver();
182 if(chip_ver == 0 || chip_ver == 1) {
183 /* Power down TOUCH */
184 CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
185 SET_PERI_REG_BITS(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_DCUR, 0, RTC_IO_TOUCH_DCUR_S);
186 CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
187 SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_START_FSM_EN_M);
188 }
189 #endif
190 }
191 }
192
rtc_clk_32k_enable_external(void)193 void rtc_clk_32k_enable_external(void)
194 {
195 rtc_clk_32k_enable_common(XTAL_32K_EXT_DAC_VAL, XTAL_32K_EXT_DRES_VAL, XTAL_32K_EXT_DBIAS_VAL);
196 }
197
198 /* Helping external 32kHz crystal to start up.
199 * External crystal connected to outputs GPIO32 GPIO33.
200 * Forms N pulses with a frequency of about 32KHz on the outputs of the crystal.
201 */
rtc_clk_32k_bootstrap(uint32_t cycle)202 void rtc_clk_32k_bootstrap(uint32_t cycle)
203 {
204 if (cycle){
205 const uint32_t pin_32 = 32;
206 const uint32_t pin_33 = 33;
207
208 esp_rom_gpio_pad_select_gpio(pin_32);
209 esp_rom_gpio_pad_select_gpio(pin_33);
210 gpio_ll_output_enable(&GPIO, pin_32);
211 gpio_ll_output_enable(&GPIO, pin_33);
212 gpio_ll_set_level(&GPIO, pin_32, 1);
213 gpio_ll_set_level(&GPIO, pin_33, 0);
214
215 const uint32_t delay_us = (1000000 / RTC_SLOW_CLK_FREQ_32K / 2);
216 while(cycle){
217 gpio_ll_set_level(&GPIO, pin_32, 1);
218 gpio_ll_set_level(&GPIO, pin_33, 0);
219 esp_rom_delay_us(delay_us);
220 gpio_ll_set_level(&GPIO, pin_33, 1);
221 gpio_ll_set_level(&GPIO, pin_32, 0);
222 esp_rom_delay_us(delay_us);
223 cycle--;
224 }
225 // disable pins
226 gpio_ll_output_disable(&GPIO, pin_32);
227 gpio_ll_output_disable(&GPIO, pin_33);
228 }
229
230 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
231 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_RUE | RTC_IO_X32N_RDE);
232 esp_rom_delay_us(XTAL_32K_BOOTSTRAP_TIME_US);
233
234 rtc_clk_32k_enable_common(XTAL_32K_BOOTSTRAP_DAC_VAL,
235 XTAL_32K_BOOTSTRAP_DRES_VAL, XTAL_32K_BOOTSTRAP_DBIAS_VAL);
236 }
237
rtc_clk_32k_enabled(void)238 bool rtc_clk_32k_enabled(void)
239 {
240 return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K) != 0;
241 }
242
rtc_clk_8m_enable(bool clk_8m_en,bool d256_en)243 void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
244 {
245 if (clk_8m_en) {
246 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
247 /* no need to wait once enabled by software */
248 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1);
249 if (d256_en) {
250 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
251 } else {
252 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
253 }
254 esp_rom_delay_us(DELAY_8M_ENABLE);
255 } else {
256 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
257 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
258 }
259 }
260
rtc_clk_8m_enabled(void)261 bool rtc_clk_8m_enabled(void)
262 {
263 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
264 }
265
rtc_clk_8md256_enabled(void)266 bool rtc_clk_8md256_enabled(void)
267 {
268 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
269 }
270
rtc_clk_apll_enable(bool enable,uint32_t sdm0,uint32_t sdm1,uint32_t sdm2,uint32_t o_div)271 void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div)
272 {
273 REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1);
274 REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0);
275
276 if (!enable &&
277 REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) != RTC_CNTL_SOC_CLK_SEL_PLL) {
278 REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
279 } else {
280 REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
281 }
282
283 if (enable) {
284 uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1;
285 uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0);
286 if (is_rev0) {
287 sdm0 = 0;
288 sdm1 = 0;
289 sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0;
290 }
291 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM2, sdm2);
292 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM0, sdm0);
293 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM1, sdm1);
294 REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
295 REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, sdm_stop_val_2);
296 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
297
298 /* calibration */
299 REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
300 REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
301 REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
302
303 /* wait for calibration end */
304 while (!(REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END))) {
305 /* use esp_rom_delay_us so the RTC bus doesn't get flooded */
306 esp_rom_delay_us(1);
307 }
308 }
309 }
310
rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)311 void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
312 {
313 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
314
315 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
316 (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
317
318 esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH);
319 }
320
rtc_clk_slow_freq_get(void)321 rtc_slow_freq_t rtc_clk_slow_freq_get(void)
322 {
323 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
324 }
325
rtc_clk_slow_freq_get_hz(void)326 uint32_t rtc_clk_slow_freq_get_hz(void)
327 {
328 switch(rtc_clk_slow_freq_get()) {
329 case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
330 case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K;
331 case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256;
332 }
333 return 0;
334 }
335
rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)336 void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)
337 {
338 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq);
339 esp_rom_delay_us(DELAY_FAST_CLK_SWITCH);
340 }
341
rtc_clk_fast_freq_get(void)342 rtc_fast_freq_t rtc_clk_fast_freq_get(void)
343 {
344 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
345 }
346
rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq,int pll_freq)347 void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
348 {
349 uint8_t div_ref;
350 uint8_t div7_0;
351 uint8_t div10_8;
352 uint8_t lref;
353 uint8_t dcur;
354 uint8_t bw;
355
356 if (pll_freq == RTC_PLL_FREQ_320M) {
357 /* Raise the voltage, if needed */
358 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
359 /* Configure 320M PLL */
360 switch (xtal_freq) {
361 case RTC_XTAL_FREQ_40M:
362 div_ref = 0;
363 div7_0 = 32;
364 div10_8 = 0;
365 lref = 0;
366 dcur = 6;
367 bw = 3;
368 break;
369 case RTC_XTAL_FREQ_26M:
370 div_ref = 12;
371 div7_0 = 224;
372 div10_8 = 4;
373 lref = 1;
374 dcur = 0;
375 bw = 1;
376 break;
377 case RTC_XTAL_FREQ_24M:
378 div_ref = 11;
379 div7_0 = 224;
380 div10_8 = 4;
381 lref = 1;
382 dcur = 0;
383 bw = 1;
384 break;
385 default:
386 div_ref = 12;
387 div7_0 = 224;
388 div10_8 = 4;
389 lref = 0;
390 dcur = 0;
391 bw = 0;
392 break;
393 }
394 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_320M);
395 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_320M);
396 } else {
397 /* Raise the voltage */
398 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
399 esp_rom_delay_us(DELAY_PLL_DBIAS_RAISE);
400 /* Configure 480M PLL */
401 switch (xtal_freq) {
402 case RTC_XTAL_FREQ_40M:
403 div_ref = 0;
404 div7_0 = 28;
405 div10_8 = 0;
406 lref = 0;
407 dcur = 6;
408 bw = 3;
409 break;
410 case RTC_XTAL_FREQ_26M:
411 div_ref = 12;
412 div7_0 = 144;
413 div10_8 = 4;
414 lref = 1;
415 dcur = 0;
416 bw = 1;
417 break;
418 case RTC_XTAL_FREQ_24M:
419 div_ref = 11;
420 div7_0 = 144;
421 div10_8 = 4;
422 lref = 1;
423 dcur = 0;
424 bw = 1;
425 break;
426 default:
427 div_ref = 12;
428 div7_0 = 224;
429 div10_8 = 4;
430 lref = 0;
431 dcur = 0;
432 bw = 0;
433 break;
434 }
435 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_480M);
436 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_480M);
437 }
438
439 uint8_t i2c_bbpll_lref = (lref << 7) | (div10_8 << 4) | (div_ref);
440 uint8_t i2c_bbpll_div_7_0 = div7_0;
441 uint8_t i2c_bbpll_dcur = (bw << 6) | dcur;
442 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
443 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
444 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
445 uint32_t delay_pll_en = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ?
446 DELAY_PLL_ENABLE_WITH_150K : DELAY_PLL_ENABLE_WITH_32K;
447 esp_rom_delay_us(delay_pll_en);
448 s_cur_pll_freq = pll_freq;
449 }
450
451 /**
452 * Switch to XTAL frequency. Does not disable the PLL.
453 */
rtc_clk_cpu_freq_to_xtal(int freq,int div)454 void rtc_clk_cpu_freq_to_xtal(int freq, int div)
455 {
456 ets_update_cpu_frequency(freq);
457 /* set divider from XTAL to APB clock */
458 REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, div - 1);
459 /* adjust ref_tick */
460 REG_WRITE(SYSCON_XTAL_TICK_CONF_REG, freq * MHZ / REF_CLK_FREQ - 1);
461 /* switch clock source */
462 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
463 rtc_clk_apb_freq_update(freq * MHZ);
464 /* lower the voltage */
465 if (freq <= 2) {
466 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M);
467 } else {
468 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
469 }
470 }
471
rtc_clk_cpu_freq_to_8m(void)472 static void rtc_clk_cpu_freq_to_8m(void)
473 {
474 ets_update_cpu_frequency(8);
475 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
476 REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, 0);
477 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M);
478 rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);
479 }
480
rtc_clk_bbpll_disable(void)481 static void rtc_clk_bbpll_disable(void)
482 {
483 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
484 RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
485 RTC_CNTL_BBPLL_I2C_FORCE_PD);
486 s_cur_pll_freq = 0;
487
488 /* is APLL under force power down? */
489 uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
490 if (apll_fpd) {
491 /* then also power down the internal I2C bus */
492 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
493 }
494 }
495
rtc_clk_bbpll_enable(void)496 static void rtc_clk_bbpll_enable(void)
497 {
498 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
499 RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
500 RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
501
502 /* reset BBPLL configuration */
503 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
504 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
505 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
506 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
507 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
508 }
509
510 /**
511 * Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL.
512 * PLL must already be enabled.
513 * @param cpu_freq new CPU frequency
514 */
rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)515 static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
516 {
517 int dbias = DIG_DBIAS_80M_160M;
518 int per_conf = DPORT_CPUPERIOD_SEL_80;
519 if (cpu_freq_mhz == 80) {
520 /* nothing to do */
521 } else if (cpu_freq_mhz == 160) {
522 per_conf = DPORT_CPUPERIOD_SEL_160;
523 } else if (cpu_freq_mhz == 240) {
524 dbias = DIG_DBIAS_240M;
525 per_conf = DPORT_CPUPERIOD_SEL_240;
526 } else {
527 SOC_LOGE(TAG, "invalid frequency");
528 abort();
529 }
530 DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, per_conf);
531 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
532 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
533 rtc_clk_apb_freq_update(80 * MHZ);
534 ets_update_cpu_frequency(cpu_freq_mhz);
535 rtc_clk_wait_for_slow_cycle();
536 }
537
rtc_clk_cpu_freq_set_xtal(void)538 void rtc_clk_cpu_freq_set_xtal(void)
539 {
540 int freq_mhz = (int) rtc_clk_xtal_freq_get();
541
542 rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
543 rtc_clk_wait_for_slow_cycle();
544 rtc_clk_bbpll_disable();
545 }
546
rtc_clk_cpu_freq_to_config(rtc_cpu_freq_t cpu_freq,rtc_cpu_freq_config_t * out_config)547 void rtc_clk_cpu_freq_to_config(rtc_cpu_freq_t cpu_freq, rtc_cpu_freq_config_t* out_config)
548 {
549 uint32_t source_freq_mhz;
550 rtc_cpu_freq_src_t source;
551 uint32_t freq_mhz;
552 uint32_t divider;
553
554 switch (cpu_freq) {
555 case RTC_CPU_FREQ_XTAL:
556 case RTC_CPU_FREQ_2M:
557 source_freq_mhz = rtc_clk_xtal_freq_get();
558 source = RTC_CPU_FREQ_SRC_XTAL;
559 if (cpu_freq == RTC_CPU_FREQ_2M) {
560 freq_mhz = 2;
561 divider = source_freq_mhz / 2;
562 } else {
563 freq_mhz = source_freq_mhz;
564 divider = 1;
565 }
566 break;
567 case RTC_CPU_FREQ_80M:
568 source = RTC_CPU_FREQ_SRC_PLL;
569 source_freq_mhz = RTC_PLL_FREQ_320M;
570 divider = 4;
571 freq_mhz = 80;
572 break;
573 case RTC_CPU_FREQ_160M:
574 source = RTC_CPU_FREQ_SRC_PLL;
575 source_freq_mhz = RTC_PLL_FREQ_320M;
576 divider = 2;
577 freq_mhz = 160;
578 break;
579 case RTC_CPU_FREQ_240M:
580 source = RTC_CPU_FREQ_SRC_PLL;
581 source_freq_mhz = RTC_PLL_FREQ_480M;
582 divider = 2;
583 freq_mhz = 240;
584 break;
585 default:
586 SOC_LOGE(TAG, "invalid rtc_cpu_freq_t value");
587 abort();
588 }
589
590 *out_config = (rtc_cpu_freq_config_t) {
591 .source = source,
592 .source_freq_mhz = source_freq_mhz,
593 .div = divider,
594 .freq_mhz = freq_mhz
595 };
596 }
597
rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz,rtc_cpu_freq_config_t * out_config)598 bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* out_config)
599 {
600 uint32_t source_freq_mhz;
601 rtc_cpu_freq_src_t source;
602 uint32_t divider;
603 uint32_t real_freq_mhz;
604
605 uint32_t xtal_freq = (uint32_t) rtc_clk_xtal_freq_get();
606 if (freq_mhz <= xtal_freq) {
607 divider = xtal_freq / freq_mhz;
608 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */
609 if (real_freq_mhz != freq_mhz) {
610 // no suitable divider
611 return false;
612 }
613
614 source_freq_mhz = xtal_freq;
615 source = RTC_CPU_FREQ_SRC_XTAL;
616 } else if (freq_mhz == 80) {
617 real_freq_mhz = freq_mhz;
618 source = RTC_CPU_FREQ_SRC_PLL;
619 source_freq_mhz = RTC_PLL_FREQ_320M;
620 divider = 4;
621 } else if (freq_mhz == 160) {
622 real_freq_mhz = freq_mhz;
623 source = RTC_CPU_FREQ_SRC_PLL;
624 source_freq_mhz = RTC_PLL_FREQ_320M;
625 divider = 2;
626 } else if (freq_mhz == 240) {
627 real_freq_mhz = freq_mhz;
628 source = RTC_CPU_FREQ_SRC_PLL;
629 source_freq_mhz = RTC_PLL_FREQ_480M;
630 divider = 2;
631 } else {
632 // unsupported frequency
633 return false;
634 }
635 *out_config = (rtc_cpu_freq_config_t) {
636 .source = source,
637 .div = divider,
638 .source_freq_mhz = source_freq_mhz,
639 .freq_mhz = real_freq_mhz
640 };
641 return true;
642 }
643
rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t * config)644 void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t* config)
645 {
646 rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
647 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
648 if (soc_clk_sel != RTC_CNTL_SOC_CLK_SEL_XTL) {
649 rtc_clk_cpu_freq_to_xtal(xtal_freq, 1);
650 rtc_clk_wait_for_slow_cycle();
651 }
652 if (soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_PLL) {
653 rtc_clk_bbpll_disable();
654 }
655 if (config->source == RTC_CPU_FREQ_SRC_XTAL) {
656 if (config->div > 1) {
657 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
658 }
659 } else if (config->source == RTC_CPU_FREQ_SRC_PLL) {
660 rtc_clk_bbpll_enable();
661 rtc_clk_wait_for_slow_cycle();
662 rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
663 rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
664 } else if (config->source == RTC_CPU_FREQ_SRC_8M) {
665 rtc_clk_cpu_freq_to_8m();
666 }
667 }
668
rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t * out_config)669 void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config)
670 {
671 rtc_cpu_freq_src_t source;
672 uint32_t source_freq_mhz;
673 uint32_t div;
674 uint32_t freq_mhz;
675 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
676 switch (soc_clk_sel) {
677 case RTC_CNTL_SOC_CLK_SEL_XTL: {
678 source = RTC_CPU_FREQ_SRC_XTAL;
679 div = REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT) + 1;
680 source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get();
681 freq_mhz = source_freq_mhz / div;
682 }
683 break;
684 case RTC_CNTL_SOC_CLK_SEL_PLL: {
685 source = RTC_CPU_FREQ_SRC_PLL;
686 uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
687 if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
688 source_freq_mhz = RTC_PLL_FREQ_320M;
689 div = 4;
690 freq_mhz = 80;
691 } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
692 source_freq_mhz = RTC_PLL_FREQ_320M;
693 div = 2;
694 freq_mhz = 160;
695 } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) {
696 source_freq_mhz = RTC_PLL_FREQ_480M;
697 div = 2;
698 freq_mhz = 240;
699 } else {
700 SOC_LOGE(TAG, "unsupported frequency configuration");
701 abort();
702 }
703 break;
704 }
705 case RTC_CNTL_SOC_CLK_SEL_8M:
706 source = RTC_CPU_FREQ_SRC_8M;
707 source_freq_mhz = 8;
708 div = 1;
709 freq_mhz = source_freq_mhz;
710 break;
711 case RTC_CNTL_SOC_CLK_SEL_APLL:
712 default:
713 SOC_LOGE(TAG, "unsupported frequency configuration");
714 abort();
715 }
716 *out_config = (rtc_cpu_freq_config_t) {
717 .source = source,
718 .source_freq_mhz = source_freq_mhz,
719 .div = div,
720 .freq_mhz = freq_mhz
721 };
722 }
723
rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t * config)724 void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t* config)
725 {
726 if (config->source == RTC_CPU_FREQ_SRC_XTAL) {
727 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
728 } else if (config->source == RTC_CPU_FREQ_SRC_PLL &&
729 s_cur_pll_freq == config->source_freq_mhz) {
730 rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
731 } else {
732 /* fallback */
733 rtc_clk_cpu_freq_set_config(config);
734 }
735 }
736
rtc_clk_xtal_freq_get(void)737 rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
738 {
739 /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */
740 uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
741 if (!clk_val_is_valid(xtal_freq_reg)) {
742 return RTC_XTAL_FREQ_AUTO;
743 }
744 return reg_val_to_clk_val(xtal_freq_reg & ~RTC_DISABLE_ROM_LOG);
745 }
746
rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)747 void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
748 {
749 uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
750 if (reg == RTC_DISABLE_ROM_LOG) {
751 xtal_freq |= 1;
752 }
753 WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
754 }
755
rtc_clk_apb_freq_update(uint32_t apb_freq)756 void rtc_clk_apb_freq_update(uint32_t apb_freq)
757 {
758 WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
759 }
760
rtc_clk_apb_freq_get(void)761 uint32_t rtc_clk_apb_freq_get(void)
762 {
763 #if CONFIG_IDF_ENV_FPGA
764 return CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * MHZ;
765 #endif // CONFIG_IDF_ENV_FPGA
766 uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
767 // round to the nearest MHz
768 freq_hz += MHZ / 2;
769 uint32_t remainder = freq_hz % MHZ;
770 return freq_hz - remainder;
771 }
772
rtc_dig_clk8m_enable(void)773 void rtc_dig_clk8m_enable(void)
774 {
775 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
776 esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
777 }
778
rtc_dig_clk8m_disable(void)779 void rtc_dig_clk8m_disable(void)
780 {
781 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
782 esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
783 }
784
785 /* Name used in libphy.a:phy_chip_v7.o
786 * TODO: update the library to use rtc_clk_xtal_freq_get
787 */
788 rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get")));
789
