1 /*
2  * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 /*
7  Tests for the spi sio mode
8 */
9 
10 #include <esp_types.h>
11 #include <stdio.h>
12 #include <stdlib.h>
13 #include <malloc.h>
14 #include <string.h>
15 #include "sdkconfig.h"
16 #include "freertos/FreeRTOS.h"
17 #include "freertos/task.h"
18 #include "freertos/semphr.h"
19 #include "freertos/queue.h"
20 #include "unity.h"
21 #include "driver/spi_master.h"
22 #include "driver/spi_slave.h"
23 #include "esp_heap_caps.h"
24 #include "esp_log.h"
25 #include "soc/spi_periph.h"
26 #include "test_utils.h"
27 #include "test/test_common_spi.h"
28 #include "soc/gpio_periph.h"
29 
30 #include "hal/spi_ll.h"
31 
32 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
33 #if !DISABLED_FOR_TARGETS(ESP32C3)  //There is only one GPSPI controller, so single-board test is disabled.
34 
35 /********************************************************************************
36  *      Test SIO
37  ********************************************************************************/
38 TEST_CASE("local test sio", "[spi]")
39 {
40     spi_device_handle_t spi;
41     WORD_ALIGNED_ATTR uint8_t master_rx_buffer[320];
42     WORD_ALIGNED_ATTR uint8_t slave_rx_buffer[320];
43 
44     uint32_t pre_set[16] = {[0 ... 15] = 0xcccccccc,};
45     spi_ll_write_buffer(SPI_LL_GET_HW(TEST_SPI_HOST),   (uint8_t*)pre_set, 16*32);
46     spi_ll_write_buffer(SPI_LL_GET_HW(TEST_SLAVE_HOST), (uint8_t*)pre_set, 16*32);
47 
48     /* This test use a strange connection to test the SIO mode:
49      * master spid -> slave spid
50      * slave spiq -> master spid
51      */
52     spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
53     spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
54     spi_slave_interface_config_t slv_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
55     slv_cfg.spics_io_num = dev_cfg.spics_io_num;
56     TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, 0));
57 
58     int miso_io_num = bus_cfg.miso_io_num;
59     int mosi_io_num = bus_cfg.mosi_io_num;
60     bus_cfg.mosi_io_num = miso_io_num;
61     bus_cfg.miso_io_num = -1;
62     TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, 0));
63 
64     dev_cfg.flags = SPI_DEVICE_HALFDUPLEX | SPI_DEVICE_3WIRE;
65     TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi));
66 
67     spitest_gpio_output_sel(mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out);
68     spitest_gpio_output_sel(miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out);
69     spitest_gpio_output_sel(dev_cfg.spics_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spics_out[0]);
70     spitest_gpio_output_sel(bus_cfg.sclk_io_num, FUNC_GPIO,  spi_periph_signal[TEST_SPI_HOST].spiclk_out);
71 
72     for (int i = 0; i < 8; i ++) {
73         int tlen = i*2+1;
74         int rlen = 9-i;
75 
76         ESP_LOGI(MASTER_TAG, "=========== TEST%d ==========", i);
77 
78         spi_transaction_t master_t = {
79             .length = tlen*8,
80             .tx_buffer = spitest_master_send+i,
81             .rxlength = rlen*8,
82             .rx_buffer = master_rx_buffer+i,
83         };
84         spi_slave_transaction_t slave_t = {
85             .length = (tlen+rlen)*8,
86             .tx_buffer = spitest_slave_send+i,
87             .rx_buffer = slave_rx_buffer,
88         };
89         memset(master_rx_buffer, 0x66, sizeof(master_rx_buffer));
90         memset(slave_rx_buffer, 0x66, sizeof(slave_rx_buffer));
91         TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_t, portMAX_DELAY));
92 
93         TEST_ESP_OK(spi_device_transmit(spi, &master_t));
94         spi_slave_transaction_t* ret_t;
95         TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &ret_t, portMAX_DELAY));
96         TEST_ASSERT(ret_t == &slave_t);
97 
98         ESP_LOG_BUFFER_HEXDUMP("master tx", master_t.tx_buffer, tlen, ESP_LOG_INFO);
99         ESP_LOG_BUFFER_HEXDUMP("slave rx", slave_t.rx_buffer, tlen+rlen, ESP_LOG_INFO);
100         ESP_LOG_BUFFER_HEXDUMP("slave tx", slave_t.tx_buffer, tlen+rlen, ESP_LOG_INFO);
101         ESP_LOG_BUFFER_HEXDUMP("master rx", master_t.rx_buffer, rlen, ESP_LOG_INFO);
102 
103         TEST_ASSERT_EQUAL_HEX8_ARRAY(master_t.tx_buffer, slave_t.rx_buffer, tlen);
104         TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_t.tx_buffer + tlen, master_t.rx_buffer, rlen);
105     }
106 
107     spi_slave_free(TEST_SLAVE_HOST);
108     master_free_device_bus(spi);
109 }
110 #endif //!DISABLED_FOR_TARGETS(ESP32C3)  //There is only one GPSPI controller, so single-board test is disabled.
111 
112 
113 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3)
114 //These tests are ESP32 only due to lack of runners
115 /********************************************************************************
116  *      Test SIO Master & Slave
117  ********************************************************************************/
118 //if test_mosi is false, test on miso of slave, otherwise test on mosi of slave
test_sio_master_round(bool test_mosi)119 void test_sio_master_round(bool test_mosi)
120 {
121     spi_device_handle_t spi;
122     WORD_ALIGNED_ATTR uint8_t rx_buffer[320];
123 
124     if (test_mosi) {
125         ESP_LOGI(MASTER_TAG, "======== TEST MOSI ===========");
126     } else {
127         ESP_LOGI(MASTER_TAG, "======== TEST MISO ===========");
128     }
129 
130     spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
131     if (!test_mosi) bus_cfg.mosi_io_num = bus_cfg.miso_io_num;
132     bus_cfg.miso_io_num = -1;
133     TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, 0));
134 
135     spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
136     dev_cfg.flags = SPI_DEVICE_HALFDUPLEX | SPI_DEVICE_3WIRE;
137     dev_cfg.clock_speed_hz = 1*1000*1000;
138     TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi));
139 
140     for (int i = 0; i < 8; i ++) {
141         int tlen = i*2+1;
142         int rlen = 9-i;
143         spi_transaction_t t = {
144             .length = tlen*8,
145             .tx_buffer = spitest_master_send+i,
146             .rxlength = rlen*8,
147             .rx_buffer = rx_buffer+i,
148         };
149         memset(rx_buffer, 0x66, sizeof(rx_buffer));
150 
151         //get signal
152         unity_wait_for_signal("slave ready");
153 
154         TEST_ESP_OK(spi_device_transmit(spi, &t));
155         uint8_t* exp_ptr = spitest_slave_send+i;
156         ESP_LOG_BUFFER_HEXDUMP("master tx", t.tx_buffer, tlen, ESP_LOG_INFO);
157         ESP_LOG_BUFFER_HEXDUMP("exp tx", exp_ptr, rlen, ESP_LOG_INFO);
158         ESP_LOG_BUFFER_HEXDUMP("master rx", t.rx_buffer, rlen, ESP_LOG_INFO);
159         if (!test_mosi) {
160             TEST_ASSERT_EQUAL_HEX8_ARRAY(exp_ptr+tlen, t.rx_buffer, rlen);
161         }
162     }
163 
164     master_free_device_bus(spi);
165 }
166 
test_sio_master(void)167 void test_sio_master(void)
168 {
169     test_sio_master_round(true);
170     unity_send_signal("master ready");
171     test_sio_master_round(false);
172 }
173 
test_sio_slave_round(bool test_mosi)174 void test_sio_slave_round(bool test_mosi)
175 {
176     WORD_ALIGNED_ATTR uint8_t rx_buffer[320];
177 
178     if (test_mosi) {
179         ESP_LOGI(SLAVE_TAG, "======== TEST MOSI ===========");
180     } else {
181         ESP_LOGI(SLAVE_TAG, "======== TEST MISO ===========");
182     }
183 
184     spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
185     bus_cfg.mosi_io_num = spi_periph_signal[TEST_SLAVE_HOST].spid_iomux_pin;
186     bus_cfg.miso_io_num = spi_periph_signal[TEST_SLAVE_HOST].spiq_iomux_pin;
187     bus_cfg.sclk_io_num = spi_periph_signal[TEST_SLAVE_HOST].spiclk_iomux_pin;
188 
189     spi_slave_interface_config_t slv_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
190     slv_cfg.spics_io_num = spi_periph_signal[TEST_SLAVE_HOST].spics0_iomux_pin;
191     TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, 0));
192 
193     for (int i = 0; i < 8; i++) {
194         int tlen = 9-i;
195         int rlen = i*2+1;
196         spi_slave_transaction_t t = {
197             .length = (tlen+rlen)*8,
198             .tx_buffer = spitest_slave_send+i,
199             .rx_buffer = rx_buffer,
200         };
201 
202         TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &t, portMAX_DELAY));
203 
204         ESP_LOG_BUFFER_HEXDUMP("slave tx", t.tx_buffer, tlen+rlen, ESP_LOG_INFO);
205 
206         //send signal_idx
207         unity_send_signal("slave ready");
208 
209         uint8_t *exp_ptr = spitest_master_send+i;
210         spi_slave_transaction_t* ret_t;
211         TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &ret_t, portMAX_DELAY));
212 
213         ESP_LOG_BUFFER_HEXDUMP("exp tx", exp_ptr, tlen+rlen, ESP_LOG_INFO);
214         ESP_LOG_BUFFER_HEXDUMP("slave rx", t.rx_buffer, tlen+rlen, ESP_LOG_INFO);
215         if (test_mosi) {
216             TEST_ASSERT_EQUAL_HEX8_ARRAY(exp_ptr, t.rx_buffer, rlen);
217         }
218     }
219 
220     spi_slave_free(TEST_SLAVE_HOST);
221 }
222 
test_sio_slave(void)223 void test_sio_slave(void)
224 {
225     test_sio_slave_round(true);
226     unity_wait_for_signal("master ready");
227     test_sio_slave_round(false);
228 }
229 
230 TEST_CASE_MULTIPLE_DEVICES("sio mode", "[spi][test_env=Example_SPI_Multi_device]", test_sio_master, test_sio_slave);
231 #endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3)
232 
233 #endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3)
234