1 /*
2 * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <stdbool.h>
7 #include <assert.h>
8 #include "string.h"
9 #include "sdkconfig.h"
10 #include "esp_err.h"
11 #include "esp_log.h"
12 #include "esp32c3/rom/gpio.h"
13 #include "esp32c3/rom/spi_flash.h"
14 #include "esp32c3/rom/efuse.h"
15 #include "soc/gpio_periph.h"
16 #include "soc/efuse_reg.h"
17 #include "soc/spi_reg.h"
18 #include "soc/spi_mem_reg.h"
19 #include "soc/soc_caps.h"
20 #include "flash_qio_mode.h"
21 #include "bootloader_flash_config.h"
22 #include "bootloader_common.h"
23
24 #define FLASH_IO_MATRIX_DUMMY_40M 0
25 #define FLASH_IO_MATRIX_DUMMY_80M 0
26
bootloader_flash_update_id()27 void bootloader_flash_update_id()
28 {
29 esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
30 chip->device_id = bootloader_read_flash_id();
31 }
32
bootloader_flash_cs_timing_config()33 void IRAM_ATTR bootloader_flash_cs_timing_config()
34 {
35 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
36 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
37 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
38 SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
39 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S);
40 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
41 }
42
bootloader_flash_clock_config(const esp_image_header_t * pfhdr)43 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
44 {
45 uint32_t spi_clk_div = 0;
46 switch (pfhdr->spi_speed) {
47 case ESP_IMAGE_SPI_SPEED_80M:
48 spi_clk_div = 1;
49 break;
50 case ESP_IMAGE_SPI_SPEED_40M:
51 spi_clk_div = 2;
52 break;
53 case ESP_IMAGE_SPI_SPEED_26M:
54 spi_clk_div = 3;
55 break;
56 case ESP_IMAGE_SPI_SPEED_20M:
57 spi_clk_div = 4;
58 break;
59 default:
60 break;
61 }
62 esp_rom_spiflash_config_clk(spi_clk_div, 0);
63 }
64
bootloader_flash_set_dummy_out(void)65 void IRAM_ATTR bootloader_flash_set_dummy_out(void)
66 {
67 REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
68 REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
69 }
70
bootloader_flash_dummy_config(const esp_image_header_t * pfhdr)71 void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr)
72 {
73 bootloader_configure_spi_pins(1);
74 bootloader_flash_set_dummy_out();
75 }
76
