1 // Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 // Test for spi_flash_{read,write}.
16
17 #include <assert.h>
18 #include <stdint.h>
19 #include <stdio.h>
20 #include <string.h>
21 #include <sys/param.h>
22
23 #include <unity.h>
24 #include <test_utils.h>
25 #include <esp_spi_flash.h>
26 #include <esp32/rom/spi_flash.h>
27 #include "../cache_utils.h"
28 #include "soc/timer_periph.h"
29 #include "esp_heap_caps.h"
30
31 #define MIN_BLOCK_SIZE 12
32 /* Base offset in flash for tests. */
33
34 static size_t start;
35
setup_tests(void)36 static void setup_tests(void)
37 {
38 if (start == 0) {
39 const esp_partition_t *part = get_test_data_partition();
40 start = part->address;
41 printf("Test data partition @ 0x%x\n", start);
42 }
43 }
44
45 #ifndef CONFIG_SPI_FLASH_MINIMAL_TEST
46 #define CONFIG_SPI_FLASH_MINIMAL_TEST 1
47 #endif
48
fill(char * dest,int32_t start,int32_t len)49 static void fill(char *dest, int32_t start, int32_t len)
50 {
51 for (int32_t i = 0; i < len; i++) {
52 *(dest + i) = (char) (start + i);
53 }
54 }
55
cmp_or_dump(const void * a,const void * b,size_t len)56 static int cmp_or_dump(const void *a, const void *b, size_t len)
57 {
58 int r = memcmp(a, b, len);
59 if (r != 0) {
60 for (int i = 0; i < len; i++) {
61 fprintf(stderr, "%02x", ((unsigned char *) a)[i]);
62 }
63 fprintf(stderr, "\n");
64 for (int i = 0; i < len; i++) {
65 fprintf(stderr, "%02x", ((unsigned char *) b)[i]);
66 }
67 fprintf(stderr, "\n");
68 }
69 return r;
70 }
71
72
test_read(int src_off,int dst_off,int len)73 static void IRAM_ATTR test_read(int src_off, int dst_off, int len)
74 {
75 uint32_t src_buf[16];
76 char dst_buf[64], dst_gold[64];
77
78 fprintf(stderr, "src=%d dst=%d len=%d\n", src_off, dst_off, len);
79 memset(src_buf, 0xAA, sizeof(src_buf));
80 fill(((char *) src_buf) + src_off, src_off, len);
81 ESP_ERROR_CHECK(spi_flash_erase_sector((start + src_off) / SPI_FLASH_SEC_SIZE));
82 spi_flash_disable_interrupts_caches_and_other_cpu();
83 esp_rom_spiflash_result_t rc = esp_rom_spiflash_write(start, src_buf, sizeof(src_buf));
84 spi_flash_enable_interrupts_caches_and_other_cpu();
85 TEST_ASSERT_EQUAL_HEX(rc, ESP_ROM_SPIFLASH_RESULT_OK);
86 memset(dst_buf, 0x55, sizeof(dst_buf));
87 memset(dst_gold, 0x55, sizeof(dst_gold));
88 fill(dst_gold + dst_off, src_off, len);
89 ESP_ERROR_CHECK(spi_flash_read(start + src_off, dst_buf + dst_off, len));
90 TEST_ASSERT_EQUAL_INT(cmp_or_dump(dst_buf, dst_gold, sizeof(dst_buf)), 0);
91 }
92
93 TEST_CASE("Test spi_flash_read", "[spi_flash][esp_flash]")
94 {
95 setup_tests();
96 #if CONFIG_SPI_FLASH_MINIMAL_TEST
97 test_read(0, 0, 0);
98 test_read(0, 0, 4);
99 test_read(0, 0, 16);
100 test_read(0, 0, 64);
101 test_read(0, 0, 1);
102 test_read(0, 1, 1);
103 test_read(1, 0, 1);
104 test_read(1, 1, 1);
105 test_read(1, 1, 2);
106 test_read(1, 1, 3);
107 test_read(1, 1, 4);
108 test_read(1, 1, 5);
109 test_read(3, 2, 5);
110 test_read(0, 0, 17);
111 test_read(0, 1, 17);
112 test_read(1, 0, 17);
113 test_read(1, 1, 17);
114 test_read(1, 1, 18);
115 test_read(1, 1, 19);
116 test_read(1, 1, 20);
117 test_read(1, 1, 21);
118 test_read(3, 2, 21);
119 test_read(4, 4, 60);
120 test_read(59, 0, 5);
121 test_read(60, 0, 4);
122 test_read(60, 0, 3);
123 test_read(60, 0, 2);
124 test_read(63, 0, 1);
125 test_read(64, 0, 0);
126 test_read(59, 59, 5);
127 test_read(60, 60, 4);
128 test_read(60, 60, 3);
129 test_read(60, 60, 2);
130 test_read(63, 63, 1);
131 test_read(64, 64, 0);
132 #else
133 /* This will run a more thorough test but will slam flash pretty hard. */
134 for (int src_off = 1; src_off < 16; src_off++) {
135 for (int dst_off = 0; dst_off < 16; dst_off++) {
136 for (int len = 0; len < 32; len++) {
137 test_read(dst_off, src_off, len);
138 }
139 }
140 }
141 #endif
142 }
143
144 #if CONFIG_IDF_TARGET_ESP32
fix_rom_func(void)145 static void IRAM_ATTR fix_rom_func(void)
146 {
147 return; // ESP32 ROM has no compatible issue for now
148 }
149 # else
150 extern void spi_common_set_dummy_output(esp_rom_spiflash_read_mode_t mode);
151 extern void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
fix_rom_func(void)152 static void IRAM_ATTR fix_rom_func(void)
153 {
154 esp_rom_spiflash_read_mode_t read_mode;
155 uint8_t freqdiv;
156 #if defined CONFIG_ESPTOOLPY_FLASHMODE_QIO
157 read_mode = ESP_ROM_SPIFLASH_QIO_MODE;
158 #elif defined CONFIG_ESPTOOLPY_FLASHMODE_QOUT
159 read_mode = ESP_ROM_SPIFLASH_QOUT_MODE;
160 #elif defined CONFIG_ESPTOOLPY_FLASHMODE_DIO
161 read_mode = ESP_ROM_SPIFLASH_DIO_MODE;
162 #elif defined CONFIG_ESPTOOLPY_FLASHMODE_DOUT
163 read_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
164 #endif
165
166 # if defined CONFIG_ESPTOOLPY_FLASHFREQ_80M
167 freqdiv = 1;
168 # elif defined CONFIG_ESPTOOLPY_FLASHFREQ_40M
169 freqdiv = 2;
170 # elif defined CONFIG_ESPTOOLPY_FLASHFREQ_26M
171 freqdiv = 3;
172 # elif defined CONFIG_ESPTOOLPY_FLASHFREQ_20M
173 freqdiv = 4;
174 #endif
175
176 spi_flash_disable_interrupts_caches_and_other_cpu();
177 esp_rom_spiflash_config_clk(freqdiv, 1);
178 spi_dummy_len_fix(1, freqdiv);
179 esp_rom_spiflash_config_readmode(read_mode);
180 #if !CONFIG_IDF_TARGET_ESP32S2
181 spi_common_set_dummy_output(read_mode);
182 #endif //!CONFIG_IDF_TARGET_ESP32S2
183 spi_flash_enable_interrupts_caches_and_other_cpu();
184 }
185 #endif
186
test_write(int dst_off,int src_off,int len)187 static void IRAM_ATTR test_write(int dst_off, int src_off, int len)
188 {
189 char src_buf[64], dst_gold[64];
190 uint32_t dst_buf[16];
191 fprintf(stderr, "dst=%d src=%d len=%d\n", dst_off, src_off, len);
192 memset(src_buf, 0x55, sizeof(src_buf));
193 fill(src_buf + src_off, src_off, len);
194 // Fills with 0xff
195 ESP_ERROR_CHECK(spi_flash_erase_sector((start + dst_off) / SPI_FLASH_SEC_SIZE));
196 memset(dst_gold, 0xff, sizeof(dst_gold));
197 if (len > 0) {
198 int pad_left_off = (dst_off & ~3U);
199 memset(dst_gold + pad_left_off, 0xff, 4);
200 if (dst_off + len > pad_left_off + 4 && (dst_off + len) % 4 != 0) {
201 int pad_right_off = ((dst_off + len) & ~3U);
202 memset(dst_gold + pad_right_off, 0xff, 4);
203 }
204 fill(dst_gold + dst_off, src_off, len);
205 }
206 ESP_ERROR_CHECK(spi_flash_write(start + dst_off, src_buf + src_off, len));
207
208 fix_rom_func();
209
210 spi_flash_disable_interrupts_caches_and_other_cpu();
211 esp_rom_spiflash_result_t rc = esp_rom_spiflash_read(start, dst_buf, sizeof(dst_buf));
212 spi_flash_enable_interrupts_caches_and_other_cpu();
213 TEST_ASSERT_EQUAL_HEX(rc, ESP_ROM_SPIFLASH_RESULT_OK);
214
215 TEST_ASSERT_EQUAL_INT(cmp_or_dump(dst_buf, dst_gold, sizeof(dst_buf)), 0);
216 }
217
218 TEST_CASE("Test spi_flash_write", "[spi_flash][esp_flash]")
219 {
220 setup_tests();
221 #if CONFIG_SPI_FLASH_MINIMAL_TEST
222 test_write(0, 0, 0);
223 test_write(0, 0, 4);
224 test_write(0, 0, 16);
225 test_write(0, 0, 64);
226 test_write(0, 0, 1);
227 test_write(0, 1, 1);
228 test_write(1, 0, 1);
229 test_write(1, 1, 1);
230 test_write(1, 1, 2);
231 test_write(1, 1, 3);
232 test_write(1, 1, 4);
233 test_write(1, 1, 5);
234 test_write(3, 2, 5);
235 test_write(4, 4, 60);
236 test_write(59, 0, 5);
237 test_write(60, 0, 4);
238 test_write(60, 0, 3);
239 test_write(60, 0, 2);
240 test_write(63, 0, 1);
241 test_write(64, 0, 0);
242 test_write(59, 59, 5);
243 test_write(60, 60, 4);
244 test_write(60, 60, 3);
245 test_write(60, 60, 2);
246 test_write(63, 63, 1);
247 test_write(64, 64, 0);
248 #else
249 /* This will run a more thorough test but will slam flash pretty hard. */
250 for (int dst_off = 1; dst_off < 16; dst_off++) {
251 for (int src_off = 0; src_off < 16; src_off++) {
252 for (int len = 0; len < 16; len++) {
253 test_write(dst_off, src_off, len);
254 }
255 }
256 }
257 #endif
258 /*
259 * Test writing from ROM, IRAM and caches. We don't know what exactly will be
260 * written, we're testing that there's no crash here.
261 *
262 * NB: At the moment these only support aligned addresses, because memcpy
263 * is not aware of the 32-but load requirements for these regions.
264 */
265 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
266 #define TEST_SOC_IROM_ADDR (SOC_IROM_LOW)
267 #define TEST_SOC_CACHE_RAM_BANK0_ADDR (SOC_IRAM_LOW)
268 #define TEST_SOC_CACHE_RAM_BANK1_ADDR (SOC_IRAM_LOW + 0x2000)
269 #define TEST_SOC_CACHE_RAM_BANK2_ADDR (SOC_IRAM_LOW + 0x4000)
270 #define TEST_SOC_CACHE_RAM_BANK3_ADDR (SOC_IRAM_LOW + 0x6000)
271 #define TEST_SOC_IRAM_ADDR (SOC_IRAM_LOW + 0x8000)
272 #define TEST_SOC_RTC_IRAM_ADDR (SOC_RTC_IRAM_LOW)
273 #define TEST_SOC_RTC_DRAM_ADDR (SOC_RTC_DRAM_LOW)
274 ESP_ERROR_CHECK(spi_flash_write(start, (char *) TEST_SOC_IROM_ADDR, 16));
275 ESP_ERROR_CHECK(spi_flash_write(start, (char *) TEST_SOC_IRAM_ADDR, 16));
276 ESP_ERROR_CHECK(spi_flash_write(start, (char *) TEST_SOC_CACHE_RAM_BANK0_ADDR, 16));
277 ESP_ERROR_CHECK(spi_flash_write(start, (char *) TEST_SOC_CACHE_RAM_BANK1_ADDR, 16));
278 ESP_ERROR_CHECK(spi_flash_write(start, (char *) TEST_SOC_CACHE_RAM_BANK2_ADDR, 16));
279 ESP_ERROR_CHECK(spi_flash_write(start, (char *) TEST_SOC_CACHE_RAM_BANK3_ADDR, 16));
280 ESP_ERROR_CHECK(spi_flash_write(start, (char *) TEST_SOC_RTC_IRAM_ADDR, 16));
281 ESP_ERROR_CHECK(spi_flash_write(start, (char *) TEST_SOC_RTC_DRAM_ADDR, 16));
282 #else
283 ESP_ERROR_CHECK(spi_flash_write(start, (char *) 0x40000000, 16));
284 ESP_ERROR_CHECK(spi_flash_write(start, (char *) 0x40070000, 16));
285 ESP_ERROR_CHECK(spi_flash_write(start, (char *) 0x40078000, 16));
286 ESP_ERROR_CHECK(spi_flash_write(start, (char *) 0x40080000, 16));
287 #endif
288 }
289
290 #ifdef CONFIG_SPIRAM
291
292 TEST_CASE("spi_flash_read can read into buffer in external RAM", "[spi_flash]")
293 {
294 uint8_t* buf_ext = (uint8_t*) heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
295 TEST_ASSERT_NOT_NULL(buf_ext);
296
297 uint8_t* buf_int = (uint8_t*) heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
298 TEST_ASSERT_NOT_NULL(buf_int);
299
300 TEST_ESP_OK(spi_flash_read(0x1000, buf_int, SPI_FLASH_SEC_SIZE));
301 TEST_ESP_OK(spi_flash_read(0x1000, buf_ext, SPI_FLASH_SEC_SIZE));
302
303 TEST_ASSERT_EQUAL(0, memcmp(buf_ext, buf_int, SPI_FLASH_SEC_SIZE));
304 free(buf_ext);
305 free(buf_int);
306 }
307
308 TEST_CASE("spi_flash_write can write from external RAM buffer", "[spi_flash]")
309 {
310 uint32_t* buf_ext = (uint32_t*) heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
311 TEST_ASSERT_NOT_NULL(buf_ext);
312
313 srand(0);
314 for (size_t i = 0; i < SPI_FLASH_SEC_SIZE / sizeof(uint32_t); i++)
315 {
316 uint32_t val = rand();
317 buf_ext[i] = val;
318 }
319
320 uint8_t* buf_int = (uint8_t*) heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
321 TEST_ASSERT_NOT_NULL(buf_int);
322
323 /* Write to flash from buf_ext */
324 const esp_partition_t *part = get_test_data_partition();
325 TEST_ESP_OK(spi_flash_erase_range(part->address, SPI_FLASH_SEC_SIZE));
326 TEST_ESP_OK(spi_flash_write(part->address, buf_ext, SPI_FLASH_SEC_SIZE));
327
328 /* Read back to buf_int and compare */
329 TEST_ESP_OK(spi_flash_read(part->address, buf_int, SPI_FLASH_SEC_SIZE));
330 TEST_ASSERT_EQUAL(0, memcmp(buf_ext, buf_int, SPI_FLASH_SEC_SIZE));
331
332 free(buf_ext);
333 free(buf_int);
334 }
335
336 TEST_CASE("spi_flash_read less than 16 bytes into buffer in external RAM", "[spi_flash]")
337 {
338 uint8_t *buf_ext_8 = (uint8_t *) heap_caps_malloc(MIN_BLOCK_SIZE, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
339 TEST_ASSERT_NOT_NULL(buf_ext_8);
340
341 uint8_t *buf_int_8 = (uint8_t *) heap_caps_malloc(MIN_BLOCK_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
342 TEST_ASSERT_NOT_NULL(buf_int_8);
343
344 uint8_t data_8[MIN_BLOCK_SIZE];
345 for (int i = 0; i < MIN_BLOCK_SIZE; i++) {
346 data_8[i] = i;
347 }
348
349 const esp_partition_t *part = get_test_data_partition();
350 TEST_ESP_OK(spi_flash_erase_range(part->address, SPI_FLASH_SEC_SIZE));
351 TEST_ESP_OK(spi_flash_write(part->address, data_8, MIN_BLOCK_SIZE));
352 TEST_ESP_OK(spi_flash_read(part->address, buf_ext_8, MIN_BLOCK_SIZE));
353 TEST_ESP_OK(spi_flash_read(part->address, buf_int_8, MIN_BLOCK_SIZE));
354
355 TEST_ASSERT_EQUAL(0, memcmp(buf_ext_8, data_8, MIN_BLOCK_SIZE));
356 TEST_ASSERT_EQUAL(0, memcmp(buf_int_8, data_8, MIN_BLOCK_SIZE));
357
358 if (buf_ext_8) {
359 free(buf_ext_8);
360 buf_ext_8 = NULL;
361 }
362 if (buf_int_8) {
363 free(buf_int_8);
364 buf_int_8 = NULL;
365 }
366 }
367
368 #endif // CONFIG_SPIRAM
369
