1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef ESP_SPI_FLASH_CACHE_UTILS_H 16 #define ESP_SPI_FLASH_CACHE_UTILS_H 17 18 #include "sdkconfig.h" 19 #include <stdbool.h> 20 21 /** 22 * This header file contains declarations of cache manipulation functions 23 * used both in flash_ops.c and flash_mmap.c. 24 * 25 * These functions are considered internal and are not designed to be called from applications. 26 */ 27 28 // Init mutex protecting access to spi_flash_* APIs 29 void spi_flash_init_lock(void); 30 31 // Take mutex protecting access to spi_flash_* APIs 32 void spi_flash_op_lock(void); 33 34 // Release said mutex 35 void spi_flash_op_unlock(void); 36 37 // Suspend the scheduler on both CPUs, disable cache. 38 // Contrary to its name this doesn't do anything with interrupts, yet. 39 // Interrupt disabling capability will be added once we implement 40 // interrupt allocation API. 41 void spi_flash_disable_interrupts_caches_and_other_cpu(void); 42 43 // Enable cache, enable interrupts (to be added in future), resume scheduler 44 void spi_flash_enable_interrupts_caches_and_other_cpu(void); 45 46 // Disables non-IRAM interrupt handlers on current CPU and caches on both CPUs. 47 // This function is implied to be called when other CPU is not running or running code from IRAM. 48 void spi_flash_disable_interrupts_caches_and_other_cpu_no_os(void); 49 50 // Enable cache, enable interrupts on current CPU. 51 // This function is implied to be called when other CPU is not running or running code from IRAM. 52 void spi_flash_enable_interrupts_caches_no_os(void); 53 54 // Mark the pages containing a flash region as having been 55 // erased or written to. This means the flash cache needs 56 // to be evicted before these pages can be flash_mmap()ed again, 57 // as they may contain stale data 58 // 59 // Only call this while holding spi_flash_op_lock() 60 // Returns true if cache was flushed, false otherwise 61 bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length); 62 63 //config cache mode 64 #if !CONFIG_IDF_TARGET_ESP32 65 //config instrcutin cache size and cache block size by menuconfig 66 void esp_config_instruction_cache_mode(void); 67 //config data cache size and cache block size by menuconfig 68 void esp_config_data_cache_mode(void); 69 //enable cache wrap mode for instruction cache and data cache 70 esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable); 71 #endif 72 73 74 #endif //ESP_SPI_FLASH_CACHE_UTILS_H 75
