1 // Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef BOOTLOADER_BUILD 15 16 #include <stdint.h> 17 #include <stdlib.h> 18 #include "sdkconfig.h" 19 #include "esp_attr.h" 20 #include "soc/soc.h" 21 #include "soc/soc_memory_layout.h" 22 #include "esp_heap_caps.h" 23 24 /** 25 * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC. 26 * Each type of memory map consists of one or more regions in the address space. 27 * Each type contains an array of prioritized capabilities. 28 * Types with later entries are only taken if earlier ones can't fulfill the memory request. 29 * 30 * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory. 31 * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM. 32 * - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM. 33 * - Most other malloc caps only fit in one region anyway. 34 * 35 */ 36 const soc_memory_type_desc_t soc_memory_types[] = { 37 // Type 0: DRAM 38 { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, 39 // Type 1: DRAM used for startup stacks 40 { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, true}, 41 // Type 2: DRAM which has an alias on the I-port 42 { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, 43 // Type 3: IRAM 44 { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, 45 // Type 4: SPI SRAM data 46 { "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}, false, false}, 47 }; 48 49 const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); 50 51 /** 52 * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type. 53 * 54 * @note Because of requirements in the coalescing code which merges adjacent regions, 55 * this list should always be sorted from low to high by start address. 56 * 57 */ 58 const soc_memory_region_t soc_memory_regions[] = { 59 #ifdef CONFIG_SPIRAM 60 { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 4, 0}, //SPI SRAM, if available 61 #endif 62 #if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB 63 { 0x40374000, 0x4000, 3, 0}, //Level 1, IRAM 64 #endif 65 { 0x3FC88000, 0x8000, 2, 0x40378000}, //Level 2, IDRAM, can be used as trace memroy 66 { 0x3FC90000, 0x10000, 2, 0x40380000}, //Level 3, IDRAM, can be used as trace memroy 67 { 0x3FCA0000, 0x10000, 2, 0x40390000}, //Level 4, IDRAM, can be used as trace memroy 68 { 0x3FCB0000, 0x10000, 2, 0x403A0000}, //Level 5, IDRAM, can be used as trace memroy 69 { 0x3FCC0000, 0x10000, 2, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy 70 { 0x3FCD0000, 0x10000, 2, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy 71 { 0x3FCE0000, 0x10000, 1, 0}, //Level 8, IDRAM, can be used as trace memroy, contains stacks used by startup flow, recycled by heap allocator in app_main task 72 #if CONFIG_ESP32S3_DATA_CACHE_32KB 73 { 0x3FCF0000, 0x8000, 0, 0}, //Level 9, DRAM 74 #endif 75 }; 76 77 const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); 78 79 extern int _dram0_rtos_reserved_start; // defined in esp32s3.rom.ld 80 extern int _data_start, _heap_start, _iram_start, _iram_end; // defined in esp32s3.project.ld.in 81 82 /** 83 * Reserved memory regions. 84 * These are removed from the soc_memory_regions array when heaps are created. 85 * 86 */ 87 //ROM data region 88 SOC_RESERVE_MEMORY_REGION((intptr_t)&_dram0_rtos_reserved_start, SOC_DIRAM_DRAM_HIGH, rom_data_region); 89 90 // Static data region. DRAM used by data+bss and possibly rodata 91 SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data); 92 93 // ESP32S3 has a big D/IRAM region, the part used by code is reserved 94 // The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address 95 #define I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) 96 #if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB 97 SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_start + 0x4000, iram_code_1); 98 SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start + 0x4000 - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code_2); 99 #else 100 SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code); 101 #endif 102 103 #ifdef CONFIG_SPIRAM 104 /* Reserve the whole possible SPIRAM region here, spiram.c will add some or all of this 105 * memory to heap depending on the actual SPIRAM chip size. */ 106 SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_data_region); 107 #endif 108 109 #if CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM > 0 110 SOC_RESERVE_MEMORY_REGION(0x3fffc000 - CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM, 0x3fffc000, trace_mem); 111 #endif 112 113 #endif // BOOTLOADER_BUILD 114
