1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #pragma once 15 16 #ifdef __cplusplus 17 extern "C" 18 { 19 #endif 20 21 #include <stdint.h> 22 23 typedef volatile struct { 24 union { 25 struct { 26 uint32_t in_rst : 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/ 27 uint32_t out_rst : 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/ 28 uint32_t in_loop_test : 1; /*reserved*/ 29 uint32_t out_loop_test : 1; /*reserved*/ 30 uint32_t out_auto_wrback : 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/ 31 uint32_t out_eof_mode : 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/ 32 uint32_t outdscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.*/ 33 uint32_t indscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.*/ 34 uint32_t out_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.*/ 35 uint32_t in_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.*/ 36 uint32_t mem_trans_en : 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/ 37 uint32_t reserved11 : 21; /*reserved*/ 38 }; 39 uint32_t val; 40 } conf0[5]; 41 union { 42 struct { 43 uint32_t infifo_full_thrs : 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/ 44 uint32_t check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ 45 uint32_t in_ext_mem_bk_size : 2; /*Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ 46 uint32_t out_ext_mem_bk_size : 2; /*Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ 47 uint32_t reserved17 : 15; /*reserved*/ 48 }; 49 uint32_t val; 50 } conf1[5]; 51 union { 52 struct { 53 uint32_t in_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/ 54 uint32_t in_suc_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/ 55 uint32_t in_err_eof : 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.*/ 56 uint32_t out_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/ 57 uint32_t out_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.*/ 58 uint32_t in_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 0.*/ 59 uint32_t out_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 0.*/ 60 uint32_t in_dscr_empty : 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.*/ 61 uint32_t out_total_eof : 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/ 62 uint32_t infifo_full_wm : 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.*/ 63 uint32_t infifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.*/ 64 uint32_t infifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.*/ 65 uint32_t infifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow.*/ 66 uint32_t infifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow.*/ 67 uint32_t outfifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.*/ 68 uint32_t outfifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.*/ 69 uint32_t outfifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow.*/ 70 uint32_t outfifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow.*/ 71 uint32_t reserved18 : 14; /*reserved*/ 72 }; 73 uint32_t val; 74 } int_raw[5]; 75 uint32_t reserved_3c; 76 union { 77 struct { 78 uint32_t in_done : 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ 79 uint32_t in_suc_eof : 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ 80 uint32_t in_err_eof : 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ 81 uint32_t out_done : 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ 82 uint32_t out_eof : 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ 83 uint32_t in_dscr_err : 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ 84 uint32_t out_dscr_err : 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ 85 uint32_t in_dscr_empty : 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ 86 uint32_t out_total_eof : 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ 87 uint32_t infifo_full_wm : 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ 88 uint32_t infifo_ovf_l1 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ 89 uint32_t infifo_udf_l1 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ 90 uint32_t infifo_ovf_l3 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ 91 uint32_t infifo_udf_l3 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ 92 uint32_t outfifo_ovf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ 93 uint32_t outfifo_udf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ 94 uint32_t outfifo_ovf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ 95 uint32_t outfifo_udf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ 96 uint32_t reserved18 : 14; /*reserved*/ 97 }; 98 uint32_t val; 99 } int_st[5]; 100 union { 101 struct { 102 uint32_t in_done : 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ 103 uint32_t in_suc_eof : 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ 104 uint32_t in_err_eof : 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ 105 uint32_t out_done : 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ 106 uint32_t out_eof : 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ 107 uint32_t in_dscr_err : 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ 108 uint32_t out_dscr_err : 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ 109 uint32_t in_dscr_empty : 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ 110 uint32_t out_total_eof : 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ 111 uint32_t infifo_full_wm : 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ 112 uint32_t infifo_ovf_l1 : 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ 113 uint32_t infifo_udf_l1 : 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ 114 uint32_t infifo_ovf_l3 : 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ 115 uint32_t infifo_udf_l3 : 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ 116 uint32_t outfifo_ovf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ 117 uint32_t outfifo_udf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ 118 uint32_t outfifo_ovf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ 119 uint32_t outfifo_udf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ 120 uint32_t reserved18 : 14; /*reserved*/ 121 }; 122 uint32_t val; 123 } int_ena[5]; 124 union { 125 struct { 126 uint32_t in_done : 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/ 127 uint32_t in_suc_eof : 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ 128 uint32_t in_err_eof : 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ 129 uint32_t out_done : 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ 130 uint32_t out_eof : 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ 131 uint32_t in_dscr_err : 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ 132 uint32_t out_dscr_err : 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ 133 uint32_t in_dscr_empty : 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ 134 uint32_t out_total_eof : 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ 135 uint32_t infifo_full_wm : 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ 136 uint32_t infifo_ovf_l1 : 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ 137 uint32_t infifo_udf_l1 : 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ 138 uint32_t infifo_ovf_l3 : 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ 139 uint32_t infifo_udf_l3 : 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ 140 uint32_t outfifo_ovf_l1 : 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ 141 uint32_t outfifo_udf_l1 : 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ 142 uint32_t outfifo_ovf_l3 : 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ 143 uint32_t outfifo_udf_l3 : 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ 144 uint32_t reserved18 : 14; /*reserved*/ 145 }; 146 uint32_t val; 147 } int_clr[5]; 148 union { 149 struct { 150 uint32_t infifo_full_l1 : 1; /*L1 Rx FIFO full signal for Rx channel 0.*/ 151 uint32_t infifo_empty_l1 : 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/ 152 uint32_t infifo_full_l2 : 1; /*L2 Rx FIFO full signal for Rx channel 0.*/ 153 uint32_t infifo_empty_l2 : 1; /*L2 Rx FIFO empty signal for Rx channel 0.*/ 154 uint32_t infifo_full_l3 : 1; /*L3 Rx FIFO full signal for Rx channel 0.*/ 155 uint32_t infifo_empty_l3 : 1; /*L3 Rx FIFO empty signal for Rx channel 0.*/ 156 uint32_t infifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/ 157 uint32_t infifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.*/ 158 uint32_t infifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.*/ 159 uint32_t in_remain_under_1b_l3 : 1; /*reserved*/ 160 uint32_t in_remain_under_2b_l3 : 1; /*reserved*/ 161 uint32_t in_remain_under_3b_l3 : 1; /*reserved*/ 162 uint32_t in_remain_under_4b_l3 : 1; /*reserved*/ 163 uint32_t in_buf_hungry : 1; /*reserved*/ 164 uint32_t reserved28 : 4; /*reserved*/ 165 }; 166 uint32_t val; 167 } infifo_status[5]; 168 union { 169 struct { 170 uint32_t outfifo_full_l1 : 1; /*L1 Tx FIFO full signal for Tx channel 0.*/ 171 uint32_t outfifo_empty_l1 : 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/ 172 uint32_t outfifo_full_l2 : 1; /*L2 Tx FIFO full signal for Tx channel 0.*/ 173 uint32_t outfifo_empty_l2 : 1; /*L2 Tx FIFO empty signal for Tx channel 0.*/ 174 uint32_t outfifo_full_l3 : 1; /*L3 Tx FIFO full signal for Tx channel 0.*/ 175 uint32_t outfifo_empty_l3 : 1; /*L3 Tx FIFO empty signal for Tx channel 0.*/ 176 uint32_t outfifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/ 177 uint32_t outfifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.*/ 178 uint32_t outfifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0.*/ 179 uint32_t out_remain_under_1b_l3 : 1; /*reserved*/ 180 uint32_t out_remain_under_2b_l3 : 1; /*reserved*/ 181 uint32_t out_remain_under_3b_l3 : 1; /*reserved*/ 182 uint32_t out_remain_under_4b_l3 : 1; /*reserved*/ 183 uint32_t reserved27 : 5; /*reserved*/ 184 }; 185 uint32_t val; 186 } outfifo_status[5]; 187 union { 188 struct { 189 uint32_t outfifo_wdata : 9; /*This register stores the data that need to be pushed into DMA FIFO.*/ 190 uint32_t outfifo_push : 1; /*Set this bit to push data into DMA FIFO.*/ 191 uint32_t reserved10 : 22; /*reserved*/ 192 }; 193 uint32_t val; 194 } out_push[5]; 195 union { 196 struct { 197 uint32_t infifo_rdata : 12; /*This register stores the data popping from DMA FIFO.*/ 198 uint32_t infifo_pop : 1; /*Set this bit to pop data from DMA FIFO.*/ 199 uint32_t reserved13 : 19; /*reserved*/ 200 }; 201 uint32_t val; 202 } in_pop[5]; 203 union { 204 struct { 205 uint32_t addr : 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/ 206 uint32_t stop : 1; /*Set this bit to stop dealing with the outlink descriptors.*/ 207 uint32_t start : 1; /*Set this bit to start dealing with the outlink descriptors.*/ 208 uint32_t restart : 1; /*Set this bit to restart a new outlink from the last address.*/ 209 uint32_t park : 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/ 210 uint32_t reserved24 : 8; 211 }; 212 uint32_t val; 213 } out_link[5]; 214 union { 215 struct { 216 uint32_t addr : 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/ 217 uint32_t auto_ret : 1; /*Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data.*/ 218 uint32_t stop : 1; /*Set this bit to stop dealing with the inlink descriptors.*/ 219 uint32_t start : 1; /*Set this bit to start dealing with the inlink descriptors.*/ 220 uint32_t restart : 1; /*Set this bit to mount a new inlink descriptor.*/ 221 uint32_t park : 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/ 222 uint32_t reserved25 : 7; 223 }; 224 uint32_t val; 225 } in_link[5]; 226 union { 227 struct { 228 uint32_t inlink_dscr_addr : 18; /*This register stores the current inlink descriptor's address.*/ 229 uint32_t in_dscr_state : 2; /*reserved*/ 230 uint32_t in_state : 3; /*reserved*/ 231 uint32_t reserved23 : 9; /*reserved*/ 232 }; 233 uint32_t val; 234 } in_state[5]; 235 union { 236 struct { 237 uint32_t outlink_dscr_addr : 18; /*This register stores the current outlink descriptor's address.*/ 238 uint32_t out_dscr_state : 2; /*reserved*/ 239 uint32_t out_state : 3; /*reserved*/ 240 uint32_t reserved23 : 9; /*reserved*/ 241 }; 242 uint32_t val; 243 } out_state[5]; 244 uint32_t out_eof_des_addr[5]; /*This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.*/ 245 uint32_t in_suc_eof_des_addr[5]; /*This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.*/ 246 uint32_t in_err_eof_des_addr[5]; /*This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ 247 uint32_t out_eof_bfr_des_addr[5]; /*This register stores the address of the outlink descriptor before the last outlink descriptor.*/ 248 union { 249 struct { 250 uint32_t ahb_testmode : 3; /*reserved*/ 251 uint32_t reserved3 : 1; /*reserved*/ 252 uint32_t ahb_testaddr : 2; /*reserved*/ 253 uint32_t reserved6 : 26; /*reserved*/ 254 }; 255 uint32_t val; 256 } ahb_test; 257 uint32_t in_dscr[5]; /*The address of the current inlink descriptor x.*/ 258 uint32_t in_dscr_bf0[5]; /*The address of the last inlink descriptor x-1.*/ 259 uint32_t in_dscr_bf1[5]; /*The address of the second-to-last inlink descriptor x-2.*/ 260 uint32_t out_dscr[5]; /*The address of the current outlink descriptor y.*/ 261 uint32_t out_dscr_bf0[5]; /*The address of the last outlink descriptor y-1.*/ 262 uint32_t out_dscr_bf1[5]; /*The address of the second-to-last inlink descriptor y-2.*/ 263 union { 264 struct { 265 uint32_t reserved0 : 4; /*reserved*/ 266 uint32_t ram_force_pd : 1; /*power down*/ 267 uint32_t ram_force_pu : 1; 268 uint32_t ram_clk_fo : 1; /*1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA.*/ 269 uint32_t reserved7 : 25; /*reserved*/ 270 }; 271 uint32_t val; 272 } pd_conf; 273 union { 274 struct { 275 uint32_t tx_weight : 4; /*The weight of Tx channel 0.*/ 276 uint32_t rx_weight : 4; /*The weight of Rx channel 0.*/ 277 uint32_t reserved8 : 24; 278 }; 279 uint32_t val; 280 } wight[5]; 281 union { 282 struct { 283 uint32_t tx_pri : 4; /*The priority of Tx channel 0. The larger of the value the higher of the priority.*/ 284 uint32_t rx_pri : 4; /*The priority of Rx channel 0. The larger of the value the higher of the priority.*/ 285 uint32_t reserved8 : 24; 286 }; 287 uint32_t val; 288 } pri[5]; 289 union { 290 struct { 291 uint32_t ahbm_rst_inter : 1; /*Set this bit then clear this bit to reset the internal ahb FSM.*/ 292 uint32_t ahbm_rst_exter : 1; /*Set this bit then clear this bit to reset the external ahb FSM.*/ 293 uint32_t arb_pri_dis : 1; /*Set this bit to disable priority arbitration function.*/ 294 uint32_t clk_en : 1; 295 uint32_t reserved4 : 28; 296 }; 297 uint32_t val; 298 } misc_conf; 299 union { 300 struct { 301 uint32_t peri_in_sel : 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2*/ 302 uint32_t peri_out_sel : 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2*/ 303 uint32_t reserved12 : 20; 304 }; 305 uint32_t val; 306 } peri_sel[5]; 307 union { 308 struct { 309 uint32_t in_size : 5; /*This register is used to configure the size of L2 Rx FIFO for Rx channel 0. 0:16 bytes*/ 310 uint32_t out_size : 5; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes*/ 311 uint32_t reserved10 : 22; 312 }; 313 uint32_t val; 314 } sram_size[5]; 315 uint32_t date; /*register version.*/ 316 } gdma_dev_t; 317 318 _Static_assert(sizeof(gdma_dev_t) == 0x244, "incorrect size of gdma_dev_t."); 319 320 extern gdma_dev_t GDMA; 321 322 #ifdef __cplusplus 323 } 324 #endif 325
