1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef BOOTLOADER_BUILD 15 16 #include <stdint.h> 17 #include <stdlib.h> 18 #include "esp_attr.h" 19 #include "sdkconfig.h" 20 #include "soc/soc.h" 21 #include "soc/soc_memory_layout.h" 22 #include "esp_heap_caps.h" 23 24 /** 25 * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC. 26 * Each type of memory map consists of one or more regions in the address space. 27 * Each type contains an array of prioritized capabilities. 28 * Types with later entries are only taken if earlier ones can't fulfill the memory request. 29 * 30 * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory. 31 * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM. 32 * - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM. 33 * - Most other malloc caps only fit in one region anyway. 34 * 35 */ 36 const soc_memory_type_desc_t soc_memory_types[] = { 37 // Type 0: DRAM 38 { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, 39 // Type 1: DRAM used for startup stacks 40 { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, 41 // Type 2: DRAM which has an alias on the I-port 42 { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, 43 // Type 3: IRAM 44 { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, 45 // Type 4: RTCRAM 46 { "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false}, 47 }; 48 49 #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE 50 #define SOC_MEMORY_TYPE_DEFAULT 0 51 #else 52 #define SOC_MEMORY_TYPE_DEFAULT 2 53 #endif 54 55 const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); 56 57 /** 58 * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type. 59 * 60 * @note Because of requirements in the coalescing code which merges adjacent regions, 61 * this list should always be sorted from low to high by start address. 62 * 63 */ 64 const soc_memory_region_t soc_memory_regions[] = { 65 { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //Block 4, can be remapped to ROM, can be used as trace memory 66 { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Block 5, can be remapped to ROM, can be used as trace memory 67 { 0x3FCC0000, 0x20000, 1, 0x403C0000}, //Block 9, can be used as trace memory 68 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 69 { 0x50000000, 0x2000, 4, 0}, //Fast RTC memory 70 #endif 71 }; 72 73 const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); 74 75 76 extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end; 77 78 /** 79 * Reserved memory regions. 80 * These are removed from the soc_memory_regions array when heaps are created. 81 * 82 */ 83 84 // Static data region. DRAM used by data+bss and possibly rodata 85 SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data); 86 87 // Target has a big D/IRAM region, the part used by code is reserved 88 // The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address 89 #define I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) 90 SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code); 91 92 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 93 /* We use _rtc_force_slow_end not _rtc_noinit_end here, as rtc "fast" memory ends up in RTC SLOW 94 region on C3, no differentiation. And _rtc_force_slow_end is the end of all the static RTC sections. 95 */ 96 SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data); 97 #endif 98 99 #endif // BOOTLOADER_BUILD 100
