1 #pragma once
2 
3 /* put target-specific macros into include/target/idf_performance_target.h */
4 #include "idf_performance_target.h"
5 
6 /* Define default values in this file with #ifndef if the value could been overwritten in the target-specific headers
7  * above. Forgetting this will produce compile-time warnings.
8  */
9 
10 #ifndef IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP
11 #define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP                     200
12 #endif
13 #ifndef IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_PSRAM
14 #define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_PSRAM               300
15 #endif
16 #ifndef IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_UNICORE
17 #define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_UNICORE             130
18 #endif
19 #ifndef IDF_PERFORMANCE_MAX_ESP_TIMER_GET_TIME_PER_CALL
20 #define IDF_PERFORMANCE_MAX_ESP_TIMER_GET_TIME_PER_CALL                         1000
21 #endif
22 
23 #ifndef IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING
24 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                               15
25 #endif
26 #ifndef IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA
27 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA                        15
28 #endif
29 
30 /* Due to code size & linker layout differences interacting with cache, VFS
31    microbenchmark currently runs slower with PSRAM enabled. */
32 #ifndef IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME
33 #define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME                           20000
34 #endif
35 #ifndef IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM
36 #define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM                     25000
37 #endif
38 
39 // throughput performance by iperf
40 #ifndef IDF_PERFORMANCE_MIN_TCP_RX_THROUGHPUT
41 #define IDF_PERFORMANCE_MIN_TCP_RX_THROUGHPUT                                   45
42 #endif
43 #ifndef IDF_PERFORMANCE_MIN_TCP_TX_THROUGHPUT
44 #define IDF_PERFORMANCE_MIN_TCP_TX_THROUGHPUT                                   40
45 #endif
46 #ifndef IDF_PERFORMANCE_MIN_UDP_RX_THROUGHPUT
47 #define IDF_PERFORMANCE_MIN_UDP_RX_THROUGHPUT                                   64
48 #endif
49 #ifndef IDF_PERFORMANCE_MIN_UDP_TX_THROUGHPUT
50 #define IDF_PERFORMANCE_MIN_UDP_TX_THROUGHPUT                                   50
51 #endif
52 
53 // events dispatched per second by event loop library
54 #ifndef IDF_PERFORMANCE_MIN_EVENT_DISPATCH
55 #define IDF_PERFORMANCE_MIN_EVENT_DISPATCH                                      25000
56 #endif
57 #ifndef IDF_PERFORMANCE_MIN_EVENT_DISPATCH_PSRAM
58 #define IDF_PERFORMANCE_MIN_EVENT_DISPATCH_PSRAM                                21000
59 #endif
60 
61 #ifndef IDF_PERFORMANCE_MAX_SPILL_REG_CYCLES
62 #define IDF_PERFORMANCE_MAX_SPILL_REG_CYCLES                                    150
63 #endif
64 #ifndef IDF_PERFORMANCE_MAX_ISR_ENTER_CYCLES
65 #define IDF_PERFORMANCE_MAX_ISR_ENTER_CYCLES                                    290
66 #endif
67 #ifndef IDF_PERFORMANCE_MAX_ISR_EXIT_CYCLES
68 #define IDF_PERFORMANCE_MAX_ISR_EXIT_CYCLES                                     565
69 #endif
70 
71 #ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_4BIT
72 #define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_4BIT                   12200
73 #endif
74 #ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT
75 #define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT                   12200
76 #endif
77 #ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_1BIT
78 #define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_1BIT                   4000
79 #endif
80 #ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_1BIT
81 #define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_1BIT                   4000
82 #endif
83 #ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_SPI
84 #define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_SPI                    1000
85 #endif
86 #ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_SPI
87 #define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_SPI                    1000
88 #endif
89 
90 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_WR_4B
91 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_WR_4B               22200
92 #endif
93 // IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_RD_4B in target file
94 // IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_WR_2KB in target file
95 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_RD_2KB
96 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_RD_2KB              (7088*1000)
97 #endif
98 //This value is usually around 44K, but there are some chips with such low performance....
99 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_ERASE
100 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_ERASE               12000
101 #endif
102 
103 // IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_4B in target file
104 // IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_4B in target file
105 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_2KB
106 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_2KB                     (694*1000)
107 #endif
108 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_2KB
109 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_2KB                     (7797*1000)
110 #endif
111 // IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_ERASE in target file
112 
113 // IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_WR_4B in target file
114 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_RD_4B
115 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_RD_4B                 50100
116 #endif
117 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_WR_2KB
118 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_WR_2KB                (618*1000)
119 #endif
120 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_RD_2KB
121 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_RD_2KB                (1601*1000)
122 #endif
123 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_ERASE
124 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_SPI1_ERASE                 59800
125 #endif
126 
127 // Some performance value based on the test against GD chip with single_core config.
128 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_4B
129 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_4B                  64900
130 #endif
131 // IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B in target file
132 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_2KB
133 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_2KB                 (475*1000)
134 #endif
135 // IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB in target file
136 // IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE in target file
137 
138 //time to perform the task selection plus context switch (from task)
139 #ifndef IDF_PERFORMANCE_MAX_SCHEDULING_TIME
140 #define IDF_PERFORMANCE_MAX_SCHEDULING_TIME                                     2000
141 #endif
142 
143 #ifndef IDF_PERFORMANCE_MAX_MALLOC_DEFAULT_AVERAGE_TIME
144 #define IDF_PERFORMANCE_MAX_MALLOC_DEFAULT_AVERAGE_TIME                         2600
145 #endif
146 
147 #ifndef IDF_PERFORMANCE_MAX_FREE_DEFAULT_AVERAGE_TIME
148 #define IDF_PERFORMANCE_MAX_FREE_DEFAULT_AVERAGE_TIME                           950
149 #endif
150