1 // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 // The HAL layer for ADC (common part)
16
17 #include "hal/adc_hal.h"
18 #include "hal/adc_hal_conf.h"
19 #include "hal/adc_types.h"
20
adc_hal_digi_deinit(void)21 void adc_hal_digi_deinit(void)
22 {
23 adc_ll_digi_clear_pattern_table(ADC_NUM_1);
24 adc_ll_digi_clear_pattern_table(ADC_NUM_2);
25 }
26
adc_hal_digi_controller_config(const adc_digi_config_t * cfg)27 void adc_hal_digi_controller_config(const adc_digi_config_t *cfg)
28 {
29 /* Single channel mode or multi channel mode. */
30 adc_ll_digi_set_convert_mode(cfg->conv_mode);
31 if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) {
32 adc_ll_set_controller(ADC_NUM_1, ADC_CTRL_DIG);
33 if (cfg->adc1_pattern_len) {
34 adc_ll_digi_clear_pattern_table(ADC_NUM_1);
35 adc_ll_digi_set_pattern_table_len(ADC_NUM_1, cfg->adc1_pattern_len);
36 for (uint32_t i = 0; i < cfg->adc1_pattern_len; i++) {
37 adc_ll_digi_set_pattern_table(ADC_NUM_1, i, cfg->adc1_pattern[i]);
38 }
39 }
40 }
41 if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_2) {
42 adc_ll_set_controller(ADC_NUM_2, ADC_CTRL_DIG);
43 if (cfg->adc2_pattern_len) {
44 adc_ll_digi_clear_pattern_table(ADC_NUM_2);
45 adc_ll_digi_set_pattern_table_len(ADC_NUM_2, cfg->adc2_pattern_len);
46 for (uint32_t i = 0; i < cfg->adc2_pattern_len; i++) {
47 adc_ll_digi_set_pattern_table(ADC_NUM_2, i, cfg->adc2_pattern[i]);
48 }
49 }
50 }
51 adc_ll_digi_set_output_format(cfg->format);
52 if (cfg->conv_limit_en) {
53 adc_ll_digi_set_convert_limit_num(cfg->conv_limit_num);
54 adc_ll_digi_convert_limit_enable();
55 } else {
56 adc_ll_digi_convert_limit_disable();
57 }
58 adc_ll_digi_set_data_source(ADC_I2S_DATA_SRC_ADC);
59 }
60
adc_hal_hall_convert(void)61 int adc_hal_hall_convert(void)
62 {
63 int Sens_Vp0;
64 int Sens_Vn0;
65 int Sens_Vp1;
66 int Sens_Vn1;
67 int hall_value;
68 // convert for 4 times with different phase and outputs
69 adc_ll_hall_phase_disable(); // hall phase
70 adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_0, &Sens_Vp0 );
71 adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_3, &Sens_Vn0 );
72 adc_ll_hall_phase_enable();
73 adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_0, &Sens_Vp1 );
74 adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_3, &Sens_Vn1 );
75 hall_value = (Sens_Vp1 - Sens_Vp0) - (Sens_Vn1 - Sens_Vn0);
76 return hall_value;
77 }
78
