1
2 // Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
3 //
4 // Licensed under the Apache License, Version 2.0 (the "License");
5 // you may not use this file except in compliance with the License.
6 // You may obtain a copy of the License at
7 //
8 // http://www.apache.org/licenses/LICENSE-2.0
9 //
10 // Unless required by applicable law or agreed to in writing, software
11 // distributed under the License is distributed on an "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 // See the License for the specific language governing permissions and
14 // limitations under the License.
15
16 #include <stdint.h>
17 #include <sys/cdefs.h>
18 #include <sys/time.h>
19 #include <sys/param.h>
20 #include "sdkconfig.h"
21 #include "esp_attr.h"
22 #include "esp_log.h"
23 #include "esp32s3/clk.h"
24 #include "esp_clk_internal.h"
25 #include "esp32s3/rom/ets_sys.h"
26 #include "esp32s3/rom/rtc.h"
27 #include "esp_rom_uart.h"
28 #include "soc/system_reg.h"
29 #include "soc/dport_access.h"
30 #include "soc/soc.h"
31 #include "soc/rtc.h"
32 #include "soc/rtc_periph.h"
33 #include "soc/i2s_reg.h"
34 #include "hal/cpu_hal.h"
35 #include "hal/wdt_hal.h"
36 #include "driver/periph_ctrl.h"
37 #include "bootloader_clock.h"
38 #include "soc/syscon_reg.h"
39
40 static const char *TAG = "clk";
41
42 /* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
43 * Larger values increase startup delay. Smaller values may cause false positive
44 * detection (i.e. oscillator runs for a few cycles and then stops).
45 */
46 #define SLOW_CLK_CAL_CYCLES CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES
47
48 #ifdef CONFIG_ESP32S3_RTC_XTAL_CAL_RETRY
49 #define RTC_XTAL_CAL_RETRY CONFIG_ESP32S3_RTC_XTAL_CAL_RETRY
50 #else
51 #define RTC_XTAL_CAL_RETRY 1
52 #endif
53
54 /* Lower threshold for a reasonably-looking calibration value for a 32k XTAL.
55 * The ideal value (assuming 32768 Hz frequency) is 1000000/32768*(2**19) = 16*10^6.
56 */
57 #define MIN_32K_XTAL_CAL_VAL 15000000L
58
59 /* Indicates that this 32k oscillator gets input from external oscillator, rather
60 * than a crystal.
61 */
62 #define EXT_OSC_FLAG BIT(3)
63
64 /* This is almost the same as rtc_slow_freq_t, except that we define
65 * an extra enum member for the external 32k oscillator.
66 * For convenience, lower 2 bits should correspond to rtc_slow_freq_t values.
67 */
68 typedef enum {
69 SLOW_CLK_RTC = RTC_SLOW_FREQ_RTC, //!< Internal 90 kHz RC oscillator
70 SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, //!< External 32 kHz XTAL
71 SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, //!< Internal 8 MHz RC oscillator, divided by 256
72 SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin
73 } slow_clk_sel_t;
74
75 static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
76
esp_clk_init(void)77 __attribute__((weak)) void esp_clk_init(void)
78 {
79 rtc_config_t cfg = RTC_CONFIG_DEFAULT();
80 rtc_init(cfg);
81
82 assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
83
84 rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
85
86 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
87 // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
88 // If the frequency changes from 90kHz to 32kHz, then the timeout set for the WDT will increase 2.8 times.
89 // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
90 // This prevents excessive delay before resetting in case the supply voltage is drawdown.
91 // (If frequency is changed from 90kHz to 32kHz then WDT timeout will increased to 1.6sec * 90/32 = 4.5 sec).
92 wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
93 uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
94 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
95 wdt_hal_feed(&rtc_wdt_ctx);
96 //Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same
97 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
98 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
99 #endif
100
101 #if defined(CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS)
102 select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
103 #elif defined(CONFIG_ESP32S3_RTC_CLK_SRC_EXT_OSC)
104 select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
105 #elif defined(CONFIG_ESP32S3_RTC_CLK_SRC_INT_8MD256)
106 select_rtc_slow_clk(SLOW_CLK_8MD256);
107 #else
108 select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
109 #endif
110
111 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
112 // After changing a frequency WDT timeout needs to be set for new frequency.
113 stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000ULL);
114 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
115 wdt_hal_feed(&rtc_wdt_ctx);
116 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
117 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
118 #endif
119
120 rtc_cpu_freq_config_t old_config, new_config;
121 rtc_clk_cpu_freq_get_config(&old_config);
122 const uint32_t old_freq_mhz = old_config.freq_mhz;
123 const uint32_t new_freq_mhz = CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ;
124
125 bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
126 assert(res);
127
128 // Wait for UART TX to finish, otherwise some UART output will be lost
129 // when switching APB frequency
130 if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
131 esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
132 }
133
134 rtc_clk_cpu_freq_set_config(&new_config);
135
136 // Re calculate the ccount to make time calculation correct.
137 cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz );
138 }
139
select_rtc_slow_clk(slow_clk_sel_t slow_clk)140 static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
141 {
142 rtc_slow_freq_t rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
143 uint32_t cal_val = 0;
144 /* number of times to repeat 32k XTAL calibration
145 * before giving up and switching to the internal RC
146 */
147 int retry_32k_xtal = RTC_XTAL_CAL_RETRY;
148
149 do {
150 if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
151 /* 32k XTAL oscillator needs to be enabled and running before it can
152 * be used. Hardware doesn't have a direct way of checking if the
153 * oscillator is running. Here we use rtc_clk_cal function to count
154 * the number of main XTAL cycles in the given number of 32k XTAL
155 * oscillator cycles. If the 32k XTAL has not started up, calibration
156 * will time out, returning 0.
157 */
158 ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
159 if (slow_clk == SLOW_CLK_32K_XTAL) {
160 rtc_clk_32k_enable(true);
161 } else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
162 rtc_clk_32k_enable_external();
163 }
164 // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
165 if (SLOW_CLK_CAL_CYCLES > 0) {
166 cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
167 if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) {
168 if (retry_32k_xtal-- > 0) {
169 continue;
170 }
171 ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 90 kHz oscillator");
172 rtc_slow_freq = RTC_SLOW_FREQ_RTC;
173 }
174 }
175 } else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) {
176 rtc_clk_8m_enable(true, true);
177 }
178 rtc_clk_slow_freq_set(rtc_slow_freq);
179
180 if (SLOW_CLK_CAL_CYCLES > 0) {
181 /* TODO: 32k XTAL oscillator has some frequency drift at startup.
182 * Improve calibration routine to wait until the frequency is stable.
183 */
184 cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
185 } else {
186 const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
187 cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
188 }
189 } while (cal_val == 0);
190 ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
191 esp_clk_slowclk_cal_set(cal_val);
192 }
193
rtc_clk_select_rtc_slow_clk(void)194 void rtc_clk_select_rtc_slow_clk(void)
195 {
196 select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL);
197 }
198
199 /* This function is not exposed as an API at this point.
200 * All peripheral clocks are default enabled after chip is powered on.
201 * This function disables some peripheral clocks when cpu starts.
202 * These peripheral clocks are enabled when the peripherals are initialized
203 * and disabled when they are de-initialized.
204 */
esp_perip_clk_init(void)205 __attribute__((weak)) void esp_perip_clk_init(void)
206 {
207 uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
208 uint32_t common_perip_clk1 = 0;
209
210 #if CONFIG_FREERTOS_UNICORE
211 RESET_REASON rst_reas[1];
212 #else
213 RESET_REASON rst_reas[2];
214 #endif
215
216 rst_reas[0] = rtc_get_reset_reason(0);
217 #if !CONFIG_FREERTOS_UNICORE
218 rst_reas[1] = rtc_get_reset_reason(1);
219 #endif
220
221 /* For reason that only reset CPU, do not disable the clocks
222 * that have been enabled before reset.
223 */
224 if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET)
225 #if !CONFIG_FREERTOS_UNICORE
226 || (rst_reas[1] >= TG0WDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
227 #endif
228 ) {
229 common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
230 hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
231 wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
232 } else {
233 common_perip_clk = SYSTEM_WDG_CLK_EN |
234 SYSTEM_I2S0_CLK_EN |
235 #if CONFIG_CONSOLE_UART_NUM != 0
236 SYSTEM_UART_CLK_EN |
237 #endif
238 #if CONFIG_CONSOLE_UART_NUM != 1
239 SYSTEM_UART1_CLK_EN |
240 #endif
241 #if CONFIG_CONSOLE_UART_NUM != 2
242 SYSTEM_UART2_CLK_EN |
243 #endif
244 SYSTEM_USB_CLK_EN |
245 SYSTEM_SPI2_CLK_EN |
246 SYSTEM_I2C_EXT0_CLK_EN |
247 SYSTEM_UHCI0_CLK_EN |
248 SYSTEM_RMT_CLK_EN |
249 SYSTEM_PCNT_CLK_EN |
250 SYSTEM_LEDC_CLK_EN |
251 SYSTEM_TIMERGROUP1_CLK_EN |
252 SYSTEM_SPI3_CLK_EN |
253 SYSTEM_SPI4_CLK_EN |
254 SYSTEM_PWM0_CLK_EN |
255 SYSTEM_TWAI_CLK_EN |
256 SYSTEM_PWM1_CLK_EN |
257 SYSTEM_I2S1_CLK_EN |
258 SYSTEM_SPI2_DMA_CLK_EN |
259 SYSTEM_SPI3_DMA_CLK_EN |
260 SYSTEM_PWM2_CLK_EN |
261 SYSTEM_PWM3_CLK_EN;
262 common_perip_clk1 = 0;
263 hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN |
264 SYSTEM_CRYPTO_SHA_CLK_EN |
265 SYSTEM_CRYPTO_RSA_CLK_EN;
266 wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
267 SYSTEM_WIFI_CLK_BT_EN_M |
268 SYSTEM_WIFI_CLK_UNUSED_BIT5 |
269 SYSTEM_WIFI_CLK_UNUSED_BIT12 |
270 SYSTEM_WIFI_CLK_SDIO_HOST_EN;
271 }
272
273 //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
274 common_perip_clk |= SYSTEM_I2S0_CLK_EN |
275 #if CONFIG_CONSOLE_UART_NUM != 0
276 SYSTEM_UART_CLK_EN |
277 #endif
278 #if CONFIG_CONSOLE_UART_NUM != 1
279 SYSTEM_UART1_CLK_EN |
280 #endif
281 #if CONFIG_CONSOLE_UART_NUM != 2
282 SYSTEM_UART2_CLK_EN |
283 #endif
284 SYSTEM_USB_CLK_EN |
285 SYSTEM_SPI2_CLK_EN |
286 SYSTEM_I2C_EXT0_CLK_EN |
287 SYSTEM_UHCI0_CLK_EN |
288 SYSTEM_RMT_CLK_EN |
289 SYSTEM_UHCI1_CLK_EN |
290 SYSTEM_SPI3_CLK_EN |
291 SYSTEM_SPI4_CLK_EN |
292 SYSTEM_I2C_EXT1_CLK_EN |
293 SYSTEM_I2S1_CLK_EN |
294 SYSTEM_SPI2_DMA_CLK_EN |
295 SYSTEM_SPI3_DMA_CLK_EN;
296 common_perip_clk1 = 0;
297
298 /* Disable some peripheral clocks. */
299 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
300 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
301
302 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1);
303 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1);
304
305 /* Disable hardware crypto clocks. */
306 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
307 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
308
309 /* Disable WiFi/BT/SDIO clocks. */
310 CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
311 SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
312
313 /* Enable RNG clock. */
314 periph_module_enable(PERIPH_RNG_MODULE);
315 }
316
