1 /*
2  * copyright (c) Espressif System 2019
3  *
4  */
5 
6 #ifndef _ROM_OPI_FLASH_H_
7 #define _ROM_OPI_FLASH_H_
8 #include <stdio.h>
9 #include <string.h>
10 #include <stdint.h>
11 #include "spi_flash.h"
12 
13 #ifdef __cplusplus
14 extern "C" {
15 #endif
16 
17 typedef struct {
18     uint16_t cmd;                /*!< Command value */
19     uint16_t cmdBitLen;          /*!< Command byte length*/
20     uint32_t *addr;              /*!< Point to address value*/
21     uint32_t addrBitLen;         /*!< Address byte length*/
22     uint32_t *txData;            /*!< Point to send data buffer*/
23     uint32_t txDataBitLen;       /*!< Send data byte length.*/
24     uint32_t *rxData;            /*!< Point to recevie data buffer*/
25     uint32_t rxDataBitLen;       /*!< Recevie Data byte length.*/
26     uint32_t dummyBitLen;
27 } esp_rom_spi_cmd_t;
28 
29 #define ESP_ROM_OPIFLASH_MUX_TAKE()
30 #define ESP_ROM_OPIFLASH_MUX_GIVE()
31 #define ESP_ROM_OPIFLASH_SEL_CS0     (BIT(0))
32 #define ESP_ROM_OPIFLASH_SEL_CS1     (BIT(1))
33 
34 // Definition of MX25UM25645G Octa Flash
35 // SPI status register
36 #define ESP_ROM_SPIFLASH_BUSY_FLAG     BIT0
37 #define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
38 #define ESP_ROM_SPIFLASH_BP0           BIT2
39 #define ESP_ROM_SPIFLASH_BP1           BIT3
40 #define ESP_ROM_SPIFLASH_BP2           BIT4
41 #define ESP_ROM_SPIFLASH_WR_PROTECT    (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
42 #define ESP_ROM_SPIFLASH_QE            BIT9
43 #define ESP_ROM_SPIFLASH_BP_MASK_ISSI  (BIT7 | BIT5 | BIT4 | BIT3 | BIT2)
44 
45 #define FLASH_OP_MODE_RDCMD_DOUT       0x3B
46 #define ESP_ROM_FLASH_SECTOR_SIZE      0x1000
47 #define ESP_ROM_FLASH_BLOCK_SIZE_64K   0x10000
48 #define ESP_ROM_FLASH_PAGE_SIZE        256
49 
50 // FLASH commands
51 #define ROM_FLASH_CMD_RDID             0x9F
52 #define ROM_FLASH_CMD_WRSR             0x01
53 #define ROM_FLASH_CMD_WRSR2            0x31 /* Not all SPI flash uses this command */
54 #define ROM_FLASH_CMD_WREN             0x06
55 #define ROM_FLASH_CMD_WRDI             0x04
56 #define ROM_FLASH_CMD_RDSR             0x05
57 #define ROM_FLASH_CMD_RDSR2            0x35 /* Not all SPI flash uses this command */
58 #define ROM_FLASH_CMD_ERASE_SEC        0x20
59 #define ROM_FLASH_CMD_ERASE_BLK_32K    0x52
60 #define ROM_FLASH_CMD_ERASE_BLK_64K    0xD8
61 #define ROM_FLASH_CMD_OTPEN            0x3A /* Enable OTP mode, not all SPI flash uses this command */
62 #define ROM_FLASH_CMD_RSTEN            0x66
63 #define ROM_FLASH_CMD_RST              0x99
64 
65 #define ROM_FLASH_CMD_SE4B             0x21
66 #define ROM_FLASH_CMD_SE4B_OCT         0xDE21
67 #define ROM_FLASH_CMD_BE4B             0xDC
68 #define ROM_FLASH_CMD_BE4B_OCT         0x23DC
69 #define ROM_FLASH_CMD_RSTEN_OCT        0x9966
70 #define ROM_FLASH_CMD_RST_OCT          0x6699
71 
72 #define ROM_FLASH_CMD_FSTRD4B_STR      0x13EC
73 #define ROM_FLASH_CMD_FSTRD4B_DTR      0x11EE
74 #define ROM_FLASH_CMD_FSTRD4B          0x0C
75 #define ROM_FLASH_CMD_PP4B             0x12
76 #define ROM_FLASH_CMD_PP4B_OCT         0xED12
77 
78 #define ROM_FLASH_CMD_RDID_OCT         0x609F
79 #define ROM_FLASH_CMD_WREN_OCT         0xF906
80 #define ROM_FLASH_CMD_RDSR_OCT         0xFA05
81 #define ROM_FLASH_CMD_RDCR2            0x71
82 #define ROM_FLASH_CMD_RDCR2_OCT        0x8E71
83 #define ROM_FLASH_CMD_WRCR2            0x72
84 #define ROM_FLASH_CMD_WRCR2_OCT        0x8D72
85 
86 // Definitions for GigaDevice GD25LX256E Flash
87 #define ROM_FLASH_CMD_RDFSR_GD            0x70
88 #define ROM_FLASH_CMD_RD_GD               0x03
89 #define ROM_FLASH_CMD_RD4B_GD             0x13
90 #define ROM_FLASH_CMD_FSTRD_GD            0x0B
91 #define ROM_FLASH_CMD_FSTRD4B_GD          0x0C
92 #define ROM_FLASH_CMD_FSTRD_OOUT_GD       0x8B
93 #define ROM_FLASH_CMD_FSTRD4B_OOUT_GD     0x7C
94 #define ROM_FLASH_CMD_FSTRD_OIOSTR_GD     0xCB
95 #define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD   0xCC
96 #define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD   0xFD
97 
98 #define ROM_FLASH_CMD_PP_GD               0x02
99 #define ROM_FLASH_CMD_PP4B_GD             0x12
100 #define ROM_FLASH_CMD_PP_OOUT_GD          0x82
101 #define ROM_FLASH_CMD_PP4B_OOUT_GD        0x84
102 #define ROM_FLASH_CMD_PP_OIO_GD           0xC2
103 #define ROM_FLASH_CMD_PP4B_OIOSTR_GD      0x8E
104 
105 #define ROM_FLASH_CMD_SE_GD               0x20
106 #define ROM_FLASH_CMD_SE4B_GD             0x21
107 #define ROM_FLASH_CMD_BE32K_GD            0x52
108 #define ROM_FLASH_CMD_BE32K4B_GD          0x5C
109 #define ROM_FLASH_CMD_BE64K_GD            0xD8
110 #define ROM_FLASH_CMD_BE64K4B_GD          0xDC
111 
112 #define ROM_FLASH_CMD_EN4B_GD             0xB7
113 #define ROM_FLASH_CMD_DIS4B_GD            0xE9
114 
115 // spi user mode command config
116 
117 /**
118  * @brief Config the spi user command
119  * @param spi_num spi port
120  * @param pcmd pointer to accept the spi command struct
121  */
122 void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t* pcmd);
123 
124 /**
125  * @brief Start a spi user command sequence
126  * @param spi_num spi port
127  * @param rx_buf buffer pointer to receive data
128  * @param rx_len receive data length in byte
129  * @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1
130  * @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission
131  */
132 void esp_rom_spi_cmd_start(int spi_num, uint8_t* rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase);
133 
134 /**
135  * @brief Config opi flash pads according to efuse settings.
136  */
137 void esp_rom_opiflash_pin_config(void);
138 
139 // set SPI read/write mode
140 /**
141  * @brief Set SPI operation mode
142  * @param spi_num spi port
143  * @param mode Flash Read Mode
144  */
145 void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
146 
147 /**
148  * @brief Set data swap mode in DTR(DDR) mode
149  * @param spi_num spi port
150  * @param wr_swap to decide whether to swap fifo data in dtr write operation
151  * @param rd_swap to decide whether to swap fifo data in dtr read operation
152  */
153 void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap);
154 
155 
156 /**
157  * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G)
158  * @param spi_num spi port
159  */
160 void esp_rom_opiflash_mode_reset(int spi_num);
161 
162 #if 0
163 // MX25UM25645G opi flash interface
164 /**
165  * @brief To execute a flash operation command
166  * @param spi_num spi port
167  * @param mode Flash Read Mode
168  * @param cmd data to send in command field
169  * @param cmd_bit_len bit length of command field
170  * @param addr data to send in address field
171  * @param addr_bit_len bit length of address field
172  * @param dummy_bits bit length of dummy field
173  * @param mosi_data data buffer to be sent in mosi field
174  * @param mosi_bit_len bit length of data buffer to be sent in mosi field
175  * @param miso_data data buffer to accept data in miso field
176  * @param miso_bit_len bit length of data buffer to accept data in miso field
177  * @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1
178  * @param is_write_erase_operation to indicate whether this a write or erase flash operation
179  */
180 void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode,
181                                   uint32_t cmd, int cmd_bit_len,
182                                   uint32_t addr, int addr_bit_len,
183                                   int dummy_bits,
184                                   uint8_t* mosi_data, int mosi_bit_len,
185                                   uint8_t* miso_data, int miso_bit_len,
186                                   uint32_t cs_mask,
187                                   bool is_write_erase_operation);
188 
189 /**
190  * @brief send reset command to opi flash
191  * @param spi_num spi port
192  * @param mode Flash Operation Mode
193  */
194 void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode);
195 
196 /**
197  * @brief to read opi flash ID(for MX25UM25645G)
198  * @param spi_num spi port
199  * @param mode Flash Operation Mode
200  * @return opi flash id
201  */
202 uint32_t esp_rom_opiflash_read_id(int spi_num, esp_rom_spiflash_read_mode_t mode);
203 
204 /**
205  * @brief to read opi flash status register(for MX25UM25645G)
206  * @param spi_num spi port
207  * @param mode Flash Operation Mode
208  * @return opi flash status value
209  */
210 uint8_t esp_rom_opiflash_rdsr(int spi_num, esp_rom_spiflash_read_mode_t mode);
211 
212 /**
213  * @brief wait opi flash status register to be idle
214  * @param spi_num spi port
215  * @param mode Flash Operation Mode
216  */
217 void esp_rom_opiflash_wait_idle(int spi_num, esp_rom_spiflash_read_mode_t mode);
218 
219 /**
220  * @brief to read the config register2(for MX25UM25645G)
221  * @param spi_num spi port
222  * @param mode Flash Operation Mode
223  * @param addr the address of configure register
224  * @return value of config register2
225  */
226 uint8_t esp_rom_opiflash_rdcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr);
227 
228 /**
229  * @brief to write the config register2(for MX25UM25645G)
230  * @param spi_num spi port
231  * @param mode Flash Operation Mode
232  * @param addr the address of config register
233  * @param val the value to write
234  */
235 void esp_rom_opiflash_wrcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr, uint8_t val);
236 
237 /**
238  * @brief to erase flash sector(for MX25UM25645G)
239  * @param spi_num spi port
240  * @param address the sector address to be erased
241  * @param mode Flash operation mode
242  * @return flash operation result
243  */
244 esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode);
245 
246 /**
247  * @brief to erase flash block(for MX25UM25645G)
248  * @param spi_num spi port
249  * @param address the block address to be erased
250  * @param mode Flash operation mode
251  * @return flash operation result
252  */
253 esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode);
254 
255 /**
256  * @brief to erase a flash area define by start address and length(for MX25UM25645G)
257  * @param spi_num spi port
258  * @param start_addr the start address to be erased
259  * @param area_len the erea length to be erased
260  * @param mode flash operation mode
261  * @return flash operation result
262  */
263 esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(int spi_num, uint32_t start_addr, uint32_t area_len, esp_rom_spiflash_read_mode_t mode);
264 
265 /**
266  * @brief to read data from opi flash(for MX25UM25645G)
267  * @param spi_num spi port
268  * @param mode flash operation mode
269  * @param flash_addr flash address to read data from
270  * @param data_addr data buffer to accept the data
271  * @param len data length to be read
272  * @return flash operation result
273  */
274 esp_rom_spiflash_result_t esp_rom_opiflash_read(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, int len);
275 
276 /**
277  * @brief to write data to opi flash(for MX25UM25645G)
278  * @param spi_num spi port
279  * @param mode flash operation mode
280  * @param flash_addr flash address to write data to
281  * @param data_addr data buffer to write to flash
282  * @param len data length to write
283  * @return flash operation result
284  */
285 esp_rom_spiflash_result_t esp_rom_opiflash_write(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, uint32_t len);
286 
287 /**
288  * @brief to set opi flash operation mode(for MX25UM25645G)
289  * @param spi_num spi port
290  * @param cur_mode current operation mode
291  * @param target the target operation mode to be set
292  */
293 void esp_rom_opiflash_set_mode(int spi_num, esp_rom_spiflash_read_mode_t cur_mode, esp_rom_spiflash_read_mode_t target_mode);
294 #endif
295 
296 #ifdef __cplusplus
297 }
298 #endif
299 
300 #endif
301