1 // Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef _ROM_RTC_H_ 16 #define _ROM_RTC_H_ 17 18 #include "ets_sys.h" 19 20 #include <stdbool.h> 21 #include <stdint.h> 22 23 #include "soc/soc.h" 24 #include "soc/rtc_cntl_reg.h" 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 /** \defgroup rtc_apis, rtc registers and memory related apis 31 * @brief rtc apis 32 */ 33 34 /** @addtogroup rtc_apis 35 * @{ 36 */ 37 38 /************************************************************************************** 39 * Note: * 40 * Some Rtc memory and registers are used, in ROM or in internal library. * 41 * Please do not use reserved or used rtc memory or registers. * 42 * * 43 ************************************************************************************* 44 * RTC Memory & Store Register usage 45 ************************************************************************************* 46 * rtc memory addr type size usage 47 * 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry 48 * 0x3f421000+SIZE_CP Slow 8192-SIZE_CP 49 * 50 * 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code 51 * 52 ************************************************************************************* 53 * RTC store registers usage 54 * RTC_CNTL_STORE0_REG Reserved 55 * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value 56 * RTC_CNTL_STORE2_REG Boot time, low word 57 * RTC_CNTL_STORE3_REG Boot time, high word 58 * RTC_CNTL_STORE4_REG External XTAL frequency 59 * RTC_CNTL_STORE5_REG APB bus frequency 60 * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY 61 * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC 62 ************************************************************************************* 63 */ 64 65 #define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG 66 #define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG 67 #define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG 68 #define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG 69 #define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG 70 #define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG 71 #define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG 72 #define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG 73 74 typedef enum { 75 AWAKE = 0, //<CPU ON 76 LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode. 77 DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up 78 } SLEEP_MODE; 79 80 typedef enum { 81 NO_MEAN = 0, 82 POWERON_RESET = 1, /**<1, Vbat power on reset*/ 83 RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/ 84 DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core*/ 85 TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/ 86 TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/ 87 RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/ 88 INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/ 89 TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/ 90 RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/ 91 RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/ 92 RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/ 93 RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/ 94 TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/ 95 SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/ 96 GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/ 97 } RESET_REASON; 98 99 typedef enum { 100 NO_SLEEP = 0, 101 EXT_EVENT0_TRIG = BIT0, 102 EXT_EVENT1_TRIG = BIT1, 103 GPIO_TRIG = BIT2, 104 TIMER_EXPIRE = BIT3, 105 SDIO_TRIG = BIT4, 106 MAC_TRIG = BIT5, 107 UART0_TRIG = BIT6, 108 UART1_TRIG = BIT7, 109 TOUCH_TRIG = BIT8, 110 SAR_TRIG = BIT9, 111 BT_TRIG = BIT10, 112 RISCV_TRIG = BIT11, 113 XTAL_DEAD_TRIG = BIT12, 114 RISCV_TRAP_TRIG = BIT13, 115 USB_TRIG = BIT14 116 } WAKEUP_REASON; 117 118 typedef enum { 119 DISEN_WAKEUP = NO_SLEEP, 120 EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG, 121 EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG, 122 GPIO_TRIG_EN = GPIO_TRIG, 123 TIMER_EXPIRE_EN = TIMER_EXPIRE, 124 SDIO_TRIG_EN = SDIO_TRIG, 125 MAC_TRIG_EN = MAC_TRIG, 126 UART0_TRIG_EN = UART0_TRIG, 127 UART1_TRIG_EN = UART1_TRIG, 128 TOUCH_TRIG_EN = TOUCH_TRIG, 129 SAR_TRIG_EN = SAR_TRIG, 130 BT_TRIG_EN = BT_TRIG, 131 RISCV_TRIG_EN = RISCV_TRIG, 132 XTAL_DEAD_TRIG_EN = XTAL_DEAD_TRIG, 133 RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG, 134 USB_TRIG_EN = USB_TRIG 135 } WAKEUP_ENABLE; 136 137 /** 138 * @brief Get the reset reason for CPU. 139 * 140 * @param int cpu_no : CPU no. 141 * 142 * @return RESET_REASON 143 */ 144 RESET_REASON rtc_get_reset_reason(int cpu_no); 145 146 /** 147 * @brief Get the wakeup cause for CPU. 148 * 149 * @param int cpu_no : CPU no. 150 * 151 * @return WAKEUP_REASON 152 */ 153 WAKEUP_REASON rtc_get_wakeup_cause(void); 154 155 /** 156 * @brief Get CRC for Fast RTC Memory. 157 * 158 * @param uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory. 159 * 160 * @param uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte. 161 * 162 * @return uint32_t : CRC32 result 163 */ 164 uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len); 165 166 /** 167 * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7. 168 * 169 * @param None 170 * 171 * @return None 172 */ 173 void set_rtc_memory_crc(void); 174 175 /** 176 * @brief Fetch entry from RTC memory and RTC STORE reg 177 * 178 * @param uint32_t * entry_addr : the address to save entry 179 * 180 * @param RESET_REASON reset_reason : reset reason this time 181 * 182 * @return None 183 */ 184 void rtc_boot_control(uint32_t * entry_addr, RESET_REASON reset_reason); 185 186 /** 187 * @brief Software Reset digital core. 188 * 189 * It is not recommended to use this function in esp-idf, use 190 * esp_restart() instead. 191 * 192 * @param None 193 * 194 * @return None 195 */ 196 void software_reset(void); 197 198 /** 199 * @brief Software Reset digital core. 200 * 201 * It is not recommended to use this function in esp-idf, use 202 * esp_restart() instead. 203 * 204 * @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU. 205 * 206 * @return None 207 */ 208 void software_reset_cpu(int cpu_no); 209 210 /** 211 * @} 212 */ 213 214 #ifdef __cplusplus 215 } 216 #endif 217 218 #endif /* _ROM_RTC_H_ */ 219
