1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <stdint.h>
16 #include "esp32c3/rom/ets_sys.h"
17 #include "soc/rtc.h"
18 #include "soc/rtc_cntl_reg.h"
19 #include "soc/timer_group_reg.h"
20 #include "esp_rom_sys.h"
21
22 /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
23 * This feature counts the number of XTAL clock cycles within a given number of
24 * RTC_SLOW_CLK cycles.
25 *
26 * Slow clock calibration feature has two modes of operation: one-off and cycling.
27 * In cycling mode (which is enabled by default on SoC reset), counting of XTAL
28 * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
29 * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
30 * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
31 * enabled using TIMG_RTC_CALI_START bit.
32 */
33
34 /**
35 * @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
36 * @param cal_clk which clock to calibrate
37 * @param slowclk_cycles number of slow clock cycles to count
38 * @return number of XTAL clock cycles within the given number of slow clock cycles
39 */
rtc_clk_cal_internal(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)40 uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
41 {
42 /* On ESP32S3, choosing RTC_CAL_RTC_MUX results in calibration of
43 * the 90k RTC clock regardless of the currenlty selected SLOW_CLK.
44 * On the ESP32, it used the currently selected SLOW_CLK.
45 * The following code emulates ESP32 behavior:
46 */
47 if (cal_clk == RTC_CAL_RTC_MUX) {
48 rtc_slow_freq_t slow_freq = rtc_clk_slow_freq_get();
49 if (slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
50 cal_clk = RTC_CAL_32K_XTAL;
51 } else if (slow_freq == RTC_SLOW_FREQ_8MD256) {
52 cal_clk = RTC_CAL_8MD256;
53 }
54 }
55 /* Enable requested clock (150k clock is always on) */
56 int dig_32k_xtal_state = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
57 if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_state) {
58 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
59 }
60
61 if (cal_clk == RTC_CAL_8MD256) {
62 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
63 }
64 /* Prepare calibration */
65 REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
66 /* There may be another calibration process already running during we call this function,
67 * so we should wait the last process is done.
68 */
69 if (!GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
70 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
71 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY));
72 }
73 }
74 CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
75 REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
76 /* Figure out how long to wait for calibration to finish */
77
78 /* Set timeout reg and expect time delay*/
79 uint32_t expected_freq;
80 if (cal_clk == RTC_CAL_32K_XTAL) {
81 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
82 expected_freq = RTC_SLOW_CLK_FREQ_32K;
83 } else if (cal_clk == RTC_CAL_8MD256) {
84 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles));
85 expected_freq = RTC_SLOW_CLK_FREQ_8MD256;
86 } else {
87 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles));
88 expected_freq = RTC_SLOW_CLK_FREQ_90K;
89 }
90 uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
91 /* Start calibration */
92 CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
93 SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
94
95 /* Wait for calibration to finish up to another us_time_estimate */
96 esp_rom_delay_us(us_time_estimate);
97 uint32_t cal_val;
98 while (true) {
99 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
100 cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
101 break;
102 }
103 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
104 cal_val = 0;
105 break;
106 }
107 }
108 CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
109
110 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, dig_32k_xtal_state);
111
112 if (cal_clk == RTC_CAL_8MD256) {
113 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
114 }
115
116 return cal_val;
117 }
118
rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)119 uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
120 {
121 uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
122 uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
123 uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
124 return ratio;
125 }
126
rtc_clk_cal(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)127 uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
128 {
129 rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
130 uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
131 uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
132 uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider;
133 uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
134 return period;
135 }
136
rtc_time_us_to_slowclk(uint64_t time_in_us,uint32_t period)137 uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
138 {
139 /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days.
140 * TODO: fix overflow.
141 */
142 return (time_in_us << RTC_CLK_CAL_FRACT) / period;
143 }
144
rtc_time_slowclk_to_us(uint64_t rtc_cycles,uint32_t period)145 uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
146 {
147 return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
148 }
149
rtc_time_get(void)150 uint64_t rtc_time_get(void)
151 {
152 SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
153 #if 0 // TODO ESP32-C3 IDF-2569: Re-enable it in the future
154 while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) {
155 esp_rom_delay_us(1); // might take 1 RTC slowclk period, don't flood RTC bus
156 }
157 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TIME_VALID_INT_CLR);
158 #endif
159 uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
160 t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
161 return t;
162 }
163
rtc_light_slp_time_get(void)164 uint64_t rtc_light_slp_time_get(void)
165 {
166 uint64_t t_wake = READ_PERI_REG(RTC_CNTL_TIME_LOW0_REG);
167 t_wake |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH0_REG)) << 32;
168 uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG);
169 t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32;
170 return (t_wake - t_slp);
171 }
172
rtc_deep_slp_time_get(void)173 uint64_t rtc_deep_slp_time_get(void)
174 {
175 uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG);
176 t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32;
177 uint64_t t_wake = rtc_time_get();
178 return (t_wake - t_slp);
179 }
180
rtc_clk_wait_for_slow_cycle(void)181 void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
182 {
183 SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE);
184 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) {
185 esp_rom_delay_us(1);
186 }
187 }
188
rtc_clk_freq_cal(uint32_t cal_val)189 uint32_t rtc_clk_freq_cal(uint32_t cal_val)
190 {
191 if (cal_val == 0) {
192 return 0; // cal_val will be denominator, return 0 as the symbol of failure.
193 }
194 return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
195 }
196
