1 // Copyright 2013-2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <string.h>
16 #include "sdkconfig.h"
17 #include "esp_system.h"
18 #include "esp_private/system_internal.h"
19 #include "esp_attr.h"
20 #include "esp_log.h"
21 #include "esp32s3/rom/cache.h"
22 #include "esp_rom_uart.h"
23 #include "soc/dport_reg.h"
24 #include "soc/gpio_reg.h"
25 #include "soc/rtc_cntl_reg.h"
26 #include "soc/timer_group_reg.h"
27 #include "soc/cpu.h"
28 #include "soc/rtc.h"
29 #include "soc/syscon_reg.h"
30 #include "hal/wdt_hal.h"
31 #include "freertos/xtensa_api.h"
32
33 /* "inner" restart function for after RTOS, interrupts & anything else on this
34 * core are already stopped. Stalls other core, resets hardware,
35 * triggers restart.
36 */
esp_restart_noos(void)37 void IRAM_ATTR esp_restart_noos(void)
38 {
39 // Disable interrupts
40 xt_ints_off(0xFFFFFFFF);
41
42 // Enable RTC watchdog for 1 second
43 wdt_hal_context_t rtc_wdt_ctx;
44 wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
45 uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
46 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
47 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
48 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
49 //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
50 wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
51 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
52
53 // Reset and stall the other CPU.
54 // CPU must be reset before stalling, in case it was running a s32c1i
55 // instruction. This would cause memory pool to be locked by arbiter
56 // to the stalled CPU, preventing current CPU from accessing this pool.
57 const uint32_t core_id = cpu_hal_get_core_id();
58 #if !CONFIG_FREERTOS_UNICORE
59 const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
60 esp_cpu_reset(other_core_id);
61 esp_cpu_stall(other_core_id);
62 #endif
63
64 // Disable TG0/TG1 watchdogs
65 wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
66 wdt_hal_write_protect_disable(&wdt0_context);
67 wdt_hal_disable(&wdt0_context);
68 wdt_hal_write_protect_enable(&wdt0_context);
69
70 wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
71 wdt_hal_write_protect_disable(&wdt1_context);
72 wdt_hal_disable(&wdt1_context);
73 wdt_hal_write_protect_enable(&wdt1_context);
74
75 // Flush any data left in UART FIFOs
76 esp_rom_uart_tx_wait_idle(0);
77 esp_rom_uart_tx_wait_idle(1);
78 // Disable cache
79 Cache_Disable_ICache();
80 Cache_Disable_DCache();
81
82 // 2nd stage bootloader reconfigures SPI flash signals.
83 // Reset them to the defaults expected by ROM.
84 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
85 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
86 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
87 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
88 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
89 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
90
91 // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
92 SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
93 SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST |
94 SYSTEM_BT_RST | SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST |
95 SYSTEM_SDIO_HOST_RST | SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST |
96 SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | SYSTEM_BLE_REG_RST | SYSTEM_PWR_REG_RST | SYSTEM_BB_REG_RST);
97 REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
98
99 // Reset timer/spi/uart
100 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
101 SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST);
102 REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
103
104 // Reset dma
105 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
106 REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
107
108 SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
109 CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
110
111 // Set CPU back to XTAL source, no PLL, same as hard reset
112 #if !CONFIG_IDF_ENV_FPGA
113 rtc_clk_cpu_freq_set_xtal();
114 #endif
115
116 #if !CONFIG_FREERTOS_UNICORE
117 // Clear entry point for APP CPU
118 REG_WRITE(SYSTEM_CORE_1_CONTROL_1_REG, 0);
119 #endif
120
121 // Reset CPUs
122 if (core_id == 0) {
123 // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
124 #if !CONFIG_FREERTOS_UNICORE
125 esp_cpu_reset(1);
126 #endif
127 esp_cpu_reset(0);
128 }
129 #if !CONFIG_FREERTOS_UNICORE
130 else {
131 // Running on APP CPU: need to reset PRO CPU and unstall it,
132 // then reset APP CPU
133 esp_cpu_reset(0);
134 esp_cpu_unstall(0);
135 esp_cpu_reset(1);
136 }
137 #endif
138 while (true) {
139 ;
140 }
141 }
142
esp_chip_info(esp_chip_info_t * out_info)143 void esp_chip_info(esp_chip_info_t *out_info)
144 {
145 memset(out_info, 0, sizeof(*out_info));
146 out_info->model = CHIP_ESP32S3;
147 out_info->cores = 2;
148 out_info->features = CHIP_FEATURE_WIFI_BGN;
149 }
150
