1 // Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at", 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License 14 15 #include "sdkconfig.h" 16 #include "esp_efuse.h" 17 #include <assert.h> 18 #include "esp_efuse_table.h" 19 20 // md5_digest_table f552d73ac112985991efa6734a60c8d9 21 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. 22 // If you want to change some fields, you need to change esp_efuse_table.csv file 23 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. 24 // To show efuse_table run the command 'show_efuse_table'. 25 26 #define MAX_BLK_LEN CONFIG_EFUSE_MAX_BLK_LEN 27 28 // The last free bit in the block is counted over the entire file. 29 #define LAST_FREE_BIT_BLK1 MAX_BLK_LEN 30 #define LAST_FREE_BIT_BLK2 MAX_BLK_LEN 31 #define LAST_FREE_BIT_BLK3 192 32 33 _Static_assert(LAST_FREE_BIT_BLK1 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files."); 34 _Static_assert(LAST_FREE_BIT_BLK2 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files."); 35 _Static_assert(LAST_FREE_BIT_BLK3 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files."); 36 37 static const esp_efuse_desc_t MAC_FACTORY[] = { 38 {EFUSE_BLK0, 72, 8}, // Factory MAC addr [0], 39 {EFUSE_BLK0, 64, 8}, // Factory MAC addr [1], 40 {EFUSE_BLK0, 56, 8}, // Factory MAC addr [2], 41 {EFUSE_BLK0, 48, 8}, // Factory MAC addr [3], 42 {EFUSE_BLK0, 40, 8}, // Factory MAC addr [4], 43 {EFUSE_BLK0, 32, 8}, // Factory MAC addr [5], 44 }; 45 46 static const esp_efuse_desc_t MAC_FACTORY_CRC[] = { 47 {EFUSE_BLK0, 80, 8}, // CRC8 for factory MAC address, 48 }; 49 50 static const esp_efuse_desc_t MAC_CUSTOM_CRC[] = { 51 {EFUSE_BLK3, 0, 8}, // CRC8 for custom MAC address., 52 }; 53 54 static const esp_efuse_desc_t MAC_CUSTOM[] = { 55 {EFUSE_BLK3, 8, 48}, // Custom MAC, 56 }; 57 58 static const esp_efuse_desc_t MAC_CUSTOM_VER[] = { 59 {EFUSE_BLK3, 184, 8}, // Custom MAC version, 60 }; 61 62 static const esp_efuse_desc_t SECURE_BOOT_KEY[] = { 63 {EFUSE_BLK2, 0, MAX_BLK_LEN}, // Security boot. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128), 64 }; 65 66 static const esp_efuse_desc_t ABS_DONE_0[] = { 67 {EFUSE_BLK0, 196, 1}, // Secure boot V1 is enabled for bootloader image. EFUSE_RD_ABS_DONE_0, 68 }; 69 70 static const esp_efuse_desc_t ABS_DONE_1[] = { 71 {EFUSE_BLK0, 197, 1}, // Secure boot V2 is enabled for bootloader image. EFUSE_RD_ABS_DONE_1, 72 }; 73 74 static const esp_efuse_desc_t ENCRYPT_FLASH_KEY[] = { 75 {EFUSE_BLK1, 0, MAX_BLK_LEN}, // Flash encrypt. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128), 76 }; 77 78 static const esp_efuse_desc_t ENCRYPT_CONFIG[] = { 79 {EFUSE_BLK0, 188, 4}, // Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M, 80 }; 81 82 static const esp_efuse_desc_t DISABLE_DL_ENCRYPT[] = { 83 {EFUSE_BLK0, 199, 1}, // Flash encrypt. Disable UART bootloader encryption. EFUSE_DISABLE_DL_ENCRYPT., 84 }; 85 86 static const esp_efuse_desc_t DISABLE_DL_DECRYPT[] = { 87 {EFUSE_BLK0, 200, 1}, // Flash encrypt. Disable UART bootloader decryption. EFUSE_DISABLE_DL_DECRYPT., 88 }; 89 90 static const esp_efuse_desc_t DISABLE_DL_CACHE[] = { 91 {EFUSE_BLK0, 201, 1}, // Flash encrypt. Disable UART bootloader MMU cache. EFUSE_DISABLE_DL_CACHE., 92 }; 93 94 static const esp_efuse_desc_t FLASH_CRYPT_CNT[] = { 95 {EFUSE_BLK0, 20, 7}, // Flash encrypt. Flash encryption is enabled if this field has an odd number of bits set. EFUSE_FLASH_CRYPT_CNT., 96 }; 97 98 static const esp_efuse_desc_t DISABLE_JTAG[] = { 99 {EFUSE_BLK0, 198, 1}, // Disable JTAG. EFUSE_RD_DISABLE_JTAG., 100 }; 101 102 static const esp_efuse_desc_t CONSOLE_DEBUG_DISABLE[] = { 103 {EFUSE_BLK0, 194, 1}, // Disable ROM BASIC interpreter fallback. EFUSE_RD_CONSOLE_DEBUG_DISABLE., 104 }; 105 106 static const esp_efuse_desc_t UART_DOWNLOAD_DIS[] = { 107 {EFUSE_BLK0, 27, 1}, // Disable UART download mode. Valid for ESP32 V3 and newer, 108 }; 109 110 static const esp_efuse_desc_t WR_DIS_EFUSE_RD_DISABLE[] = { 111 {EFUSE_BLK0, 0, 1}, // Write protection for EFUSE_RD_DISABLE, 112 }; 113 114 static const esp_efuse_desc_t WR_DIS_FLASH_CRYPT_CNT[] = { 115 {EFUSE_BLK0, 2, 1}, // Flash encrypt. Write protection FLASH_CRYPT_CNT, 116 }; 117 118 static const esp_efuse_desc_t WR_DIS_BLK1[] = { 119 {EFUSE_BLK0, 7, 1}, // Flash encrypt. Write protection encryption key. EFUSE_WR_DIS_BLK1, 120 }; 121 122 static const esp_efuse_desc_t WR_DIS_BLK2[] = { 123 {EFUSE_BLK0, 8, 1}, // Security boot. Write protection security key. EFUSE_WR_DIS_BLK2, 124 }; 125 126 static const esp_efuse_desc_t WR_DIS_BLK3[] = { 127 {EFUSE_BLK0, 9, 1}, // Write protection for EFUSE_BLK3. EFUSE_WR_DIS_BLK3, 128 }; 129 130 static const esp_efuse_desc_t RD_DIS_BLK1[] = { 131 {EFUSE_BLK0, 16, 1}, // Flash encrypt. efuse_key_read_protected. EFUSE_RD_DIS_BLK1, 132 }; 133 134 static const esp_efuse_desc_t RD_DIS_BLK2[] = { 135 {EFUSE_BLK0, 17, 1}, // Security boot. efuse_key_read_protected. EFUSE_RD_DIS_BLK2, 136 }; 137 138 static const esp_efuse_desc_t RD_DIS_BLK3[] = { 139 {EFUSE_BLK0, 18, 1}, // Read protection for EFUSE_BLK3. EFUSE_RD_DIS_BLK3, 140 }; 141 142 static const esp_efuse_desc_t CHIP_VER_DIS_APP_CPU[] = { 143 {EFUSE_BLK0, 96, 1}, // EFUSE_RD_CHIP_VER_DIS_APP_CPU, 144 }; 145 146 static const esp_efuse_desc_t CHIP_VER_DIS_BT[] = { 147 {EFUSE_BLK0, 97, 1}, // EFUSE_RD_CHIP_VER_DIS_BT, 148 }; 149 150 static const esp_efuse_desc_t CHIP_VER_PKG[] = { 151 {EFUSE_BLK0, 105, 3}, // EFUSE_RD_CHIP_VER_PKG least significant bits, 152 {EFUSE_BLK0, 98, 1}, // EFUSE_RD_CHIP_VER_PKG_4BIT most significant bit, 153 }; 154 155 static const esp_efuse_desc_t CHIP_CPU_FREQ_LOW[] = { 156 {EFUSE_BLK0, 108, 1}, // EFUSE_RD_CHIP_CPU_FREQ_LOW, 157 }; 158 159 static const esp_efuse_desc_t CHIP_CPU_FREQ_RATED[] = { 160 {EFUSE_BLK0, 109, 1}, // EFUSE_RD_CHIP_CPU_FREQ_RATED, 161 }; 162 163 static const esp_efuse_desc_t CHIP_VER_REV1[] = { 164 {EFUSE_BLK0, 111, 1}, // EFUSE_RD_CHIP_VER_REV1, 165 }; 166 167 static const esp_efuse_desc_t CHIP_VER_REV2[] = { 168 {EFUSE_BLK0, 180, 1}, // EFUSE_RD_CHIP_VER_REV2, 169 }; 170 171 static const esp_efuse_desc_t XPD_SDIO_REG[] = { 172 {EFUSE_BLK0, 142, 1}, // EFUSE_RD_XPD_SDIO_REG, 173 }; 174 175 static const esp_efuse_desc_t SDIO_TIEH[] = { 176 {EFUSE_BLK0, 143, 1}, // EFUSE_RD_SDIO_TIEH, 177 }; 178 179 static const esp_efuse_desc_t SDIO_FORCE[] = { 180 {EFUSE_BLK0, 144, 1}, // EFUSE_RD_SDIO_FORCE, 181 }; 182 183 static const esp_efuse_desc_t ADC_VREF_AND_SDIO_DREF[] = { 184 {EFUSE_BLK0, 136, 6}, // EFUSE_RD_ADC_VREF[0..4] or ( SDIO_DREFH[0 1], 185 }; 186 187 static const esp_efuse_desc_t ADC1_TP_LOW[] = { 188 {EFUSE_BLK3, 96, 7}, // TP_REG EFUSE_RD_ADC1_TP_LOW, 189 }; 190 191 static const esp_efuse_desc_t ADC2_TP_LOW[] = { 192 {EFUSE_BLK3, 112, 7}, // TP_REG EFUSE_RD_ADC2_TP_LOW, 193 }; 194 195 static const esp_efuse_desc_t ADC1_TP_HIGH[] = { 196 {EFUSE_BLK3, 103, 9}, // TP_REG EFUSE_RD_ADC1_TP_HIGH, 197 }; 198 199 static const esp_efuse_desc_t ADC2_TP_HIGH[] = { 200 {EFUSE_BLK3, 119, 9}, // TP_REG EFUSE_RD_ADC2_TP_HIGH, 201 }; 202 203 static const esp_efuse_desc_t SECURE_VERSION[] = { 204 {EFUSE_BLK3, 128, 32}, // Secure version for anti-rollback, 205 }; 206 207 208 209 210 211 const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { 212 &MAC_FACTORY[0], // Factory MAC addr [0] 213 &MAC_FACTORY[1], // Factory MAC addr [1] 214 &MAC_FACTORY[2], // Factory MAC addr [2] 215 &MAC_FACTORY[3], // Factory MAC addr [3] 216 &MAC_FACTORY[4], // Factory MAC addr [4] 217 &MAC_FACTORY[5], // Factory MAC addr [5] 218 NULL 219 }; 220 221 const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY_CRC[] = { 222 &MAC_FACTORY_CRC[0], // CRC8 for factory MAC address 223 NULL 224 }; 225 226 const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_CRC[] = { 227 &MAC_CUSTOM_CRC[0], // CRC8 for custom MAC address. 228 NULL 229 }; 230 231 const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM[] = { 232 &MAC_CUSTOM[0], // Custom MAC 233 NULL 234 }; 235 236 const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_VER[] = { 237 &MAC_CUSTOM_VER[0], // Custom MAC version 238 NULL 239 }; 240 241 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY[] = { 242 &SECURE_BOOT_KEY[0], // Security boot. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128) 243 NULL 244 }; 245 246 const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_0[] = { 247 &ABS_DONE_0[0], // Secure boot V1 is enabled for bootloader image. EFUSE_RD_ABS_DONE_0 248 NULL 249 }; 250 251 const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_1[] = { 252 &ABS_DONE_1[0], // Secure boot V2 is enabled for bootloader image. EFUSE_RD_ABS_DONE_1 253 NULL 254 }; 255 256 const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_FLASH_KEY[] = { 257 &ENCRYPT_FLASH_KEY[0], // Flash encrypt. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128) 258 NULL 259 }; 260 261 const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_CONFIG[] = { 262 &ENCRYPT_CONFIG[0], // Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M 263 NULL 264 }; 265 266 const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_ENCRYPT[] = { 267 &DISABLE_DL_ENCRYPT[0], // Flash encrypt. Disable UART bootloader encryption. EFUSE_DISABLE_DL_ENCRYPT. 268 NULL 269 }; 270 271 const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_DECRYPT[] = { 272 &DISABLE_DL_DECRYPT[0], // Flash encrypt. Disable UART bootloader decryption. EFUSE_DISABLE_DL_DECRYPT. 273 NULL 274 }; 275 276 const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_CACHE[] = { 277 &DISABLE_DL_CACHE[0], // Flash encrypt. Disable UART bootloader MMU cache. EFUSE_DISABLE_DL_CACHE. 278 NULL 279 }; 280 281 const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CNT[] = { 282 &FLASH_CRYPT_CNT[0], // Flash encrypt. Flash encryption is enabled if this field has an odd number of bits set. EFUSE_FLASH_CRYPT_CNT. 283 NULL 284 }; 285 286 const esp_efuse_desc_t* ESP_EFUSE_DISABLE_JTAG[] = { 287 &DISABLE_JTAG[0], // Disable JTAG. EFUSE_RD_DISABLE_JTAG. 288 NULL 289 }; 290 291 const esp_efuse_desc_t* ESP_EFUSE_CONSOLE_DEBUG_DISABLE[] = { 292 &CONSOLE_DEBUG_DISABLE[0], // Disable ROM BASIC interpreter fallback. EFUSE_RD_CONSOLE_DEBUG_DISABLE. 293 NULL 294 }; 295 296 const esp_efuse_desc_t* ESP_EFUSE_UART_DOWNLOAD_DIS[] = { 297 &UART_DOWNLOAD_DIS[0], // Disable UART download mode. Valid for ESP32 V3 and newer 298 NULL 299 }; 300 301 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_EFUSE_RD_DISABLE[] = { 302 &WR_DIS_EFUSE_RD_DISABLE[0], // Write protection for EFUSE_RD_DISABLE 303 NULL 304 }; 305 306 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT[] = { 307 &WR_DIS_FLASH_CRYPT_CNT[0], // Flash encrypt. Write protection FLASH_CRYPT_CNT 308 NULL 309 }; 310 311 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { 312 &WR_DIS_BLK1[0], // Flash encrypt. Write protection encryption key. EFUSE_WR_DIS_BLK1 313 NULL 314 }; 315 316 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK2[] = { 317 &WR_DIS_BLK2[0], // Security boot. Write protection security key. EFUSE_WR_DIS_BLK2 318 NULL 319 }; 320 321 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK3[] = { 322 &WR_DIS_BLK3[0], // Write protection for EFUSE_BLK3. EFUSE_WR_DIS_BLK3 323 NULL 324 }; 325 326 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK1[] = { 327 &RD_DIS_BLK1[0], // Flash encrypt. efuse_key_read_protected. EFUSE_RD_DIS_BLK1 328 NULL 329 }; 330 331 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK2[] = { 332 &RD_DIS_BLK2[0], // Security boot. efuse_key_read_protected. EFUSE_RD_DIS_BLK2 333 NULL 334 }; 335 336 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK3[] = { 337 &RD_DIS_BLK3[0], // Read protection for EFUSE_BLK3. EFUSE_RD_DIS_BLK3 338 NULL 339 }; 340 341 const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_APP_CPU[] = { 342 &CHIP_VER_DIS_APP_CPU[0], // EFUSE_RD_CHIP_VER_DIS_APP_CPU 343 NULL 344 }; 345 346 const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_BT[] = { 347 &CHIP_VER_DIS_BT[0], // EFUSE_RD_CHIP_VER_DIS_BT 348 NULL 349 }; 350 351 const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_PKG[] = { 352 &CHIP_VER_PKG[0], // EFUSE_RD_CHIP_VER_PKG least significant bits 353 &CHIP_VER_PKG[1], // EFUSE_RD_CHIP_VER_PKG_4BIT most significant bit 354 NULL 355 }; 356 357 const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_LOW[] = { 358 &CHIP_CPU_FREQ_LOW[0], // EFUSE_RD_CHIP_CPU_FREQ_LOW 359 NULL 360 }; 361 362 const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_RATED[] = { 363 &CHIP_CPU_FREQ_RATED[0], // EFUSE_RD_CHIP_CPU_FREQ_RATED 364 NULL 365 }; 366 367 const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[] = { 368 &CHIP_VER_REV1[0], // EFUSE_RD_CHIP_VER_REV1 369 NULL 370 }; 371 372 const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[] = { 373 &CHIP_VER_REV2[0], // EFUSE_RD_CHIP_VER_REV2 374 NULL 375 }; 376 377 const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[] = { 378 &XPD_SDIO_REG[0], // EFUSE_RD_XPD_SDIO_REG 379 NULL 380 }; 381 382 const esp_efuse_desc_t* ESP_EFUSE_SDIO_TIEH[] = { 383 &SDIO_TIEH[0], // EFUSE_RD_SDIO_TIEH 384 NULL 385 }; 386 387 const esp_efuse_desc_t* ESP_EFUSE_SDIO_FORCE[] = { 388 &SDIO_FORCE[0], // EFUSE_RD_SDIO_FORCE 389 NULL 390 }; 391 392 const esp_efuse_desc_t* ESP_EFUSE_ADC_VREF_AND_SDIO_DREF[] = { 393 &ADC_VREF_AND_SDIO_DREF[0], // EFUSE_RD_ADC_VREF[0..4] or ( SDIO_DREFH[0 1] 394 NULL 395 }; 396 397 const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_LOW[] = { 398 &ADC1_TP_LOW[0], // TP_REG EFUSE_RD_ADC1_TP_LOW 399 NULL 400 }; 401 402 const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_LOW[] = { 403 &ADC2_TP_LOW[0], // TP_REG EFUSE_RD_ADC2_TP_LOW 404 NULL 405 }; 406 407 const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_HIGH[] = { 408 &ADC1_TP_HIGH[0], // TP_REG EFUSE_RD_ADC1_TP_HIGH 409 NULL 410 }; 411 412 const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_HIGH[] = { 413 &ADC2_TP_HIGH[0], // TP_REG EFUSE_RD_ADC2_TP_HIGH 414 NULL 415 }; 416 417 const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { 418 &SECURE_VERSION[0], // Secure version for anti-rollback 419 NULL 420 }; 421
