1 // Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 /*
16 Tests for the adc device driver on ESP32-S2 only
17 */
18 #include "sdkconfig.h"
19 #if CONFIG_IDF_TARGET_ESP32S2
20
21
22 #include "esp_system.h"
23 #include "esp_intr_alloc.h"
24 #include "freertos/FreeRTOS.h"
25 #include "freertos/task.h"
26 #include "freertos/queue.h"
27 #include "driver/adc.h"
28 #include "driver/rtc_io.h"
29 #include "driver/gpio.h"
30 #include "unity.h"
31 #include "esp_system.h"
32 #include "esp_event.h"
33 #include "esp_wifi.h"
34 #include "esp_log.h"
35 #include "nvs_flash.h"
36 #include "test_utils.h"
37 #include "soc/adc_periph.h"
38 #include "test/test_common_adc.h"
39 #include "esp_rom_sys.h"
40 #include "driver/dac.h"
41
42 #include "soc/system_reg.h"
43 #include "soc/spi_reg.h"
44 #include "soc/soc.h"
45 #include "soc/lldesc.h"
46 #include "test/test_adc_dac_dma.h"
47
48 static const char *TAG = "test_adc";
49
50 #define PLATFORM_SELECT (1) //0: pxp; 1: chip
51 #if (PLATFORM_SELECT == 0) //PXP platform
52 #include "soc/apb_ctrl_reg.h"
53 #define SET_BREAK_POINT(flag) REG_WRITE(APB_CTRL_DATE_REG, flag)
54 //PXP clk is slower.
55 #define SYS_DELAY_TIME_MOM (1/40)
56 #define RTC_SLOW_CLK_FLAG 1 // Slow clock is 32KHz.
test_pxp_deinit_io(void)57 static void test_pxp_deinit_io(void)
58 {
59 for (int i = 0; i < 22; i++) {
60 rtc_gpio_init(i);
61 }
62 }
63 #else
64 //PXP clk is slower.
65 #define SET_BREAK_POINT(flag)
66 #define SYS_DELAY_TIME_MOM (1)
67 #define RTC_SLOW_CLK_FLAG 0 // Slow clock is 32KHz.
68 #endif
69
70 #define ADC_REG_BASE_TEST() ({ \
71 TEST_ASSERT_EQUAL_UINT32(REG_GET_FIELD(APB_SARADC_APB_CTRL_DATE_REG, APB_SARADC_APB_CTRL_DATE), APB_SARADC.apb_ctrl_date); \
72 TEST_ASSERT_EQUAL_UINT32(REG_GET_FIELD(SENS_SARDATE_REG, SENS_SAR_DATE), SENS.sardate.sar_date); \
73 TEST_ASSERT_EQUAL_UINT32(REG_GET_FIELD(RTC_IO_DATE_REG, RTC_IO_IO_DATE), RTCIO.date.date); \
74 })
75 /** Sample rate = APB_CLK(80 MHz) / (CLK_DIV + 1) / TRIGGER_INTERVAL / 2. */
76 #define TEST_ADC_TRIGGER_INTERVAL_DEFAULT (40)
77 #define TEST_ADC_DIGI_CLK_DIV_DEFAULT (9)
78 static uint8_t adc_test_num = 9;
79 static adc_channel_t adc_list[SOC_ADC_PATT_LEN_MAX] = {
80 ADC_CHANNEL_0,
81 ADC_CHANNEL_1,
82 ADC_CHANNEL_2,
83 ADC_CHANNEL_3,
84 ADC_CHANNEL_4,
85 ADC_CHANNEL_5,
86 ADC_CHANNEL_6,
87 // ADC_CHANNEL_7, // Workaround: IO18 is pullup outside in ESP32S2-Saola Runner.
88 ADC_CHANNEL_8,
89 ADC_CHANNEL_9,
90 };
91 /* For ESP32S2, it should use same atten, or, it will have error. */
92 #define TEST_ADC_ATTEN_DEFAULT (ADC_ATTEN_11db)
93
94 extern esp_err_t adc_digi_reset(void);
95
96 /* Work mode.
97 * single: eof_num;
98 * double: SAR_EOF_NUMBER/2;
99 * alter: eof_num;
100 * */
101 #define SAR_SIMPLE_NUM 512 // Set sample number of enabled unit.
102 /* Use two DMA linker to save ADC data. ADC sample 1 times -> 2 byte data -> 2 DMA link buf. */
103 #define SAR_DMA_DATA_SIZE(unit, sample_num) (SAR_EOF_NUMBER(unit, sample_num))
104 #define SAR_EOF_NUMBER(unit, sample_num) ((sample_num) * (unit))
105 #define SAR_MEAS_LIMIT_NUM(unit, sample_num) (SAR_SIMPLE_NUM)
106 #define SAR_SIMPLE_TIMEOUT_MS 1000
107
108 typedef struct dma_msg {
109 uint32_t int_msk;
110 uint8_t *data;
111 uint32_t data_len;
112 } adc_dma_event_t;
113
114 static uint8_t link_buf[2][SAR_DMA_DATA_SIZE(2, SAR_SIMPLE_NUM)] = {0};
115 static lldesc_t dma1 = {0};
116 static lldesc_t dma2 = {0};
117 static QueueHandle_t que_adc = NULL;
118 static adc_dma_event_t adc_evt;
119
120 /** ADC-DMA ISR handler. */
adc_dma_isr(void * arg)121 static IRAM_ATTR void adc_dma_isr(void *arg)
122 {
123 uint32_t int_st = REG_READ(SPI_DMA_INT_ST_REG(3));
124 int task_awoken = pdFALSE;
125 REG_WRITE(SPI_DMA_INT_CLR_REG(3), int_st);
126 if (int_st & SPI_IN_SUC_EOF_INT_ST_M) {
127 adc_evt.int_msk = int_st;
128 xQueueSendFromISR(que_adc, &adc_evt, &task_awoken);
129 }
130 if (int_st & SPI_IN_DONE_INT_ST) {
131 adc_evt.int_msk = int_st;
132 xQueueSendFromISR(que_adc, &adc_evt, &task_awoken);
133 }
134 ESP_EARLY_LOGV(TAG, "int msk%x\n", int_st);
135 if (task_awoken == pdTRUE) {
136 portYIELD_FROM_ISR();
137 }
138 }
139
140 /**
141 * DMA liner initialization and start.
142 * @param is_loop
143 * - true: The two dma linked lists are connected end to end, with no end mark (eof).
144 * - false: The two dma linked lists are connected end to end, with end mark (eof).
145 */
adc_dma_linker_init(adc_unit_t adc,bool is_loop)146 static uint32_t adc_dma_linker_init(adc_unit_t adc, bool is_loop)
147 {
148 dma1 = (lldesc_t) {
149 .size = SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM),
150 .owner = 1,
151 .buf = &link_buf[0][0],
152 .qe.stqe_next = &dma2,
153 };
154 dma2 = (lldesc_t) {
155 .size = SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM),
156 .owner = 1,
157 .buf = &link_buf[1][0],
158 };
159 if (is_loop) {
160 dma2.qe.stqe_next = &dma1;
161 } else {
162 dma2.qe.stqe_next = NULL;
163 }
164 return (uint32_t)&dma1;
165 }
166
167 #define DEBUG_CHECK_ENABLE 1
168 #define DEBUG_PRINT_ENABLE 1
169 #define DEBUG_CHECK_ERROR 10
170
171 /**
172 * Check the ADC-DMA data in linker buffer by input level.
173 * ideal_level
174 * - -1: Don't check data.
175 * - 0: ADC channel voltage is 0v.
176 * - 1: ADC channel voltage is 3.3v.
177 * - 2: ADC channel voltage is 1.4v.
178 */
adc_dma_data_check(adc_unit_t adc,int ideal_level)179 static esp_err_t adc_dma_data_check(adc_unit_t adc, int ideal_level)
180 {
181 int unit_old = 1;
182 int ch_cnt = 0;
183 for (int cnt = 0; cnt < 2; cnt++) {
184 esp_rom_printf("\n[%s] link_buf[%d]: \n", __func__, cnt % 2);
185 for (int i = 0; i < SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM); i += 2) {
186 uint8_t h = link_buf[cnt % 2][i + 1], l = link_buf[cnt % 2][i];
187 uint16_t temp = (h << 8 | l);
188 adc_digi_output_data_t *data = (adc_digi_output_data_t *)&temp;
189
190 if (adc > ADC_UNIT_2) { //ADC_ENCODE_11BIT
191 #if DEBUG_PRINT_ENABLE
192 if (i % 16 == 0) {
193 esp_rom_printf("\n");
194 }
195 esp_rom_printf("[%d_%d_%04x] ", data->type2.unit, data->type2.channel, data->type2.data);
196 #endif
197 #if DEBUG_CHECK_ENABLE
198 if (ideal_level >= 0) {
199 TEST_ASSERT_NOT_EQUAL(unit_old, data->type2.unit);
200 unit_old = data->type2.unit;
201 if (data->type2.channel > ADC_CHANNEL_MAX) {
202 printf("Data invalid [%d]\n", data->type2.channel);
203 continue;
204 }
205 int cur_ch = ((ch_cnt++ / 2) % adc_test_num);
206 TEST_ASSERT_EQUAL( data->type2.channel, adc_list[cur_ch] );
207 }
208 if (ideal_level == 1) { // high level 3.3v
209 TEST_ASSERT_EQUAL( 0x7FF, data->type2.data );
210 } else if (ideal_level == 0) { // low level 0v
211 TEST_ASSERT_LESS_THAN( 10, data->type2.data );
212 } else if (ideal_level == 2) { // middle level 1.4v
213 TEST_ASSERT_INT_WITHIN( 128, 1100, data->type2.data );
214 } else if (ideal_level == 3) { // normal level
215 } else { // no check
216 }
217 #endif
218 } else { //ADC_ENCODE_12BIT
219 #if DEBUG_PRINT_ENABLE
220 if (i % 16 == 0) {
221 esp_rom_printf("\n");
222 }
223 esp_rom_printf("[%d_%04x] ", data->type1.channel, data->type1.data);
224 #endif
225 #if DEBUG_CHECK_ENABLE
226 if (ideal_level >= 0) {
227 int cur_ch = ((ch_cnt++) % adc_test_num);
228 TEST_ASSERT_EQUAL( adc_list[cur_ch], data->type1.channel );
229 }
230 if (ideal_level == 1) { // high level 3.3v
231 TEST_ASSERT_EQUAL( 0XFFF, data->type1.data );
232 } else if (ideal_level == 0) { // low level 0v
233 TEST_ASSERT_LESS_THAN( 10, data->type1.data );
234 } else if (ideal_level == 2) { // middle level 1.4v
235 TEST_ASSERT_INT_WITHIN( 256, 2200, data->type1.data );
236 } else if (ideal_level == 3) { // normal level
237 } else { // no check
238 }
239 #endif
240 }
241 link_buf[cnt % 2][i] = 0;
242 link_buf[cnt % 2][i + 1] = 0;
243 }
244 esp_rom_printf("\n");
245 }
246 return ESP_OK;
247 }
248
adc_dma_data_multi_st_check(adc_unit_t adc,void * dma_addr,uint32_t int_mask)249 static esp_err_t adc_dma_data_multi_st_check(adc_unit_t adc, void *dma_addr, uint32_t int_mask)
250 {
251 adc_dma_event_t evt;
252
253 ESP_LOGI(TAG, "adc IO normal, test ...");
254 for (int i = 0; i < adc_test_num; i++) {
255 adc_io_normal(adc, adc_list[i]);
256 }
257 TEST_ESP_OK( adc_digi_start() );
258 while (1) {
259 TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, SAR_SIMPLE_TIMEOUT_MS / portTICK_RATE_MS), pdTRUE );
260 if (evt.int_msk & SPI_IN_SUC_EOF_INT_ENA) {
261 break;
262 }
263 }
264 TEST_ESP_OK( adc_digi_stop() );
265 adc_dac_dma_linker_start(DMA_ONLY_ADC_INLINK, (void *)dma_addr, int_mask);
266 adc_digi_reset();
267 TEST_ESP_OK( adc_dma_data_check(adc, -1) ); // Don't check data.
268
269 ESP_LOGI(TAG, "adc IO fake tie high, test ...");
270 for (int i = 0; i < adc_test_num; i++) {
271 adc_fake_tie_high(adc, adc_list[i]);
272 }
273 TEST_ESP_OK( adc_digi_start() );
274 while (1) {
275 TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, SAR_SIMPLE_TIMEOUT_MS / portTICK_RATE_MS), pdTRUE );
276 if (evt.int_msk & SPI_IN_SUC_EOF_INT_ENA) {
277 break;
278 }
279 }
280 TEST_ESP_OK( adc_digi_stop() );
281 adc_dac_dma_linker_start(DMA_ONLY_ADC_INLINK, (void *)dma_addr, int_mask);
282 adc_digi_reset();
283 TEST_ESP_OK( adc_dma_data_check(adc, 1) );
284
285 ESP_LOGI(TAG, "adc IO fake tie low, test ...");
286 for (int i = 0; i < adc_test_num; i++) {
287 adc_fake_tie_low(adc, adc_list[i]);
288 }
289 TEST_ESP_OK( adc_digi_start() );
290 while (1) {
291 TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, SAR_SIMPLE_TIMEOUT_MS / portTICK_RATE_MS), pdTRUE );
292 if (evt.int_msk & SPI_IN_SUC_EOF_INT_ENA) {
293 break;
294 }
295 }
296 TEST_ESP_OK( adc_digi_stop() );
297 adc_dac_dma_linker_start(DMA_ONLY_ADC_INLINK, (void *)dma_addr, int_mask);
298 adc_digi_reset();
299 TEST_ESP_OK( adc_dma_data_check(adc, 0) );
300
301 ESP_LOGI(TAG, "adc IO fake tie middle, test ...");
302 for (int i = 0; i < adc_test_num; i++) {
303 adc_fake_tie_middle(adc, adc_list[i]);
304 }
305 TEST_ESP_OK( adc_digi_start() );
306 while (1) {
307 TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, SAR_SIMPLE_TIMEOUT_MS / portTICK_RATE_MS), pdTRUE );
308 if (evt.int_msk & SPI_IN_SUC_EOF_INT_ENA) {
309 break;
310 }
311 }
312 TEST_ESP_OK( adc_digi_stop() );
313 adc_dac_dma_linker_start(DMA_ONLY_ADC_INLINK, (void *)dma_addr, int_mask);
314 adc_digi_reset();
315 TEST_ESP_OK( adc_dma_data_check(adc, 2) );
316
317 return ESP_OK;
318 }
319
320 #include "soc/apb_saradc_struct.h"
321 /**
322 * Test the partten table setting. It's easy wrong.
323 *
324 * @param adc_n ADC unit.
325 * @param in_partten_len The length of partten be set.
326 * @param in_last_ch The channel number of the last message.
327 */
adc_check_patt_table(adc_unit_t adc,uint32_t in_partten_len,adc_channel_t in_last_ch)328 static esp_err_t adc_check_patt_table(adc_unit_t adc, uint32_t in_partten_len, adc_channel_t in_last_ch)
329 {
330 esp_err_t ret = ESP_FAIL;
331 uint8_t index = (in_partten_len - 1) / 4;
332 uint8_t offset = 24 - ((in_partten_len - 1) % 4) * 8;
333 uint32_t temp = 0, len;
334
335 if (adc & ADC_UNIT_1) {
336 len = APB_SARADC.ctrl.sar1_patt_len + 1;
337 temp = APB_SARADC.sar1_patt_tab[index];
338 printf("patt1 len %d\n", len);
339 printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[0]);
340 printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[1]);
341 printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[2]);
342 printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[3]);
343 if (in_partten_len == len) {
344 if (in_last_ch == (((temp >> (offset + 4))) & 0xf)) {
345 ret = ESP_OK;
346 }
347 }
348 }
349 if (adc & ADC_UNIT_2) {
350 len = APB_SARADC.ctrl.sar2_patt_len + 1;
351 temp = APB_SARADC.sar2_patt_tab[index];
352 printf("patt2 len %d\n", len);
353 printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[0]);
354 printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[1]);
355 printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[2]);
356 printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[3]);
357 if (in_partten_len == len) {
358 if (in_last_ch == (((temp >> (offset + 4))) & 0xf)) {
359 ret = ESP_OK;
360 }
361 }
362 }
363 return ret;
364 }
365
366 /**
367 * Testcase: Check the base function of ADC-DMA. Include:
368 * - Various conversion modes.
369 * - Whether the channel and data are lost.
370 * - Whether the data is the same as the channel voltage.
371 */
test_adc_dig_dma_single_unit(adc_unit_t adc)372 int test_adc_dig_dma_single_unit(adc_unit_t adc)
373 {
374 ESP_LOGI(TAG, " >> %s << ", __func__);
375 ESP_LOGI(TAG, " >> adc unit: %x << ", adc);
376
377 TEST_ESP_OK( adc_digi_init() );
378 /* arbiter config */
379 adc_arbiter_t arb_cfg = {
380 .mode = ADC_ARB_MODE_FIX,
381 .dig_pri = 0,
382 .pwdet_pri = 2,
383 .rtc_pri = 1,
384 };
385 TEST_ESP_OK( adc_arbiter_config(ADC_UNIT_2, &arb_cfg) ); // If you want use force
386
387 adc_digi_config_t config = {
388 .conv_limit_en = false,
389 .conv_limit_num = 0,
390 .interval = TEST_ADC_TRIGGER_INTERVAL_DEFAULT,
391 .dig_clk.use_apll = 0, // APB clk
392 .dig_clk.div_num = TEST_ADC_DIGI_CLK_DIV_DEFAULT,
393 .dig_clk.div_b = 0,
394 .dig_clk.div_a = 0,
395 .dma_eof_num = SAR_EOF_NUMBER((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM),
396 };
397 /* Config pattern table */
398 adc_digi_pattern_table_t adc1_patt[SOC_ADC_PATT_LEN_MAX] = {0};
399 adc_digi_pattern_table_t adc2_patt[SOC_ADC_PATT_LEN_MAX] = {0};
400 if (adc & ADC_UNIT_1) {
401 config.adc1_pattern_len = adc_test_num;
402 config.adc1_pattern = adc1_patt;
403 for (int i = 0; i < adc_test_num; i++) {
404 adc1_patt[i].atten = TEST_ADC_ATTEN_DEFAULT;
405 adc1_patt[i].channel = adc_list[i];
406 adc_gpio_init(ADC_UNIT_1, adc_list[i]);
407 }
408 }
409 if (adc & ADC_UNIT_2) {
410 config.adc2_pattern_len = adc_test_num;
411 config.adc2_pattern = adc2_patt;
412 for (int i = 0; i < adc_test_num; i++) {
413 adc2_patt[i].atten = TEST_ADC_ATTEN_DEFAULT;
414 adc2_patt[i].channel = adc_list[i];
415 adc_gpio_init(ADC_UNIT_2, adc_list[i]);
416 }
417 }
418 if (adc == ADC_UNIT_1) {
419 config.conv_mode = ADC_CONV_SINGLE_UNIT_1;
420 config.format = ADC_DIGI_FORMAT_12BIT;
421 } else if (adc == ADC_UNIT_2) {
422 config.conv_mode = ADC_CONV_SINGLE_UNIT_2;
423 config.format = ADC_DIGI_FORMAT_12BIT;
424 } else if (adc == ADC_UNIT_BOTH) {
425 config.conv_mode = ADC_CONV_BOTH_UNIT;
426 config.format = ADC_DIGI_FORMAT_11BIT;
427 } else if (adc == ADC_UNIT_ALTER) {
428 config.conv_mode = ADC_CONV_ALTER_UNIT;
429 config.format = ADC_DIGI_FORMAT_11BIT;
430 }
431 TEST_ESP_OK( adc_digi_controller_config(&config) );
432
433 /* ADC-DMA linker init */
434 if (que_adc == NULL) {
435 que_adc = xQueueCreate(5, sizeof(adc_dma_event_t));
436 } else {
437 xQueueReset(que_adc);
438 }
439 uint32_t int_mask = SPI_IN_SUC_EOF_INT_ENA;
440 uint32_t dma_addr = adc_dma_linker_init(adc, false);
441 adc_dac_dma_isr_register(adc_dma_isr, NULL, int_mask);
442 adc_dac_dma_linker_start(DMA_ONLY_ADC_INLINK, (void *)dma_addr, int_mask);
443
444 TEST_ESP_OK( adc_check_patt_table(adc, adc_test_num, adc_list[adc_test_num - 1]) );
445 adc_dma_data_multi_st_check(adc, (void *)dma_addr, int_mask);
446
447 adc_dac_dma_linker_deinit();
448 adc_dac_dma_isr_deregister(adc_dma_isr, NULL);
449 TEST_ESP_OK( adc_digi_deinit() );
450 vTaskDelay(10 / portTICK_RATE_MS);
451
452 return 0;
453 }
454
455 TEST_CASE("ADC DMA single read", "[ADC]")
456 {
457 test_adc_dig_dma_single_unit(ADC_UNIT_BOTH);
458
459 test_adc_dig_dma_single_unit(ADC_UNIT_ALTER);
460
461 test_adc_dig_dma_single_unit(ADC_UNIT_1);
462
463 test_adc_dig_dma_single_unit(ADC_UNIT_2);
464 }
465
466 #include "touch_scope.h"
467 /**
468 * 0: ADC1 channels raw data debug.
469 * 1: ADC2 channels raw data debug.
470 * 2: ADC1 one channel raw data debug.
471 */
472 #define SCOPE_DEBUG_TYPE 0
473 #define SCOPE_DEBUG_CHANNEL_MAX (10)
474 #define SCOPE_DEBUG_ENABLE (0)
475 #define SCOPE_UART_BUADRATE (256000)
476 #define SCOPE_DEBUG_FREQ_MS (50)
477 #define SCOPE_OUTPUT_UART (0)
478 static float scope_temp[SCOPE_DEBUG_CHANNEL_MAX] = {0}; // max scope channel is 10.
479
test_adc_dig_scope_debug_unit(adc_unit_t adc)480 int test_adc_dig_scope_debug_unit(adc_unit_t adc)
481 {
482 ESP_LOGI(TAG, " >> %s << ", __func__);
483 ESP_LOGI(TAG, " >> adc unit: %x << ", adc);
484
485 TEST_ESP_OK( adc_digi_init() );
486 if (adc & ADC_UNIT_2) {
487 /* arbiter config */
488 adc_arbiter_t arb_cfg = {
489 .mode = ADC_ARB_MODE_FIX,
490 .dig_pri = 0,
491 .pwdet_pri = 2,
492 .rtc_pri = 1,
493 };
494 TEST_ESP_OK( adc_arbiter_config(ADC_UNIT_2, &arb_cfg) ); // If you want use force
495 }
496 adc_digi_config_t config = {
497 .conv_limit_en = false,
498 .conv_limit_num = 0,
499 .interval = TEST_ADC_TRIGGER_INTERVAL_DEFAULT,
500 .dig_clk.use_apll = 0, // APB clk
501 .dig_clk.div_num = TEST_ADC_DIGI_CLK_DIV_DEFAULT,
502 .dig_clk.div_a = 0,
503 .dig_clk.div_b = 0,
504 .dma_eof_num = SAR_EOF_NUMBER((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM),
505 };
506 /* Config pattern table */
507 adc_digi_pattern_table_t adc1_patt[SOC_ADC_PATT_LEN_MAX] = {0};
508 adc_digi_pattern_table_t adc2_patt[SOC_ADC_PATT_LEN_MAX] = {0};
509 if (adc & ADC_UNIT_1) {
510 config.adc1_pattern_len = adc_test_num;
511 config.adc1_pattern = adc1_patt;
512 for (int i = 0; i < adc_test_num; i++) {
513 adc1_patt[i].atten = TEST_ADC_ATTEN_DEFAULT;
514 adc1_patt[i].channel = adc_list[i];
515 adc_gpio_init(ADC_UNIT_1, adc_list[i]);
516 }
517 }
518 if (adc & ADC_UNIT_2) {
519 config.adc2_pattern_len = adc_test_num;
520 config.adc2_pattern = adc2_patt;
521 for (int i = 0; i < adc_test_num; i++) {
522 adc2_patt[i].atten = TEST_ADC_ATTEN_DEFAULT;
523 adc2_patt[i].channel = adc_list[i];
524 adc_gpio_init(ADC_UNIT_2, adc_list[i]);
525 }
526 }
527 if (adc == ADC_UNIT_1) {
528 config.conv_mode = ADC_CONV_SINGLE_UNIT_1;
529 config.format = ADC_DIGI_FORMAT_12BIT;
530 } else if (adc == ADC_UNIT_2) {
531 config.conv_mode = ADC_CONV_SINGLE_UNIT_2;
532 config.format = ADC_DIGI_FORMAT_12BIT;
533 } else if (adc == ADC_UNIT_BOTH) {
534 config.conv_mode = ADC_CONV_BOTH_UNIT;
535 config.format = ADC_DIGI_FORMAT_11BIT;
536 } else if (adc == ADC_UNIT_ALTER) {
537 config.conv_mode = ADC_CONV_ALTER_UNIT;
538 config.format = ADC_DIGI_FORMAT_11BIT;
539 }
540 TEST_ESP_OK( adc_digi_controller_config(&config) );
541
542 /* ADC-DMA linker init */
543 if (que_adc == NULL) {
544 que_adc = xQueueCreate(5, sizeof(adc_dma_event_t));
545 } else {
546 xQueueReset(que_adc);
547 }
548 uint32_t int_mask = SPI_IN_SUC_EOF_INT_ENA;
549 uint32_t dma_addr = adc_dma_linker_init(adc, false);
550 adc_dac_dma_isr_register(adc_dma_isr, NULL, int_mask);
551 adc_dac_dma_linker_start(DMA_ONLY_ADC_INLINK, (void *)dma_addr, int_mask);
552
553 ESP_LOGI(TAG, "adc IO fake tie middle, test ...");
554 for (int i = 0; i < adc_test_num; i++) {
555 adc_fake_tie_middle(adc, adc_list[i]);
556 }
557
558 return 0;
559 }
560
scope_output(int adc_num,int channel,int data)561 static void scope_output(int adc_num, int channel, int data)
562 {
563 /** can replace by uart log.*/
564 #if SCOPE_OUTPUT_UART
565 static int icnt = 0;
566 if (icnt++ % 8 == 0) {
567 esp_rom_printf("\n");
568 }
569 esp_rom_printf("[%d_%d_%04x] ", adc_num, channel, data);
570 return;
571 #endif
572 #if SCOPE_DEBUG_TYPE == 0
573 if (adc_num != 0) {
574 return;
575 }
576 #elif SCOPE_DEBUG_TYPE == 1
577 if (adc_num != 1) {
578 return;
579 }
580 #endif
581 int i;
582 /* adc Read */
583 for (i = 0; i < adc_test_num; i++) {
584 if (adc_list[i] == channel && scope_temp[i] == 0) {
585 scope_temp[i] = data;
586 break;
587 }
588 }
589 if (i == adc_test_num) {
590 test_tp_print_to_scope(scope_temp, adc_test_num);
591 vTaskDelay(SCOPE_DEBUG_FREQ_MS / portTICK_RATE_MS);
592 for (int i = 0; i < adc_test_num; i++) {
593 scope_temp[i] = 0;
594 }
595 }
596 }
597
598 /**
599 * Manual test: Capture ADC-DMA data and display it on the serial oscilloscope. Used to observe the stability of the data.
600 * Use step:
601 * 1. Run this test from the unit test app.
602 * 2. Use `ESP-Tuning Tool`(download from `www.espressif.com`) to capture.
603 * 3. The readings of multiple channels will be displayed on the tool.
604 */
605 TEST_CASE("test_adc_digi_slope_debug", "[adc_dma][ignore]")
606 {
607 adc_dma_event_t evt;
608 test_tp_scope_debug_init(0, -1, -1, SCOPE_UART_BUADRATE);
609 adc_unit_t adc = ADC_CONV_BOTH_UNIT;
610 test_adc_dig_scope_debug_unit(adc);
611 while (1) {
612 TEST_ESP_OK( adc_digi_start() );
613 TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, portMAX_DELAY), pdTRUE );
614 if (evt.int_msk & SPI_IN_SUC_EOF_INT_ST) {
615 TEST_ESP_OK( adc_digi_stop() );
616 adc_digi_reset();
617 for (int cnt = 0; cnt < 2; cnt++) {
618 esp_rom_printf("cnt%d\n", cnt);
619 for (int i = 0; i < SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM); i += 2) {
620 uint8_t h = link_buf[cnt % 2][i + 1], l = link_buf[cnt % 2][i];
621 uint16_t temp = (h << 8 | l);
622 adc_digi_output_data_t *data = (adc_digi_output_data_t *)&temp;
623 if (adc > ADC_UNIT_2) { //ADC_ENCODE_11BIT
624 scope_output(data->type2.unit, data->type2.channel, data->type2.data);
625 } else { //ADC_ENCODE_12BIT
626 if (adc == ADC_UNIT_1) {
627 scope_output(0, data->type1.channel, data->type1.data);
628 } else if (adc == ADC_UNIT_2) {
629 scope_output(1, data->type1.channel, data->type1.data);
630 }
631 }
632 link_buf[cnt % 2][i] = 0;
633 link_buf[cnt % 2][i + 1] = 0;
634 }
635 }
636 }
637 }
638 }
639
640 #endif // CONFIG_IDF_TARGET_ESP32S2
641
