1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #include <stdint.h>
15 #include "sdkconfig.h"
16 #include "esp_attr.h"
17 #include "esp_log.h"
18 #include "esp_image_format.h"
19 #include "flash_qio_mode.h"
20 #include "esp_rom_gpio.h"
21 #include "esp_rom_efuse.h"
22 #include "esp_rom_uart.h"
23 #include "esp_rom_sys.h"
24 #include "soc/efuse_reg.h"
25 #include "soc/gpio_sig_map.h"
26 #include "soc/io_mux_reg.h"
27 #include "soc/assist_debug_reg.h"
28 #include "soc/cpu.h"
29 #include "soc/rtc.h"
30 #include "soc/spi_periph.h"
31 #include "soc/extmem_reg.h"
32 #include "soc/io_mux_reg.h"
33 #include "soc/system_reg.h"
34 #include "esp32c3/rom/efuse.h"
35 #include "esp32c3/rom/spi_flash.h"
36 #include "esp32c3/rom/cache.h"
37 #include "esp32c3/rom/ets_sys.h"
38 #include "esp32c3/rom/spi_flash.h"
39 #include "esp32c3/rom/rtc.h"
40 #include "bootloader_common.h"
41 #include "bootloader_init.h"
42 #include "bootloader_clock.h"
43 #include "bootloader_flash_config.h"
44 #include "bootloader_mem.h"
45 #include "regi2c_ctrl.h"
46 #include "bootloader_console.h"
47 #include "bootloader_flash_priv.h"
48 
49 static const char *TAG = "boot.esp32c3";
50 
bootloader_configure_spi_pins(int drv)51 void IRAM_ATTR bootloader_configure_spi_pins(int drv)
52 {
53     const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
54     uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
55     uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
56     uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
57     uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
58     uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
59     uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
60     uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
61     if (spiconfig == 0) {
62 
63     } else {
64         clk_gpio_num = spiconfig         & 0x3f;
65         q_gpio_num = (spiconfig >> 6)    & 0x3f;
66         d_gpio_num = (spiconfig >> 12)   & 0x3f;
67         cs0_gpio_num = (spiconfig >> 18) & 0x3f;
68         hd_gpio_num = (spiconfig >> 24)  & 0x3f;
69         wp_gpio_num = wp_pin;
70     }
71     esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
72     esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
73     esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
74     esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
75     if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
76         esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
77     }
78     if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
79         esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
80     }
81 }
82 
bootloader_reset_mmu(void)83 static void bootloader_reset_mmu(void)
84 {
85     Cache_Suspend_ICache();
86     Cache_Invalidate_ICache_All();
87     Cache_MMU_Init();
88 
89     REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
90     REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
91 }
92 
update_flash_config(const esp_image_header_t * bootloader_hdr)93 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
94 {
95     uint32_t size;
96     switch (bootloader_hdr->spi_size) {
97     case ESP_IMAGE_FLASH_SIZE_1MB:
98         size = 1;
99         break;
100     case ESP_IMAGE_FLASH_SIZE_2MB:
101         size = 2;
102         break;
103     case ESP_IMAGE_FLASH_SIZE_4MB:
104         size = 4;
105         break;
106     case ESP_IMAGE_FLASH_SIZE_8MB:
107         size = 8;
108         break;
109     case ESP_IMAGE_FLASH_SIZE_16MB:
110         size = 16;
111         break;
112     default:
113         size = 2;
114     }
115     uint32_t autoload = Cache_Suspend_ICache();
116     // Set flash chip size
117     esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);    // TODO: set mode
118     Cache_Resume_ICache(autoload);
119 }
120 
print_flash_info(const esp_image_header_t * bootloader_hdr)121 static void print_flash_info(const esp_image_header_t *bootloader_hdr)
122 {
123     ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
124     ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
125     ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
126     ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
127     ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
128 
129     const char *str;
130     switch (bootloader_hdr->spi_speed) {
131     case ESP_IMAGE_SPI_SPEED_40M:
132         str = "40MHz";
133         break;
134     case ESP_IMAGE_SPI_SPEED_26M:
135         str = "26.7MHz";
136         break;
137     case ESP_IMAGE_SPI_SPEED_20M:
138         str = "20MHz";
139         break;
140     case ESP_IMAGE_SPI_SPEED_80M:
141         str = "80MHz";
142         break;
143     default:
144         str = "20MHz";
145         break;
146     }
147     ESP_LOGI(TAG, "SPI Speed      : %s", str);
148 
149     /* SPI mode could have been set to QIO during boot already,
150        so test the SPI registers not the flash header */
151     uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
152     if (spi_ctrl & SPI_MEM_FREAD_QIO) {
153         str = "QIO";
154     } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
155         str = "QOUT";
156     } else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
157         str = "DIO";
158     } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
159         str = "DOUT";
160     } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
161         str = "FAST READ";
162     } else {
163         str = "SLOW READ";
164     }
165     ESP_LOGI(TAG, "SPI Mode       : %s", str);
166 
167     switch (bootloader_hdr->spi_size) {
168     case ESP_IMAGE_FLASH_SIZE_1MB:
169         str = "1MB";
170         break;
171     case ESP_IMAGE_FLASH_SIZE_2MB:
172         str = "2MB";
173         break;
174     case ESP_IMAGE_FLASH_SIZE_4MB:
175         str = "4MB";
176         break;
177     case ESP_IMAGE_FLASH_SIZE_8MB:
178         str = "8MB";
179         break;
180     case ESP_IMAGE_FLASH_SIZE_16MB:
181         str = "16MB";
182         break;
183     default:
184         str = "2MB";
185         break;
186     }
187     ESP_LOGI(TAG, "SPI Flash Size : %s", str);
188 }
189 
bootloader_init_flash_configure(void)190 static void IRAM_ATTR bootloader_init_flash_configure(void)
191 {
192     bootloader_flash_dummy_config(&bootloader_image_hdr);
193     bootloader_flash_cs_timing_config();
194 }
195 
bootloader_spi_flash_resume(void)196 static void bootloader_spi_flash_resume(void)
197 {
198     bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
199     esp_rom_spiflash_wait_idle(&g_rom_flashchip);
200 }
201 
bootloader_init_spi_flash(void)202 static esp_err_t bootloader_init_spi_flash(void)
203 {
204     bootloader_init_flash_configure();
205 #ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
206     const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
207     if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
208         ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
209         return ESP_FAIL;
210     }
211 #endif
212 
213     bootloader_spi_flash_resume();
214     esp_rom_spiflash_unlock();
215 
216 #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
217     bootloader_enable_qio_mode();
218 #endif
219 
220     print_flash_info(&bootloader_image_hdr);
221     update_flash_config(&bootloader_image_hdr);
222     //ensure the flash is write-protected
223     bootloader_enable_wp();
224     return ESP_OK;
225 }
226 
wdt_reset_cpu0_info_enable(void)227 static void wdt_reset_cpu0_info_enable(void)
228 {
229     REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
230     REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
231     REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
232 }
233 
wdt_reset_info_dump(int cpu)234 static void wdt_reset_info_dump(int cpu)
235 {
236     // TODO ESP32-C3 IDF-2118
237     ESP_LOGE(TAG, "WDT reset info dump is not supported yet");
238 }
239 
bootloader_check_wdt_reset(void)240 static void bootloader_check_wdt_reset(void)
241 {
242     int wdt_rst = 0;
243     RESET_REASON rst_reas[2];
244 
245     rst_reas[0] = rtc_get_reset_reason(0);
246     if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
247             rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
248         ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
249         wdt_rst = 1;
250     }
251     if (wdt_rst) {
252         // if reset by WDT dump info from trace port
253         wdt_reset_info_dump(0);
254     }
255     wdt_reset_cpu0_info_enable();
256 }
257 
bootloader_super_wdt_auto_feed(void)258 static void bootloader_super_wdt_auto_feed(void)
259 {
260     REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
261     REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
262     REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
263 }
264 
bootloader_hardware_init(void)265 static inline void bootloader_hardware_init(void)
266 {
267     // This check is always included in the bootloader so it can
268     // print the minimum revision error message later in the boot
269     if (bootloader_common_get_chip_revision() < 3) {
270         REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1);
271         REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
272     }
273 }
274 
bootloader_glitch_reset_disable(void)275 static inline void bootloader_glitch_reset_disable(void)
276 {
277     uint8_t chip_version = bootloader_common_get_chip_revision();
278     if (chip_version < 2) {
279         REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST);
280     } else {
281         REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST | RTC_CNTL_FIB_BOR_RST);
282     }
283 }
284 
bootloader_init(void)285 esp_err_t bootloader_init(void)
286 {
287     esp_err_t ret = ESP_OK;
288 
289     bootloader_hardware_init();
290     bootloader_glitch_reset_disable();
291     bootloader_super_wdt_auto_feed();
292     // protect memory region
293     bootloader_init_mem();
294     /* check that static RAM is after the stack */
295     assert(&_bss_start <= &_bss_end);
296     assert(&_data_start <= &_data_end);
297     // clear bss section
298     bootloader_clear_bss_section();
299     // reset MMU
300     bootloader_reset_mmu();
301     // config clock
302     bootloader_clock_configure();
303     // initialize console, from now on, we can use esp_log
304     bootloader_console_init();
305     /* print 2nd bootloader banner */
306     bootloader_print_banner();
307     // update flash ID
308     bootloader_flash_update_id();
309     // read bootloader header
310     if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
311         goto err;
312     }
313     // read chip revision and check if it's compatible to bootloader
314     if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
315         goto err;
316     }
317     // initialize spi flash
318     if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
319         goto err;
320     }
321     // check whether a WDT reset happend
322     bootloader_check_wdt_reset();
323     // config WDT
324     bootloader_config_wdt();
325     // enable RNG early entropy source
326     bootloader_enable_random();
327 err:
328     return ret;
329 }
330