1 // Copyright 2019 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "bootloader_common.h"
16 #include "bootloader_clock.h"
17 #include "soc/efuse_reg.h"
18 #include "soc/apb_ctrl_reg.h"
19
bootloader_common_get_chip_revision(void)20 uint8_t bootloader_common_get_chip_revision(void)
21 {
22 uint8_t eco_bit0, eco_bit1, eco_bit2;
23 eco_bit0 = (REG_READ(EFUSE_BLK0_RDATA3_REG) & 0xF000) >> 15;
24 eco_bit1 = (REG_READ(EFUSE_BLK0_RDATA5_REG) & 0x100000) >> 20;
25 eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 0x80000000) >> 31;
26 uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
27 uint8_t chip_ver = 0;
28 switch (combine_value) {
29 case 0:
30 chip_ver = 0;
31 break;
32 case 1:
33 chip_ver = 1;
34 break;
35 case 3:
36 chip_ver = 2;
37 break;
38 case 7:
39 chip_ver = 3;
40 break;
41 default:
42 chip_ver = 0;
43 break;
44 }
45 return chip_ver;
46 }
47
bootloader_common_get_chip_ver_pkg(void)48 uint32_t bootloader_common_get_chip_ver_pkg(void)
49 {
50 uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
51 uint32_t pkg_version_4bit = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG_4BIT);
52 return (pkg_version_4bit << 3) | pkg_version;
53 }
54
bootloader_clock_get_rated_freq_mhz()55 int bootloader_clock_get_rated_freq_mhz()
56 {
57 //Check if ESP32 is rated for a CPU frequency of 160MHz only
58 if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) &&
59 REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) {
60 return 160;
61 }
62 return 240;
63 }
64
