1 /** 2 ****************************************************************************** 3 * @file timer_reg.h 4 * @version V1.0 5 * @date 2022-08-03 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_TIMER_H__ 37 #define __HARDWARE_TIMER_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #define TIMER_TCCR_OFFSET (0x0) /* Timer Clock Source */ 46 #define TIMER_TMR0_0_OFFSET (0x10) /* Timer0 Match Value 0 */ 47 #define TIMER_TMR0_1_OFFSET (0x14) /* Timer0 Match Value 1 */ 48 #define TIMER_TMR0_2_OFFSET (0x18) /* Timer0 Match Value 2 */ 49 #define TIMER_TMR1_0_OFFSET (0x1C) /* Timer1 Match Value 0 */ 50 #define TIMER_TMR1_1_OFFSET (0x20) /* Timer1 Match Value 1 */ 51 #define TIMER_TMR1_2_OFFSET (0x24) /* Timer1 Match Value 2 */ 52 #define TIMER_TCR0_OFFSET (0x2C) /* Timer0 Counter Value */ 53 #define TIMER_TCR1_OFFSET (0x30) /* Timer1 Counter Value */ 54 #define TIMER_TSR0_OFFSET (0x38) /* Timer0 Match Status */ 55 #define TIMER_TSR1_OFFSET (0x3C) /* Timer1 Match Status */ 56 #define TIMER_TIER0_OFFSET (0x44) /* Timer0 Match Interrupt Enable */ 57 #define TIMER_TIER1_OFFSET (0x48) /* Timer1 Match Interrupt Enable */ 58 #define TIMER_TPLVR0_OFFSET (0x50) /* Timer0 Pre-Load Value */ 59 #define TIMER_TPLVR1_OFFSET (0x54) /* Timer1 Pre-Load Value */ 60 #define TIMER_TPLCR0_OFFSET (0x5C) /* Timer0 Pre-Load Control */ 61 #define TIMER_TPLCR1_OFFSET (0x60) /* Timer1 Pre-Load Control */ 62 #define TIMER_WMER_OFFSET (0x64) /* Watch-dog reset/interrupt Mode */ 63 #define TIMER_WMR_OFFSET (0x68) /* Watch-dog Match Value */ 64 #define TIMER_WVR_OFFSET (0x6C) /* Watch-dog Counter Value */ 65 #define TIMER_WSR_OFFSET (0x70) /* Watch-dog Reset Status */ 66 #define TIMER_TICR0_OFFSET (0x78) /* Timer0 Interrupt Clear */ 67 #define TIMER_TICR1_OFFSET (0x7C) /* Timer1 Interrupt Clear */ 68 #define TIMER_WICR_OFFSET (0x80) /* WDT Interrupt Clear */ 69 #define TIMER_TCER_OFFSET (0x84) /* Timer Counter Enable/Clear */ 70 #define TIMER_TCMR_OFFSET (0x88) /* Timer Counter Mode */ 71 #define TIMER_TILR0_OFFSET (0x90) /* Timer0 Match Interrupt Mode */ 72 #define TIMER_TILR1_OFFSET (0x94) /* Timer1 Match Interrupt Mode */ 73 #define TIMER_WCR_OFFSET (0x98) /* WDT Counter Reset */ 74 #define TIMER_WFAR_OFFSET (0x9C) /* WDT Access Key1 */ 75 #define TIMER_WSAR_OFFSET (0xA0) /* WDT Access Key2 */ 76 #define TIMER_TCVWR0_OFFSET (0xA8) /* Timer0 Counter Latch Value */ 77 #define TIMER_TCVWR1_OFFSET (0xAC) /* Timer1 Counter Latch Value */ 78 #define TIMER_TCVSYN0_OFFSET (0xB4) /* Timer0 Counter Sync Value */ 79 #define TIMER_TCVSYN1_OFFSET (0xB8) /* Timer1 Counter Sync Value */ 80 #define TIMER_TCDR_OFFSET (0xBC) /* Timer Division */ 81 82 /* Register Bitfield definitions *****************************************************/ 83 84 /* 0x10 : Timer0 Match Value 0 */ 85 #define TIMER_TMR0_0_SHIFT (0U) 86 #define TIMER_TMR0_0_MASK (0xffffffff << TIMER_TMR0_0_SHIFT) 87 88 /* 0x14 : Timer0 Match Value 1 */ 89 #define TIMER_TMR0_1_SHIFT (0U) 90 #define TIMER_TMR0_1_MASK (0xffffffff << TIMER_TMR0_1_SHIFT) 91 92 /* 0x18 : Timer0 Match Value 2 */ 93 #define TIMER_TMR0_2_SHIFT (0U) 94 #define TIMER_TMR0_2_MASK (0xffffffff << TIMER_TMR0_2_SHIFT) 95 96 /* 0x1C : Timer1 Match Value 0 */ 97 #define TIMER_TMR1_0_SHIFT (0U) 98 #define TIMER_TMR1_0_MASK (0xffffffff << TIMER_TMR1_0_SHIFT) 99 100 /* 0x20 : Timer1 Match Value 1 */ 101 #define TIMER_TMR1_1_SHIFT (0U) 102 #define TIMER_TMR1_1_MASK (0xffffffff << TIMER_TMR1_1_SHIFT) 103 104 /* 0x24 : Timer1 Match Value 2 */ 105 #define TIMER_TMR1_2_SHIFT (0U) 106 #define TIMER_TMR1_2_MASK (0xffffffff << TIMER_TMR1_2_SHIFT) 107 108 /* 0x2C : Timer0 Counter Value */ 109 #define TIMER_TCR0_CNT_SHIFT (0U) 110 #define TIMER_TCR0_CNT_MASK (0xffffffff << TIMER_TCR0_CNT_SHIFT) 111 112 /* 0x30 : Timer1 Counter Value */ 113 #define TIMER_TCR1_CNT_SHIFT (0U) 114 #define TIMER_TCR1_CNT_MASK (0xffffffff << TIMER_TCR1_CNT_SHIFT) 115 116 /* 0x38 : Timer0 Match Status */ 117 #define TIMER_TSR0_0 (1 << 0U) 118 #define TIMER_TSR0_1 (1 << 1U) 119 #define TIMER_TSR0_2 (1 << 2U) 120 121 /* 0x3C : Timer1 Match Status */ 122 #define TIMER_TSR1_0 (1 << 0U) 123 #define TIMER_TSR1_1 (1 << 1U) 124 #define TIMER_TSR1_2 (1 << 2U) 125 126 /* 0x44 : Timer0 Match Interrupt Enable */ 127 #define TIMER_TIER0_0 (1 << 0U) 128 #define TIMER_TIER0_1 (1 << 1U) 129 #define TIMER_TIER0_2 (1 << 2U) 130 131 /* 0x48 : Timer1 Match Interrupt Enable */ 132 #define TIMER_TIER1_0 (1 << 0U) 133 #define TIMER_TIER1_1 (1 << 1U) 134 #define TIMER_TIER1_2 (1 << 2U) 135 136 /* 0x50 : Timer0 Pre-Load Value */ 137 #define TIMER_TPLVR0_SHIFT (0U) 138 #define TIMER_TPLVR0_MASK (0xffffffff << TIMER_TPLVR0_SHIFT) 139 140 /* 0x54 : Timer1 Pre-Load Value */ 141 #define TIMER_TPLVR1_SHIFT (0U) 142 #define TIMER_TPLVR1_MASK (0xffffffff << TIMER_TPLVR1_SHIFT) 143 144 /* 0x5C : Timer0 Pre-Load Control */ 145 #define TIMER_TPLCR0_SHIFT (0U) 146 #define TIMER_TPLCR0_MASK (0x3 << TIMER_TPLCR0_SHIFT) 147 148 /* 0x60 : Timer1 Pre-Load Control */ 149 #define TIMER_TPLCR1_SHIFT (0U) 150 #define TIMER_TPLCR1_MASK (0x3 << TIMER_TPLCR1_SHIFT) 151 152 /* 0x64 : Watch-dog reset/interrupt Mode */ 153 #define TIMER_WE (1 << 0U) 154 #define TIMER_WRIE (1 << 1U) 155 156 /* 0x68 : Watch-dog Match Value */ 157 #define TIMER_WMR_SHIFT (0U) 158 #define TIMER_WMR_MASK (0xffff << TIMER_WMR_SHIFT) 159 #define TIMER_WDT_ALIGN (1 << 16U) 160 161 /* 0x6C : Watch-dog Counter Value */ 162 #define TIMER_WDT_CNT_SHIFT (0U) 163 #define TIMER_WDT_CNT_MASK (0xffff << TIMER_WDT_CNT_SHIFT) 164 165 /* 0x70 : Watch-dog Reset Status */ 166 #define TIMER_WTS (1 << 0U) 167 168 /* 0x78 : Timer0 Interrupt Clear */ 169 #define TIMER_TCLR0_0 (1 << 0U) 170 #define TIMER_TCLR0_1 (1 << 1U) 171 #define TIMER_TCLR0_2 (1 << 2U) 172 173 /* 0x7C : Timer1 Interrupt Clear */ 174 #define TIMER_TCLR1_0 (1 << 0U) 175 #define TIMER_TCLR1_1 (1 << 1U) 176 #define TIMER_TCLR1_2 (1 << 2U) 177 178 /* 0x80 : WDT Interrupt Clear */ 179 #define TIMER_WICLR (1 << 0U) 180 181 /* 0x84 : Timer Counter Enable/Clear */ 182 #define TIMER0_EN (1 << 1U) 183 #define TIMER1_EN (1 << 2U) 184 #define TIMER_TCR0_CNT_CLR (1 << 5U) 185 #define TIMER_TCR1_CNT_CLR (1 << 6U) 186 187 /* 0x88 : Timer Counter Mode */ 188 #define TIMER0_MODE (1 << 1U) 189 #define TIMER1_MODE (1 << 2U) 190 #define TIMER0_ALIGN (1 << 5U) 191 #define TIMER1_ALIGN (1 << 6U) 192 193 /* 0x90 : Timer0 Match Interrupt Mode */ 194 #define TIMER_TILR0_0 (1 << 0U) 195 #define TIMER_TILR0_1 (1 << 1U) 196 #define TIMER_TILR0_2 (1 << 2U) 197 198 /* 0x94 : Timer1 Match Interrupt Mode */ 199 #define TIMER_TILR1_0 (1 << 0U) 200 #define TIMER_TILR1_1 (1 << 1U) 201 #define TIMER_TILR1_2 (1 << 2U) 202 203 /* 0x98 : WDT Counter Reset */ 204 #define TIMER_WCR (1 << 0U) 205 206 /* 0x9C : WDT Access Key1 */ 207 #define TIMER_WFAR_SHIFT (0U) 208 #define TIMER_WFAR_MASK (0xffff << TIMER_WFAR_SHIFT) 209 210 /* 0xA0 : WDT Access Key2 */ 211 #define TIMER_WSAR_SHIFT (0U) 212 #define TIMER_WSAR_MASK (0xffff << TIMER_WSAR_SHIFT) 213 214 /* 0xA8 : Timer0 Counter Latch Value */ 215 #define TIMER_TCR0_CNT_LAT_SHIFT (0U) 216 #define TIMER_TCR0_CNT_LAT_MASK (0xffffffff << TIMER_TCR0_CNT_LAT_SHIFT) 217 218 /* 0xAC : Timer1 Counter Latch Value */ 219 #define TIMER_TCR1_CNT_LAT_SHIFT (0U) 220 #define TIMER_TCR1_CNT_LAT_MASK (0xffffffff << TIMER_TCR1_CNT_LAT_SHIFT) 221 222 /* 0xB4 : Timer0 Counter Sync Value */ 223 #define TIMER_TCR0_CNT_SYNC_SHIFT (0U) 224 #define TIMER_TCR0_CNT_SYNC_MASK (0xffffffff << TIMER_TCR0_CNT_SYNC_SHIFT) 225 226 /* 0xB8 : Timer1 Counter Sync Value */ 227 #define TIMER_TCR1_CNT_SYNC_SHIFT (0U) 228 #define TIMER_TCR1_CNT_SYNC_MASK (0xffffffff << TIMER_TCR1_CNT_SYNC_SHIFT) 229 230 /* 0xBC : Timer Division */ 231 #define TIMER_TCDR0_SHIFT (8U) 232 #define TIMER_TCDR0_MASK (0xff << TIMER_TCDR0_SHIFT) 233 #define TIMER_TCDR1_SHIFT (16U) 234 #define TIMER_TCDR1_MASK (0xff << TIMER_TCDR1_SHIFT) 235 #define TIMER_WCDR_SHIFT (24U) 236 #define TIMER_WCDR_MASK (0xff << TIMER_WCDR_SHIFT) 237 238 #endif /* __HARDWARE_TIMER_H__ */ 239
