1 /** 2 * \file 3 * 4 * \brief Instance description for OSCCTRL 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR35_OSCCTRL_INSTANCE_ 31 #define _SAMR35_OSCCTRL_INSTANCE_ 32 33 /* ========== Register definition for OSCCTRL peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_OSCCTRL_INTENCLR (0x40000C00) /**< \brief (OSCCTRL) Interrupt Enable Clear */ 36 #define REG_OSCCTRL_INTENSET (0x40000C04) /**< \brief (OSCCTRL) Interrupt Enable Set */ 37 #define REG_OSCCTRL_INTFLAG (0x40000C08) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ 38 #define REG_OSCCTRL_STATUS (0x40000C0C) /**< \brief (OSCCTRL) Power and Clocks Status */ 39 #define REG_OSCCTRL_XOSCCTRL (0x40000C10) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ 40 #define REG_OSCCTRL_OSC16MCTRL (0x40000C14) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ 41 #define REG_OSCCTRL_DFLLCTRL (0x40000C18) /**< \brief (OSCCTRL) DFLL48M Control */ 42 #define REG_OSCCTRL_DFLLVAL (0x40000C1C) /**< \brief (OSCCTRL) DFLL48M Value */ 43 #define REG_OSCCTRL_DFLLMUL (0x40000C20) /**< \brief (OSCCTRL) DFLL48M Multiplier */ 44 #define REG_OSCCTRL_DFLLSYNC (0x40000C24) /**< \brief (OSCCTRL) DFLL48M Synchronization */ 45 #define REG_OSCCTRL_DPLLCTRLA (0x40000C28) /**< \brief (OSCCTRL) DPLL Control */ 46 #define REG_OSCCTRL_DPLLRATIO (0x40000C2C) /**< \brief (OSCCTRL) DPLL Ratio Control */ 47 #define REG_OSCCTRL_DPLLCTRLB (0x40000C30) /**< \brief (OSCCTRL) Digital Core Configuration */ 48 #define REG_OSCCTRL_DPLLPRESC (0x40000C34) /**< \brief (OSCCTRL) DPLL Prescaler */ 49 #define REG_OSCCTRL_DPLLSYNCBUSY (0x40000C38) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ 50 #define REG_OSCCTRL_DPLLSTATUS (0x40000C3C) /**< \brief (OSCCTRL) DPLL Status */ 51 #else 52 #define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40000C00UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */ 53 #define REG_OSCCTRL_INTENSET (*(RwReg *)0x40000C04UL) /**< \brief (OSCCTRL) Interrupt Enable Set */ 54 #define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40000C08UL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ 55 #define REG_OSCCTRL_STATUS (*(RoReg *)0x40000C0CUL) /**< \brief (OSCCTRL) Power and Clocks Status */ 56 #define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40000C10UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ 57 #define REG_OSCCTRL_OSC16MCTRL (*(RwReg8 *)0x40000C14UL) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ 58 #define REG_OSCCTRL_DFLLCTRL (*(RwReg16*)0x40000C18UL) /**< \brief (OSCCTRL) DFLL48M Control */ 59 #define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x40000C1CUL) /**< \brief (OSCCTRL) DFLL48M Value */ 60 #define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40000C20UL) /**< \brief (OSCCTRL) DFLL48M Multiplier */ 61 #define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x40000C24UL) /**< \brief (OSCCTRL) DFLL48M Synchronization */ 62 #define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x40000C28UL) /**< \brief (OSCCTRL) DPLL Control */ 63 #define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x40000C2CUL) /**< \brief (OSCCTRL) DPLL Ratio Control */ 64 #define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40000C30UL) /**< \brief (OSCCTRL) Digital Core Configuration */ 65 #define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40000C34UL) /**< \brief (OSCCTRL) DPLL Prescaler */ 66 #define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x40000C38UL) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ 67 #define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x40000C3CUL) /**< \brief (OSCCTRL) DPLL Status */ 68 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 69 70 /* ========== Instance parameters for OSCCTRL peripheral ========== */ 71 #define OSCCTRL_DFLL48M_COARSE_MSB 5 72 #define OSCCTRL_DFLL48M_FINE_MSB 9 73 #define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 74 #define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL 75 #define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K 76 #define OSCCTRL_DFLL48M_VERSION 0x320 77 #define OSCCTRL_FDPLL_VERSION 0x200 78 #define OSCCTRL_OSC16M_VERSION 0x100 79 #define OSCCTRL_XOSC_VERSION 0x120 80 81 #endif /* _SAMR35_OSCCTRL_INSTANCE_ */ 82
