1 /** 2 * \file 3 * 4 * \brief Component description for OSC32KCTRL 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR35_OSC32KCTRL_COMPONENT_ 31 #define _SAMR35_OSC32KCTRL_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR OSC32KCTRL */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMR35_OSC32KCTRL 32k Oscillators Control */ 37 /*@{*/ 38 39 #define OSC32KCTRL_U2246 40 #define REV_OSC32KCTRL 0x110 41 42 /* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ 47 uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready Interrupt Enable */ 48 uint32_t :30; /*!< bit: 2..31 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 uint32_t reg; /*!< Type used for register access */ 51 } OSC32KCTRL_INTENCLR_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 #define OSC32KCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */ 55 #define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */ 56 57 #define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */ 58 #define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos) 59 #define OSC32KCTRL_INTENCLR_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTENCLR) OSC32K Ready Interrupt Enable */ 60 #define OSC32KCTRL_INTENCLR_OSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_OSC32KRDY_Pos) 61 #define OSC32KCTRL_INTENCLR_MASK _U_(0x00000003) /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */ 62 63 /* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ 64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 65 typedef union { 66 struct { 67 uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ 68 uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready Interrupt Enable */ 69 uint32_t :30; /*!< bit: 2..31 Reserved */ 70 } bit; /*!< Structure used for bit access */ 71 uint32_t reg; /*!< Type used for register access */ 72 } OSC32KCTRL_INTENSET_Type; 73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 #define OSC32KCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */ 76 #define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */ 77 78 #define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */ 79 #define OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos) 80 #define OSC32KCTRL_INTENSET_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTENSET) OSC32K Ready Interrupt Enable */ 81 #define OSC32KCTRL_INTENSET_OSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_OSC32KRDY_Pos) 82 #define OSC32KCTRL_INTENSET_MASK _U_(0x00000003) /**< \brief (OSC32KCTRL_INTENSET) MASK Register */ 83 84 /* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ 85 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 86 typedef union { // __I to avoid read-modify-write on write-to-clear register 87 struct { 88 __I uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ 89 __I uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */ 90 __I uint32_t Reserved1:30; /*!< bit: 2..31 Reserved */ 91 } bit; /*!< Structure used for bit access */ 92 uint32_t reg; /*!< Type used for register access */ 93 } OSC32KCTRL_INTFLAG_Type; 94 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 95 96 #define OSC32KCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ 97 #define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ 98 99 #define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */ 100 #define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos) 101 #define OSC32KCTRL_INTFLAG_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTFLAG) OSC32K Ready */ 102 #define OSC32KCTRL_INTFLAG_OSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_OSC32KRDY_Pos) 103 #define OSC32KCTRL_INTFLAG_MASK _U_(0x00000003) /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */ 104 105 /* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ 106 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 107 typedef union { 108 struct { 109 uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ 110 uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */ 111 uint32_t :30; /*!< bit: 2..31 Reserved */ 112 } bit; /*!< Structure used for bit access */ 113 uint32_t reg; /*!< Type used for register access */ 114 } OSC32KCTRL_STATUS_Type; 115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 116 117 #define OSC32KCTRL_STATUS_OFFSET 0x0C /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */ 118 #define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */ 119 120 #define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */ 121 #define OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos) 122 #define OSC32KCTRL_STATUS_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_STATUS) OSC32K Ready */ 123 #define OSC32KCTRL_STATUS_OSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_OSC32KRDY_Pos) 124 #define OSC32KCTRL_STATUS_MASK _U_(0x00000003) /**< \brief (OSC32KCTRL_STATUS) MASK Register */ 125 126 /* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 32) Clock selection -------- */ 127 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 128 typedef union { 129 struct { 130 uint32_t RTCSEL:3; /*!< bit: 0.. 2 RTC Clock Selection */ 131 uint32_t :29; /*!< bit: 3..31 Reserved */ 132 } bit; /*!< Structure used for bit access */ 133 uint32_t reg; /*!< Type used for register access */ 134 } OSC32KCTRL_RTCCTRL_Type; 135 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 136 137 #define OSC32KCTRL_RTCCTRL_OFFSET 0x10 /**< \brief (OSC32KCTRL_RTCCTRL offset) Clock selection */ 138 #define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_RTCCTRL reset_value) Clock selection */ 139 140 #define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0 /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */ 141 #define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 142 #define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)) 143 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */ 144 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */ 145 #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val _U_(0x2) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */ 146 #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val _U_(0x3) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz internal oscillator */ 147 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */ 148 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */ 149 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 150 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 151 #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 152 #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 153 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 154 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 155 #define OSC32KCTRL_RTCCTRL_MASK _U_(0x00000007) /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */ 156 157 /* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 32) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ 158 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 159 typedef union { 160 struct { 161 uint32_t :1; /*!< bit: 0 Reserved */ 162 uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 163 uint32_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ 164 uint32_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ 165 uint32_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ 166 uint32_t :1; /*!< bit: 5 Reserved */ 167 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 168 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 169 uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ 170 uint32_t :1; /*!< bit: 11 Reserved */ 171 uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ 172 uint32_t :19; /*!< bit: 13..31 Reserved */ 173 } bit; /*!< Structure used for bit access */ 174 uint32_t reg; /*!< Type used for register access */ 175 } OSC32KCTRL_XOSC32K_Type; 176 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 177 178 #define OSC32KCTRL_XOSC32K_OFFSET 0x14 /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */ 179 #define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x00000080) /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */ 180 181 #define OSC32KCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */ 182 #define OSC32KCTRL_XOSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos) 183 #define OSC32KCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */ 184 #define OSC32KCTRL_XOSC32K_XTALEN (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos) 185 #define OSC32KCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */ 186 #define OSC32KCTRL_XOSC32K_EN32K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos) 187 #define OSC32KCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */ 188 #define OSC32KCTRL_XOSC32K_EN1K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos) 189 #define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */ 190 #define OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) 191 #define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */ 192 #define OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) 193 #define OSC32KCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */ 194 #define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos) 195 #define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos)) 196 #define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */ 197 #define OSC32KCTRL_XOSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos) 198 #define OSC32KCTRL_XOSC32K_MASK _U_(0x000017DE) /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */ 199 200 /* -------- OSC32KCTRL_OSC32K : (OSC32KCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */ 201 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 202 typedef union { 203 struct { 204 uint32_t :1; /*!< bit: 0 Reserved */ 205 uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 206 uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ 207 uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ 208 uint32_t :2; /*!< bit: 4.. 5 Reserved */ 209 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 210 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 211 uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ 212 uint32_t :1; /*!< bit: 11 Reserved */ 213 uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ 214 uint32_t :3; /*!< bit: 13..15 Reserved */ 215 uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ 216 uint32_t :9; /*!< bit: 23..31 Reserved */ 217 } bit; /*!< Structure used for bit access */ 218 uint32_t reg; /*!< Type used for register access */ 219 } OSC32KCTRL_OSC32K_Type; 220 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 221 222 #define OSC32KCTRL_OSC32K_OFFSET 0x18 /**< \brief (OSC32KCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */ 223 #define OSC32KCTRL_OSC32K_RESETVALUE _U_(0x003F0080) /**< \brief (OSC32KCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */ 224 225 #define OSC32KCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Enable */ 226 #define OSC32KCTRL_OSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_OSC32K_ENABLE_Pos) 227 #define OSC32KCTRL_OSC32K_EN32K_Pos 2 /**< \brief (OSC32KCTRL_OSC32K) 32kHz Output Enable */ 228 #define OSC32KCTRL_OSC32K_EN32K (_U_(0x1) << OSC32KCTRL_OSC32K_EN32K_Pos) 229 #define OSC32KCTRL_OSC32K_EN1K_Pos 3 /**< \brief (OSC32KCTRL_OSC32K) 1kHz Output Enable */ 230 #define OSC32KCTRL_OSC32K_EN1K (_U_(0x1) << OSC32KCTRL_OSC32K_EN1K_Pos) 231 #define OSC32KCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_OSC32K) Run in Standby */ 232 #define OSC32KCTRL_OSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_OSC32K_RUNSTDBY_Pos) 233 #define OSC32KCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_OSC32K) On Demand Control */ 234 #define OSC32KCTRL_OSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_OSC32K_ONDEMAND_Pos) 235 #define OSC32KCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Start-Up Time */ 236 #define OSC32KCTRL_OSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_OSC32K_STARTUP_Pos) 237 #define OSC32KCTRL_OSC32K_STARTUP(value) (OSC32KCTRL_OSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_OSC32K_STARTUP_Pos)) 238 #define OSC32KCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_OSC32K) Write Lock */ 239 #define OSC32KCTRL_OSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSC32K_WRTLOCK_Pos) 240 #define OSC32KCTRL_OSC32K_CALIB_Pos 16 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Calibration */ 241 #define OSC32KCTRL_OSC32K_CALIB_Msk (_U_(0x7F) << OSC32KCTRL_OSC32K_CALIB_Pos) 242 #define OSC32KCTRL_OSC32K_CALIB(value) (OSC32KCTRL_OSC32K_CALIB_Msk & ((value) << OSC32KCTRL_OSC32K_CALIB_Pos)) 243 #define OSC32KCTRL_OSC32K_MASK _U_(0x007F17CE) /**< \brief (OSC32KCTRL_OSC32K) MASK Register */ 244 245 /* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ 246 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 247 typedef union { 248 struct { 249 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 250 uint32_t CALIB:5; /*!< bit: 8..12 Oscillator Calibration */ 251 uint32_t :2; /*!< bit: 13..14 Reserved */ 252 uint32_t WRTLOCK:1; /*!< bit: 15 Write Lock */ 253 uint32_t :16; /*!< bit: 16..31 Reserved */ 254 } bit; /*!< Structure used for bit access */ 255 uint32_t reg; /*!< Type used for register access */ 256 } OSC32KCTRL_OSCULP32K_Type; 257 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 258 259 #define OSC32KCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ 260 261 #define OSC32KCTRL_OSCULP32K_CALIB_Pos 8 /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */ 262 #define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x1F) << OSC32KCTRL_OSCULP32K_CALIB_Pos) 263 #define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos)) 264 #define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15 /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */ 265 #define OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos) 266 #define OSC32KCTRL_OSCULP32K_MASK _U_(0x00009F00) /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */ 267 268 /** \brief OSC32KCTRL hardware registers */ 269 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 270 typedef struct { 271 __IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ 272 __IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ 273 __IO OSC32KCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ 274 __I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ 275 __IO OSC32KCTRL_RTCCTRL_Type RTCCTRL; /**< \brief Offset: 0x10 (R/W 32) Clock selection */ 276 __IO OSC32KCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 32) 32kHz External Crystal Oscillator (XOSC32K) Control */ 277 __IO OSC32KCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ 278 __IO OSC32KCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ 279 } Osc32kctrl; 280 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 281 282 /*@}*/ 283 284 #endif /* _SAMR35_OSC32KCTRL_COMPONENT_ */ 285
