1 /** 2 * \file 3 * 4 * \brief Component description for MCLK 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR35_MCLK_COMPONENT_ 31 #define _SAMR35_MCLK_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR MCLK */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMR35_MCLK Main Clock */ 37 /*@{*/ 38 39 #define MCLK_U2234 40 #define REV_MCLK 0x101 41 42 /* -------- MCLK_CTRLA : (MCLK Offset: 0x00) (R/W 8) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 uint8_t reg; /*!< Type used for register access */ 46 } MCLK_CTRLA_Type; 47 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 48 49 #define MCLK_CTRLA_OFFSET 0x00 /**< \brief (MCLK_CTRLA offset) Control A */ 50 #define MCLK_CTRLA_RESETVALUE _U_(0x00) /**< \brief (MCLK_CTRLA reset_value) Control A */ 51 #define MCLK_CTRLA_MASK _U_(0x00) /**< \brief (MCLK_CTRLA) MASK Register */ 52 53 /* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */ 54 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 55 typedef union { 56 struct { 57 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ 58 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 59 } bit; /*!< Structure used for bit access */ 60 uint8_t reg; /*!< Type used for register access */ 61 } MCLK_INTENCLR_Type; 62 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 63 64 #define MCLK_INTENCLR_OFFSET 0x01 /**< \brief (MCLK_INTENCLR offset) Interrupt Enable Clear */ 65 #define MCLK_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENCLR reset_value) Interrupt Enable Clear */ 66 67 #define MCLK_INTENCLR_CKRDY_Pos 0 /**< \brief (MCLK_INTENCLR) Clock Ready Interrupt Enable */ 68 #define MCLK_INTENCLR_CKRDY (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos) 69 #define MCLK_INTENCLR_MASK _U_(0x01) /**< \brief (MCLK_INTENCLR) MASK Register */ 70 71 /* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */ 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 73 typedef union { 74 struct { 75 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ 76 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 77 } bit; /*!< Structure used for bit access */ 78 uint8_t reg; /*!< Type used for register access */ 79 } MCLK_INTENSET_Type; 80 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 81 82 #define MCLK_INTENSET_OFFSET 0x02 /**< \brief (MCLK_INTENSET offset) Interrupt Enable Set */ 83 #define MCLK_INTENSET_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENSET reset_value) Interrupt Enable Set */ 84 85 #define MCLK_INTENSET_CKRDY_Pos 0 /**< \brief (MCLK_INTENSET) Clock Ready Interrupt Enable */ 86 #define MCLK_INTENSET_CKRDY (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos) 87 #define MCLK_INTENSET_MASK _U_(0x01) /**< \brief (MCLK_INTENSET) MASK Register */ 88 89 /* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */ 90 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 91 typedef union { // __I to avoid read-modify-write on write-to-clear register 92 struct { 93 __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ 94 __I uint8_t Reserved1:7; /*!< bit: 1.. 7 Reserved */ 95 } bit; /*!< Structure used for bit access */ 96 uint8_t reg; /*!< Type used for register access */ 97 } MCLK_INTFLAG_Type; 98 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 99 100 #define MCLK_INTFLAG_OFFSET 0x03 /**< \brief (MCLK_INTFLAG offset) Interrupt Flag Status and Clear */ 101 #define MCLK_INTFLAG_RESETVALUE _U_(0x01) /**< \brief (MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear */ 102 103 #define MCLK_INTFLAG_CKRDY_Pos 0 /**< \brief (MCLK_INTFLAG) Clock Ready */ 104 #define MCLK_INTFLAG_CKRDY (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos) 105 #define MCLK_INTFLAG_MASK _U_(0x01) /**< \brief (MCLK_INTFLAG) MASK Register */ 106 107 /* -------- MCLK_CPUDIV : (MCLK Offset: 0x04) (R/W 8) CPU Clock Division -------- */ 108 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 109 typedef union { 110 struct { 111 uint8_t CPUDIV:8; /*!< bit: 0.. 7 CPU Clock Division Factor */ 112 } bit; /*!< Structure used for bit access */ 113 uint8_t reg; /*!< Type used for register access */ 114 } MCLK_CPUDIV_Type; 115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 116 117 #define MCLK_CPUDIV_OFFSET 0x04 /**< \brief (MCLK_CPUDIV offset) CPU Clock Division */ 118 #define MCLK_CPUDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_CPUDIV reset_value) CPU Clock Division */ 119 120 #define MCLK_CPUDIV_CPUDIV_Pos 0 /**< \brief (MCLK_CPUDIV) CPU Clock Division Factor */ 121 #define MCLK_CPUDIV_CPUDIV_Msk (_U_(0xFF) << MCLK_CPUDIV_CPUDIV_Pos) 122 #define MCLK_CPUDIV_CPUDIV(value) (MCLK_CPUDIV_CPUDIV_Msk & ((value) << MCLK_CPUDIV_CPUDIV_Pos)) 123 #define MCLK_CPUDIV_CPUDIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_CPUDIV) Divide by 1 */ 124 #define MCLK_CPUDIV_CPUDIV_DIV2_Val _U_(0x2) /**< \brief (MCLK_CPUDIV) Divide by 2 */ 125 #define MCLK_CPUDIV_CPUDIV_DIV4_Val _U_(0x4) /**< \brief (MCLK_CPUDIV) Divide by 4 */ 126 #define MCLK_CPUDIV_CPUDIV_DIV8_Val _U_(0x8) /**< \brief (MCLK_CPUDIV) Divide by 8 */ 127 #define MCLK_CPUDIV_CPUDIV_DIV16_Val _U_(0x10) /**< \brief (MCLK_CPUDIV) Divide by 16 */ 128 #define MCLK_CPUDIV_CPUDIV_DIV32_Val _U_(0x20) /**< \brief (MCLK_CPUDIV) Divide by 32 */ 129 #define MCLK_CPUDIV_CPUDIV_DIV64_Val _U_(0x40) /**< \brief (MCLK_CPUDIV) Divide by 64 */ 130 #define MCLK_CPUDIV_CPUDIV_DIV128_Val _U_(0x80) /**< \brief (MCLK_CPUDIV) Divide by 128 */ 131 #define MCLK_CPUDIV_CPUDIV_DIV1 (MCLK_CPUDIV_CPUDIV_DIV1_Val << MCLK_CPUDIV_CPUDIV_Pos) 132 #define MCLK_CPUDIV_CPUDIV_DIV2 (MCLK_CPUDIV_CPUDIV_DIV2_Val << MCLK_CPUDIV_CPUDIV_Pos) 133 #define MCLK_CPUDIV_CPUDIV_DIV4 (MCLK_CPUDIV_CPUDIV_DIV4_Val << MCLK_CPUDIV_CPUDIV_Pos) 134 #define MCLK_CPUDIV_CPUDIV_DIV8 (MCLK_CPUDIV_CPUDIV_DIV8_Val << MCLK_CPUDIV_CPUDIV_Pos) 135 #define MCLK_CPUDIV_CPUDIV_DIV16 (MCLK_CPUDIV_CPUDIV_DIV16_Val << MCLK_CPUDIV_CPUDIV_Pos) 136 #define MCLK_CPUDIV_CPUDIV_DIV32 (MCLK_CPUDIV_CPUDIV_DIV32_Val << MCLK_CPUDIV_CPUDIV_Pos) 137 #define MCLK_CPUDIV_CPUDIV_DIV64 (MCLK_CPUDIV_CPUDIV_DIV64_Val << MCLK_CPUDIV_CPUDIV_Pos) 138 #define MCLK_CPUDIV_CPUDIV_DIV128 (MCLK_CPUDIV_CPUDIV_DIV128_Val << MCLK_CPUDIV_CPUDIV_Pos) 139 #define MCLK_CPUDIV_MASK _U_(0xFF) /**< \brief (MCLK_CPUDIV) MASK Register */ 140 141 /* -------- MCLK_LPDIV : (MCLK Offset: 0x05) (R/W 8) Low-Power Clock Division -------- */ 142 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 143 typedef union { 144 struct { 145 uint8_t LPDIV:8; /*!< bit: 0.. 7 Low-Power Clock Division Factor */ 146 } bit; /*!< Structure used for bit access */ 147 uint8_t reg; /*!< Type used for register access */ 148 } MCLK_LPDIV_Type; 149 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 150 151 #define MCLK_LPDIV_OFFSET 0x05 /**< \brief (MCLK_LPDIV offset) Low-Power Clock Division */ 152 #define MCLK_LPDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_LPDIV reset_value) Low-Power Clock Division */ 153 154 #define MCLK_LPDIV_LPDIV_Pos 0 /**< \brief (MCLK_LPDIV) Low-Power Clock Division Factor */ 155 #define MCLK_LPDIV_LPDIV_Msk (_U_(0xFF) << MCLK_LPDIV_LPDIV_Pos) 156 #define MCLK_LPDIV_LPDIV(value) (MCLK_LPDIV_LPDIV_Msk & ((value) << MCLK_LPDIV_LPDIV_Pos)) 157 #define MCLK_LPDIV_LPDIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_LPDIV) Divide by 1 */ 158 #define MCLK_LPDIV_LPDIV_DIV2_Val _U_(0x2) /**< \brief (MCLK_LPDIV) Divide by 2 */ 159 #define MCLK_LPDIV_LPDIV_DIV4_Val _U_(0x4) /**< \brief (MCLK_LPDIV) Divide by 4 */ 160 #define MCLK_LPDIV_LPDIV_DIV8_Val _U_(0x8) /**< \brief (MCLK_LPDIV) Divide by 8 */ 161 #define MCLK_LPDIV_LPDIV_DIV16_Val _U_(0x10) /**< \brief (MCLK_LPDIV) Divide by 16 */ 162 #define MCLK_LPDIV_LPDIV_DIV32_Val _U_(0x20) /**< \brief (MCLK_LPDIV) Divide by 32 */ 163 #define MCLK_LPDIV_LPDIV_DIV64_Val _U_(0x40) /**< \brief (MCLK_LPDIV) Divide by 64 */ 164 #define MCLK_LPDIV_LPDIV_DIV128_Val _U_(0x80) /**< \brief (MCLK_LPDIV) Divide by 128 */ 165 #define MCLK_LPDIV_LPDIV_DIV1 (MCLK_LPDIV_LPDIV_DIV1_Val << MCLK_LPDIV_LPDIV_Pos) 166 #define MCLK_LPDIV_LPDIV_DIV2 (MCLK_LPDIV_LPDIV_DIV2_Val << MCLK_LPDIV_LPDIV_Pos) 167 #define MCLK_LPDIV_LPDIV_DIV4 (MCLK_LPDIV_LPDIV_DIV4_Val << MCLK_LPDIV_LPDIV_Pos) 168 #define MCLK_LPDIV_LPDIV_DIV8 (MCLK_LPDIV_LPDIV_DIV8_Val << MCLK_LPDIV_LPDIV_Pos) 169 #define MCLK_LPDIV_LPDIV_DIV16 (MCLK_LPDIV_LPDIV_DIV16_Val << MCLK_LPDIV_LPDIV_Pos) 170 #define MCLK_LPDIV_LPDIV_DIV32 (MCLK_LPDIV_LPDIV_DIV32_Val << MCLK_LPDIV_LPDIV_Pos) 171 #define MCLK_LPDIV_LPDIV_DIV64 (MCLK_LPDIV_LPDIV_DIV64_Val << MCLK_LPDIV_LPDIV_Pos) 172 #define MCLK_LPDIV_LPDIV_DIV128 (MCLK_LPDIV_LPDIV_DIV128_Val << MCLK_LPDIV_LPDIV_Pos) 173 #define MCLK_LPDIV_MASK _U_(0xFF) /**< \brief (MCLK_LPDIV) MASK Register */ 174 175 /* -------- MCLK_BUPDIV : (MCLK Offset: 0x06) (R/W 8) Backup Clock Division -------- */ 176 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 177 typedef union { 178 struct { 179 uint8_t BUPDIV:8; /*!< bit: 0.. 7 Backup Clock Division Factor */ 180 } bit; /*!< Structure used for bit access */ 181 uint8_t reg; /*!< Type used for register access */ 182 } MCLK_BUPDIV_Type; 183 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 184 185 #define MCLK_BUPDIV_OFFSET 0x06 /**< \brief (MCLK_BUPDIV offset) Backup Clock Division */ 186 #define MCLK_BUPDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_BUPDIV reset_value) Backup Clock Division */ 187 188 #define MCLK_BUPDIV_BUPDIV_Pos 0 /**< \brief (MCLK_BUPDIV) Backup Clock Division Factor */ 189 #define MCLK_BUPDIV_BUPDIV_Msk (_U_(0xFF) << MCLK_BUPDIV_BUPDIV_Pos) 190 #define MCLK_BUPDIV_BUPDIV(value) (MCLK_BUPDIV_BUPDIV_Msk & ((value) << MCLK_BUPDIV_BUPDIV_Pos)) 191 #define MCLK_BUPDIV_BUPDIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_BUPDIV) Divide by 1 */ 192 #define MCLK_BUPDIV_BUPDIV_DIV2_Val _U_(0x2) /**< \brief (MCLK_BUPDIV) Divide by 2 */ 193 #define MCLK_BUPDIV_BUPDIV_DIV4_Val _U_(0x4) /**< \brief (MCLK_BUPDIV) Divide by 4 */ 194 #define MCLK_BUPDIV_BUPDIV_DIV8_Val _U_(0x8) /**< \brief (MCLK_BUPDIV) Divide by 8 */ 195 #define MCLK_BUPDIV_BUPDIV_DIV16_Val _U_(0x10) /**< \brief (MCLK_BUPDIV) Divide by 16 */ 196 #define MCLK_BUPDIV_BUPDIV_DIV32_Val _U_(0x20) /**< \brief (MCLK_BUPDIV) Divide by 32 */ 197 #define MCLK_BUPDIV_BUPDIV_DIV64_Val _U_(0x40) /**< \brief (MCLK_BUPDIV) Divide by 64 */ 198 #define MCLK_BUPDIV_BUPDIV_DIV128_Val _U_(0x80) /**< \brief (MCLK_BUPDIV) Divide by 128 */ 199 #define MCLK_BUPDIV_BUPDIV_DIV1 (MCLK_BUPDIV_BUPDIV_DIV1_Val << MCLK_BUPDIV_BUPDIV_Pos) 200 #define MCLK_BUPDIV_BUPDIV_DIV2 (MCLK_BUPDIV_BUPDIV_DIV2_Val << MCLK_BUPDIV_BUPDIV_Pos) 201 #define MCLK_BUPDIV_BUPDIV_DIV4 (MCLK_BUPDIV_BUPDIV_DIV4_Val << MCLK_BUPDIV_BUPDIV_Pos) 202 #define MCLK_BUPDIV_BUPDIV_DIV8 (MCLK_BUPDIV_BUPDIV_DIV8_Val << MCLK_BUPDIV_BUPDIV_Pos) 203 #define MCLK_BUPDIV_BUPDIV_DIV16 (MCLK_BUPDIV_BUPDIV_DIV16_Val << MCLK_BUPDIV_BUPDIV_Pos) 204 #define MCLK_BUPDIV_BUPDIV_DIV32 (MCLK_BUPDIV_BUPDIV_DIV32_Val << MCLK_BUPDIV_BUPDIV_Pos) 205 #define MCLK_BUPDIV_BUPDIV_DIV64 (MCLK_BUPDIV_BUPDIV_DIV64_Val << MCLK_BUPDIV_BUPDIV_Pos) 206 #define MCLK_BUPDIV_BUPDIV_DIV128 (MCLK_BUPDIV_BUPDIV_DIV128_Val << MCLK_BUPDIV_BUPDIV_Pos) 207 #define MCLK_BUPDIV_MASK _U_(0xFF) /**< \brief (MCLK_BUPDIV) MASK Register */ 208 209 /* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */ 210 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 211 typedef union { 212 struct { 213 uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ 214 uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ 215 uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ 216 uint32_t HPB3_:1; /*!< bit: 3 HPB3 AHB Clock Mask */ 217 uint32_t HPB4_:1; /*!< bit: 4 HPB4 AHB Clock Mask */ 218 uint32_t DSU_:1; /*!< bit: 5 DSU AHB Clock Mask */ 219 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 220 uint32_t NVMCTRL_:1; /*!< bit: 8 NVMCTRL AHB Clock Mask */ 221 uint32_t HSRAM_:1; /*!< bit: 9 HSRAM AHB Clock Mask */ 222 uint32_t LPRAM_:1; /*!< bit: 10 LPRAM AHB Clock Mask */ 223 uint32_t DMAC_:1; /*!< bit: 11 DMAC AHB Clock Mask */ 224 uint32_t :2; /*!< bit: 12..13 Reserved */ 225 uint32_t PAC_:1; /*!< bit: 14 PAC AHB Clock Mask */ 226 uint32_t NVMCTRL_PICACHU_:1; /*!< bit: 15 NVMCTRL_PICACHU AHB Clock Mask */ 227 uint32_t L2HBRIDGES_H_:1; /*!< bit: 16 L2HBRIDGES_H AHB Clock Mask */ 228 uint32_t H2LBRIDGES_H_:1; /*!< bit: 17 H2LBRIDGES_H AHB Clock Mask */ 229 uint32_t HSRAM_AHBSETUPKEEPER_:1; /*!< bit: 18 HSRAM_AHBSETUPKEEPER AHB Clock Mask */ 230 uint32_t HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_:1; /*!< bit: 19 HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE AHB Clock Mask */ 231 uint32_t :12; /*!< bit: 20..31 Reserved */ 232 } bit; /*!< Structure used for bit access */ 233 uint32_t reg; /*!< Type used for register access */ 234 } MCLK_AHBMASK_Type; 235 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 236 237 #define MCLK_AHBMASK_OFFSET 0x10 /**< \brief (MCLK_AHBMASK offset) AHB Mask */ 238 #define MCLK_AHBMASK_RESETVALUE _U_(0x000FFFFF) /**< \brief (MCLK_AHBMASK reset_value) AHB Mask */ 239 240 #define MCLK_AHBMASK_HPB0_Pos 0 /**< \brief (MCLK_AHBMASK) HPB0 AHB Clock Mask */ 241 #define MCLK_AHBMASK_HPB0 (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos) 242 #define MCLK_AHBMASK_HPB1_Pos 1 /**< \brief (MCLK_AHBMASK) HPB1 AHB Clock Mask */ 243 #define MCLK_AHBMASK_HPB1 (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos) 244 #define MCLK_AHBMASK_HPB2_Pos 2 /**< \brief (MCLK_AHBMASK) HPB2 AHB Clock Mask */ 245 #define MCLK_AHBMASK_HPB2 (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos) 246 #define MCLK_AHBMASK_HPB3_Pos 3 /**< \brief (MCLK_AHBMASK) HPB3 AHB Clock Mask */ 247 #define MCLK_AHBMASK_HPB3 (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos) 248 #define MCLK_AHBMASK_HPB4_Pos 4 /**< \brief (MCLK_AHBMASK) HPB4 AHB Clock Mask */ 249 #define MCLK_AHBMASK_HPB4 (_U_(0x1) << MCLK_AHBMASK_HPB4_Pos) 250 #define MCLK_AHBMASK_DSU_Pos 5 /**< \brief (MCLK_AHBMASK) DSU AHB Clock Mask */ 251 #define MCLK_AHBMASK_DSU (_U_(0x1) << MCLK_AHBMASK_DSU_Pos) 252 #define MCLK_AHBMASK_NVMCTRL_Pos 8 /**< \brief (MCLK_AHBMASK) NVMCTRL AHB Clock Mask */ 253 #define MCLK_AHBMASK_NVMCTRL (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos) 254 #define MCLK_AHBMASK_HSRAM_Pos 9 /**< \brief (MCLK_AHBMASK) HSRAM AHB Clock Mask */ 255 #define MCLK_AHBMASK_HSRAM (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos) 256 #define MCLK_AHBMASK_LPRAM_Pos 10 /**< \brief (MCLK_AHBMASK) LPRAM AHB Clock Mask */ 257 #define MCLK_AHBMASK_LPRAM (_U_(0x1) << MCLK_AHBMASK_LPRAM_Pos) 258 #define MCLK_AHBMASK_DMAC_Pos 11 /**< \brief (MCLK_AHBMASK) DMAC AHB Clock Mask */ 259 #define MCLK_AHBMASK_DMAC (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos) 260 #define MCLK_AHBMASK_PAC_Pos 14 /**< \brief (MCLK_AHBMASK) PAC AHB Clock Mask */ 261 #define MCLK_AHBMASK_PAC (_U_(0x1) << MCLK_AHBMASK_PAC_Pos) 262 #define MCLK_AHBMASK_NVMCTRL_PICACHU_Pos 15 /**< \brief (MCLK_AHBMASK) NVMCTRL_PICACHU AHB Clock Mask */ 263 #define MCLK_AHBMASK_NVMCTRL_PICACHU (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos) 264 #define MCLK_AHBMASK_L2HBRIDGES_H_Pos 16 /**< \brief (MCLK_AHBMASK) L2HBRIDGES_H AHB Clock Mask */ 265 #define MCLK_AHBMASK_L2HBRIDGES_H (_U_(0x1) << MCLK_AHBMASK_L2HBRIDGES_H_Pos) 266 #define MCLK_AHBMASK_H2LBRIDGES_H_Pos 17 /**< \brief (MCLK_AHBMASK) H2LBRIDGES_H AHB Clock Mask */ 267 #define MCLK_AHBMASK_H2LBRIDGES_H (_U_(0x1) << MCLK_AHBMASK_H2LBRIDGES_H_Pos) 268 #define MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER_Pos 18 /**< \brief (MCLK_AHBMASK) HSRAM_AHBSETUPKEEPER AHB Clock Mask */ 269 #define MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER (_U_(0x1) << MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER_Pos) 270 #define MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_Pos 19 /**< \brief (MCLK_AHBMASK) HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE AHB Clock Mask */ 271 #define MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE (_U_(0x1) << MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_Pos) 272 #define MCLK_AHBMASK_MASK _U_(0x000FCF3F) /**< \brief (MCLK_AHBMASK) MASK Register */ 273 274 /* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */ 275 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 276 typedef union { 277 struct { 278 uint32_t PM_:1; /*!< bit: 0 PM APB Clock Enable */ 279 uint32_t MCLK_:1; /*!< bit: 1 MCLK APB Clock Enable */ 280 uint32_t RSTC_:1; /*!< bit: 2 RSTC APB Clock Enable */ 281 uint32_t OSCCTRL_:1; /*!< bit: 3 OSCCTRL APB Clock Enable */ 282 uint32_t OSC32KCTRL_:1; /*!< bit: 4 OSC32KCTRL APB Clock Enable */ 283 uint32_t SUPC_:1; /*!< bit: 5 SUPC APB Clock Enable */ 284 uint32_t GCLK_:1; /*!< bit: 6 GCLK APB Clock Enable */ 285 uint32_t WDT_:1; /*!< bit: 7 WDT APB Clock Enable */ 286 uint32_t RTC_:1; /*!< bit: 8 RTC APB Clock Enable */ 287 uint32_t EIC_:1; /*!< bit: 9 EIC APB Clock Enable */ 288 uint32_t PORT_:1; /*!< bit: 10 PORT APB Clock Enable */ 289 uint32_t :21; /*!< bit: 11..31 Reserved */ 290 } bit; /*!< Structure used for bit access */ 291 uint32_t reg; /*!< Type used for register access */ 292 } MCLK_APBAMASK_Type; 293 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 294 295 #define MCLK_APBAMASK_OFFSET 0x14 /**< \brief (MCLK_APBAMASK offset) APBA Mask */ 296 #define MCLK_APBAMASK_RESETVALUE _U_(0x00001FFF) /**< \brief (MCLK_APBAMASK reset_value) APBA Mask */ 297 298 #define MCLK_APBAMASK_PM_Pos 0 /**< \brief (MCLK_APBAMASK) PM APB Clock Enable */ 299 #define MCLK_APBAMASK_PM (_U_(0x1) << MCLK_APBAMASK_PM_Pos) 300 #define MCLK_APBAMASK_MCLK_Pos 1 /**< \brief (MCLK_APBAMASK) MCLK APB Clock Enable */ 301 #define MCLK_APBAMASK_MCLK (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos) 302 #define MCLK_APBAMASK_RSTC_Pos 2 /**< \brief (MCLK_APBAMASK) RSTC APB Clock Enable */ 303 #define MCLK_APBAMASK_RSTC (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos) 304 #define MCLK_APBAMASK_OSCCTRL_Pos 3 /**< \brief (MCLK_APBAMASK) OSCCTRL APB Clock Enable */ 305 #define MCLK_APBAMASK_OSCCTRL (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos) 306 #define MCLK_APBAMASK_OSC32KCTRL_Pos 4 /**< \brief (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable */ 307 #define MCLK_APBAMASK_OSC32KCTRL (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos) 308 #define MCLK_APBAMASK_SUPC_Pos 5 /**< \brief (MCLK_APBAMASK) SUPC APB Clock Enable */ 309 #define MCLK_APBAMASK_SUPC (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos) 310 #define MCLK_APBAMASK_GCLK_Pos 6 /**< \brief (MCLK_APBAMASK) GCLK APB Clock Enable */ 311 #define MCLK_APBAMASK_GCLK (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos) 312 #define MCLK_APBAMASK_WDT_Pos 7 /**< \brief (MCLK_APBAMASK) WDT APB Clock Enable */ 313 #define MCLK_APBAMASK_WDT (_U_(0x1) << MCLK_APBAMASK_WDT_Pos) 314 #define MCLK_APBAMASK_RTC_Pos 8 /**< \brief (MCLK_APBAMASK) RTC APB Clock Enable */ 315 #define MCLK_APBAMASK_RTC (_U_(0x1) << MCLK_APBAMASK_RTC_Pos) 316 #define MCLK_APBAMASK_EIC_Pos 9 /**< \brief (MCLK_APBAMASK) EIC APB Clock Enable */ 317 #define MCLK_APBAMASK_EIC (_U_(0x1) << MCLK_APBAMASK_EIC_Pos) 318 #define MCLK_APBAMASK_PORT_Pos 10 /**< \brief (MCLK_APBAMASK) PORT APB Clock Enable */ 319 #define MCLK_APBAMASK_PORT (_U_(0x1) << MCLK_APBAMASK_PORT_Pos) 320 #define MCLK_APBAMASK_MASK _U_(0x000007FF) /**< \brief (MCLK_APBAMASK) MASK Register */ 321 322 /* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */ 323 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 324 typedef union { 325 struct { 326 uint32_t :1; /*!< bit: 0 Reserved */ 327 uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ 328 uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ 329 uint32_t :29; /*!< bit: 3..31 Reserved */ 330 } bit; /*!< Structure used for bit access */ 331 uint32_t reg; /*!< Type used for register access */ 332 } MCLK_APBBMASK_Type; 333 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 334 335 #define MCLK_APBBMASK_OFFSET 0x18 /**< \brief (MCLK_APBBMASK offset) APBB Mask */ 336 #define MCLK_APBBMASK_RESETVALUE _U_(0x00000017) /**< \brief (MCLK_APBBMASK reset_value) APBB Mask */ 337 338 #define MCLK_APBBMASK_DSU_Pos 1 /**< \brief (MCLK_APBBMASK) DSU APB Clock Enable */ 339 #define MCLK_APBBMASK_DSU (_U_(0x1) << MCLK_APBBMASK_DSU_Pos) 340 #define MCLK_APBBMASK_NVMCTRL_Pos 2 /**< \brief (MCLK_APBBMASK) NVMCTRL APB Clock Enable */ 341 #define MCLK_APBBMASK_NVMCTRL (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos) 342 #define MCLK_APBBMASK_MASK _U_(0x00000006) /**< \brief (MCLK_APBBMASK) MASK Register */ 343 344 /* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */ 345 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 346 typedef union { 347 struct { 348 uint32_t SERCOM0_:1; /*!< bit: 0 SERCOM0 APB Clock Enable */ 349 uint32_t SERCOM1_:1; /*!< bit: 1 SERCOM1 APB Clock Enable */ 350 uint32_t SERCOM2_:1; /*!< bit: 2 SERCOM2 APB Clock Enable */ 351 uint32_t SERCOM3_:1; /*!< bit: 3 SERCOM3 APB Clock Enable */ 352 uint32_t SERCOM4_:1; /*!< bit: 4 SERCOM4 APB Clock Enable */ 353 uint32_t TCC0_:1; /*!< bit: 5 TCC0 APB Clock Enable */ 354 uint32_t TCC1_:1; /*!< bit: 6 TCC1 APB Clock Enable */ 355 uint32_t TCC2_:1; /*!< bit: 7 TCC2 APB Clock Enable */ 356 uint32_t TC0_:1; /*!< bit: 8 TC0 APB Clock Enable */ 357 uint32_t TC1_:1; /*!< bit: 9 TC1 APB Clock Enable */ 358 uint32_t TC2_:1; /*!< bit: 10 TC2 APB Clock Enable */ 359 uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */ 360 uint32_t DAC_:1; /*!< bit: 12 DAC APB Clock Enable */ 361 uint32_t AES_:1; /*!< bit: 13 AES APB Clock Enable */ 362 uint32_t TRNG_:1; /*!< bit: 14 TRNG APB Clock Enable */ 363 uint32_t :17; /*!< bit: 15..31 Reserved */ 364 } bit; /*!< Structure used for bit access */ 365 uint32_t reg; /*!< Type used for register access */ 366 } MCLK_APBCMASK_Type; 367 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 368 369 #define MCLK_APBCMASK_OFFSET 0x1C /**< \brief (MCLK_APBCMASK offset) APBC Mask */ 370 #define MCLK_APBCMASK_RESETVALUE _U_(0x00007FFF) /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */ 371 372 #define MCLK_APBCMASK_SERCOM0_Pos 0 /**< \brief (MCLK_APBCMASK) SERCOM0 APB Clock Enable */ 373 #define MCLK_APBCMASK_SERCOM0 (_U_(0x1) << MCLK_APBCMASK_SERCOM0_Pos) 374 #define MCLK_APBCMASK_SERCOM1_Pos 1 /**< \brief (MCLK_APBCMASK) SERCOM1 APB Clock Enable */ 375 #define MCLK_APBCMASK_SERCOM1 (_U_(0x1) << MCLK_APBCMASK_SERCOM1_Pos) 376 #define MCLK_APBCMASK_SERCOM2_Pos 2 /**< \brief (MCLK_APBCMASK) SERCOM2 APB Clock Enable */ 377 #define MCLK_APBCMASK_SERCOM2 (_U_(0x1) << MCLK_APBCMASK_SERCOM2_Pos) 378 #define MCLK_APBCMASK_SERCOM3_Pos 3 /**< \brief (MCLK_APBCMASK) SERCOM3 APB Clock Enable */ 379 #define MCLK_APBCMASK_SERCOM3 (_U_(0x1) << MCLK_APBCMASK_SERCOM3_Pos) 380 #define MCLK_APBCMASK_SERCOM4_Pos 4 /**< \brief (MCLK_APBCMASK) SERCOM4 APB Clock Enable */ 381 #define MCLK_APBCMASK_SERCOM4 (_U_(0x1) << MCLK_APBCMASK_SERCOM4_Pos) 382 #define MCLK_APBCMASK_TCC0_Pos 5 /**< \brief (MCLK_APBCMASK) TCC0 APB Clock Enable */ 383 #define MCLK_APBCMASK_TCC0 (_U_(0x1) << MCLK_APBCMASK_TCC0_Pos) 384 #define MCLK_APBCMASK_TCC1_Pos 6 /**< \brief (MCLK_APBCMASK) TCC1 APB Clock Enable */ 385 #define MCLK_APBCMASK_TCC1 (_U_(0x1) << MCLK_APBCMASK_TCC1_Pos) 386 #define MCLK_APBCMASK_TCC2_Pos 7 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */ 387 #define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos) 388 #define MCLK_APBCMASK_TC0_Pos 8 /**< \brief (MCLK_APBCMASK) TC0 APB Clock Enable */ 389 #define MCLK_APBCMASK_TC0 (_U_(0x1) << MCLK_APBCMASK_TC0_Pos) 390 #define MCLK_APBCMASK_TC1_Pos 9 /**< \brief (MCLK_APBCMASK) TC1 APB Clock Enable */ 391 #define MCLK_APBCMASK_TC1 (_U_(0x1) << MCLK_APBCMASK_TC1_Pos) 392 #define MCLK_APBCMASK_TC2_Pos 10 /**< \brief (MCLK_APBCMASK) TC2 APB Clock Enable */ 393 #define MCLK_APBCMASK_TC2 (_U_(0x1) << MCLK_APBCMASK_TC2_Pos) 394 #define MCLK_APBCMASK_TC3_Pos 11 /**< \brief (MCLK_APBCMASK) TC3 APB Clock Enable */ 395 #define MCLK_APBCMASK_TC3 (_U_(0x1) << MCLK_APBCMASK_TC3_Pos) 396 #define MCLK_APBCMASK_DAC_Pos 12 /**< \brief (MCLK_APBCMASK) DAC APB Clock Enable */ 397 #define MCLK_APBCMASK_DAC (_U_(0x1) << MCLK_APBCMASK_DAC_Pos) 398 #define MCLK_APBCMASK_AES_Pos 13 /**< \brief (MCLK_APBCMASK) AES APB Clock Enable */ 399 #define MCLK_APBCMASK_AES (_U_(0x1) << MCLK_APBCMASK_AES_Pos) 400 #define MCLK_APBCMASK_TRNG_Pos 14 /**< \brief (MCLK_APBCMASK) TRNG APB Clock Enable */ 401 #define MCLK_APBCMASK_TRNG (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos) 402 #define MCLK_APBCMASK_MASK _U_(0x00007FFF) /**< \brief (MCLK_APBCMASK) MASK Register */ 403 404 /* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */ 405 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 406 typedef union { 407 struct { 408 uint32_t EVSYS_:1; /*!< bit: 0 EVSYS APB Clock Enable */ 409 uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Clock Enable */ 410 uint32_t TC4_:1; /*!< bit: 2 TC4 APB Clock Enable */ 411 uint32_t ADC_:1; /*!< bit: 3 ADC APB Clock Enable */ 412 uint32_t AC_:1; /*!< bit: 4 AC APB Clock Enable */ 413 uint32_t PTC_:1; /*!< bit: 5 PTC APB Clock Enable */ 414 uint32_t :1; /*!< bit: 6 Reserved */ 415 uint32_t CCL_:1; /*!< bit: 7 CCL APB Clock Enable */ 416 uint32_t :24; /*!< bit: 8..31 Reserved */ 417 } bit; /*!< Structure used for bit access */ 418 uint32_t reg; /*!< Type used for register access */ 419 } MCLK_APBDMASK_Type; 420 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 421 422 #define MCLK_APBDMASK_OFFSET 0x20 /**< \brief (MCLK_APBDMASK offset) APBD Mask */ 423 #define MCLK_APBDMASK_RESETVALUE _U_(0x000000FF) /**< \brief (MCLK_APBDMASK reset_value) APBD Mask */ 424 425 #define MCLK_APBDMASK_EVSYS_Pos 0 /**< \brief (MCLK_APBDMASK) EVSYS APB Clock Enable */ 426 #define MCLK_APBDMASK_EVSYS (_U_(0x1) << MCLK_APBDMASK_EVSYS_Pos) 427 #define MCLK_APBDMASK_SERCOM5_Pos 1 /**< \brief (MCLK_APBDMASK) SERCOM5 APB Clock Enable */ 428 #define MCLK_APBDMASK_SERCOM5 (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos) 429 #define MCLK_APBDMASK_TC4_Pos 2 /**< \brief (MCLK_APBDMASK) TC4 APB Clock Enable */ 430 #define MCLK_APBDMASK_TC4 (_U_(0x1) << MCLK_APBDMASK_TC4_Pos) 431 #define MCLK_APBDMASK_ADC_Pos 3 /**< \brief (MCLK_APBDMASK) ADC APB Clock Enable */ 432 #define MCLK_APBDMASK_ADC (_U_(0x1) << MCLK_APBDMASK_ADC_Pos) 433 #define MCLK_APBDMASK_AC_Pos 4 /**< \brief (MCLK_APBDMASK) AC APB Clock Enable */ 434 #define MCLK_APBDMASK_AC (_U_(0x1) << MCLK_APBDMASK_AC_Pos) 435 #define MCLK_APBDMASK_PTC_Pos 5 /**< \brief (MCLK_APBDMASK) PTC APB Clock Enable */ 436 #define MCLK_APBDMASK_PTC (_U_(0x1) << MCLK_APBDMASK_PTC_Pos) 437 #define MCLK_APBDMASK_CCL_Pos 7 /**< \brief (MCLK_APBDMASK) CCL APB Clock Enable */ 438 #define MCLK_APBDMASK_CCL (_U_(0x1) << MCLK_APBDMASK_CCL_Pos) 439 #define MCLK_APBDMASK_MASK _U_(0x000000BF) /**< \brief (MCLK_APBDMASK) MASK Register */ 440 441 /* -------- MCLK_APBEMASK : (MCLK Offset: 0x24) (R/W 32) APBE Mask -------- */ 442 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 443 typedef union { 444 struct { 445 uint32_t PAC_:1; /*!< bit: 0 PAC APB Clock Enable */ 446 uint32_t :31; /*!< bit: 1..31 Reserved */ 447 } bit; /*!< Structure used for bit access */ 448 uint32_t reg; /*!< Type used for register access */ 449 } MCLK_APBEMASK_Type; 450 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 451 452 #define MCLK_APBEMASK_OFFSET 0x24 /**< \brief (MCLK_APBEMASK offset) APBE Mask */ 453 #define MCLK_APBEMASK_RESETVALUE _U_(0x0000000D) /**< \brief (MCLK_APBEMASK reset_value) APBE Mask */ 454 455 #define MCLK_APBEMASK_PAC_Pos 0 /**< \brief (MCLK_APBEMASK) PAC APB Clock Enable */ 456 #define MCLK_APBEMASK_PAC (_U_(0x1) << MCLK_APBEMASK_PAC_Pos) 457 #define MCLK_APBEMASK_MASK _U_(0x00000001) /**< \brief (MCLK_APBEMASK) MASK Register */ 458 459 /** \brief MCLK hardware registers */ 460 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 461 typedef struct { 462 __IO MCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 463 __IO MCLK_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x01 (R/W 8) Interrupt Enable Clear */ 464 __IO MCLK_INTENSET_Type INTENSET; /**< \brief Offset: 0x02 (R/W 8) Interrupt Enable Set */ 465 __IO MCLK_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear */ 466 __IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x04 (R/W 8) CPU Clock Division */ 467 __IO MCLK_LPDIV_Type LPDIV; /**< \brief Offset: 0x05 (R/W 8) Low-Power Clock Division */ 468 __IO MCLK_BUPDIV_Type BUPDIV; /**< \brief Offset: 0x06 (R/W 8) Backup Clock Division */ 469 RoReg8 Reserved1[0x9]; 470 __IO MCLK_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x10 (R/W 32) AHB Mask */ 471 __IO MCLK_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x14 (R/W 32) APBA Mask */ 472 __IO MCLK_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x18 (R/W 32) APBB Mask */ 473 __IO MCLK_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x1C (R/W 32) APBC Mask */ 474 __IO MCLK_APBDMASK_Type APBDMASK; /**< \brief Offset: 0x20 (R/W 32) APBD Mask */ 475 __IO MCLK_APBEMASK_Type APBEMASK; /**< \brief Offset: 0x24 (R/W 32) APBE Mask */ 476 } Mclk; 477 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 478 479 /*@}*/ 480 481 #endif /* _SAMR35_MCLK_COMPONENT_ */ 482
