1 /** 2 * \file 3 * 4 * \brief Instance description for PORT 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR34_PORT_INSTANCE_ 31 #define _SAMR34_PORT_INSTANCE_ 32 33 /* ========== Register definition for PORT peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_PORT_DIR0 (0x40002800) /**< \brief (PORT) Data Direction 0 */ 36 #define REG_PORT_DIRCLR0 (0x40002804) /**< \brief (PORT) Data Direction Clear 0 */ 37 #define REG_PORT_DIRSET0 (0x40002808) /**< \brief (PORT) Data Direction Set 0 */ 38 #define REG_PORT_DIRTGL0 (0x4000280C) /**< \brief (PORT) Data Direction Toggle 0 */ 39 #define REG_PORT_OUT0 (0x40002810) /**< \brief (PORT) Data Output Value 0 */ 40 #define REG_PORT_OUTCLR0 (0x40002814) /**< \brief (PORT) Data Output Value Clear 0 */ 41 #define REG_PORT_OUTSET0 (0x40002818) /**< \brief (PORT) Data Output Value Set 0 */ 42 #define REG_PORT_OUTTGL0 (0x4000281C) /**< \brief (PORT) Data Output Value Toggle 0 */ 43 #define REG_PORT_IN0 (0x40002820) /**< \brief (PORT) Data Input Value 0 */ 44 #define REG_PORT_CTRL0 (0x40002824) /**< \brief (PORT) Control 0 */ 45 #define REG_PORT_WRCONFIG0 (0x40002828) /**< \brief (PORT) Write Configuration 0 */ 46 #define REG_PORT_EVCTRL0 (0x4000282C) /**< \brief (PORT) Event Input Control 0 */ 47 #define REG_PORT_PMUX0 (0x40002830) /**< \brief (PORT) Peripheral Multiplexing 0 */ 48 #define REG_PORT_PINCFG0 (0x40002840) /**< \brief (PORT) Pin Configuration 0 */ 49 #define REG_PORT_DIR1 (0x40002880) /**< \brief (PORT) Data Direction 1 */ 50 #define REG_PORT_DIRCLR1 (0x40002884) /**< \brief (PORT) Data Direction Clear 1 */ 51 #define REG_PORT_DIRSET1 (0x40002888) /**< \brief (PORT) Data Direction Set 1 */ 52 #define REG_PORT_DIRTGL1 (0x4000288C) /**< \brief (PORT) Data Direction Toggle 1 */ 53 #define REG_PORT_OUT1 (0x40002890) /**< \brief (PORT) Data Output Value 1 */ 54 #define REG_PORT_OUTCLR1 (0x40002894) /**< \brief (PORT) Data Output Value Clear 1 */ 55 #define REG_PORT_OUTSET1 (0x40002898) /**< \brief (PORT) Data Output Value Set 1 */ 56 #define REG_PORT_OUTTGL1 (0x4000289C) /**< \brief (PORT) Data Output Value Toggle 1 */ 57 #define REG_PORT_IN1 (0x400028A0) /**< \brief (PORT) Data Input Value 1 */ 58 #define REG_PORT_CTRL1 (0x400028A4) /**< \brief (PORT) Control 1 */ 59 #define REG_PORT_WRCONFIG1 (0x400028A8) /**< \brief (PORT) Write Configuration 1 */ 60 #define REG_PORT_EVCTRL1 (0x400028AC) /**< \brief (PORT) Event Input Control 1 */ 61 #define REG_PORT_PMUX1 (0x400028B0) /**< \brief (PORT) Peripheral Multiplexing 1 */ 62 #define REG_PORT_PINCFG1 (0x400028C0) /**< \brief (PORT) Pin Configuration 1 */ 63 #define REG_PORT_DIR2 (0x40002900) /**< \brief (PORT) Data Direction 2 */ 64 #define REG_PORT_DIRCLR2 (0x40002904) /**< \brief (PORT) Data Direction Clear 2 */ 65 #define REG_PORT_DIRSET2 (0x40002908) /**< \brief (PORT) Data Direction Set 2 */ 66 #define REG_PORT_DIRTGL2 (0x4000290C) /**< \brief (PORT) Data Direction Toggle 2 */ 67 #define REG_PORT_OUT2 (0x40002910) /**< \brief (PORT) Data Output Value 2 */ 68 #define REG_PORT_OUTCLR2 (0x40002914) /**< \brief (PORT) Data Output Value Clear 2 */ 69 #define REG_PORT_OUTSET2 (0x40002918) /**< \brief (PORT) Data Output Value Set 2 */ 70 #define REG_PORT_OUTTGL2 (0x4000291C) /**< \brief (PORT) Data Output Value Toggle 2 */ 71 #define REG_PORT_IN2 (0x40002920) /**< \brief (PORT) Data Input Value 2 */ 72 #define REG_PORT_CTRL2 (0x40002924) /**< \brief (PORT) Control 2 */ 73 #define REG_PORT_WRCONFIG2 (0x40002928) /**< \brief (PORT) Write Configuration 2 */ 74 #define REG_PORT_EVCTRL2 (0x4000292C) /**< \brief (PORT) Event Input Control 2 */ 75 #define REG_PORT_PMUX2 (0x40002930) /**< \brief (PORT) Peripheral Multiplexing 2 */ 76 #define REG_PORT_PINCFG2 (0x40002940) /**< \brief (PORT) Pin Configuration 2 */ 77 #else 78 #define REG_PORT_DIR0 (*(RwReg *)0x40002800UL) /**< \brief (PORT) Data Direction 0 */ 79 #define REG_PORT_DIRCLR0 (*(RwReg *)0x40002804UL) /**< \brief (PORT) Data Direction Clear 0 */ 80 #define REG_PORT_DIRSET0 (*(RwReg *)0x40002808UL) /**< \brief (PORT) Data Direction Set 0 */ 81 #define REG_PORT_DIRTGL0 (*(RwReg *)0x4000280CUL) /**< \brief (PORT) Data Direction Toggle 0 */ 82 #define REG_PORT_OUT0 (*(RwReg *)0x40002810UL) /**< \brief (PORT) Data Output Value 0 */ 83 #define REG_PORT_OUTCLR0 (*(RwReg *)0x40002814UL) /**< \brief (PORT) Data Output Value Clear 0 */ 84 #define REG_PORT_OUTSET0 (*(RwReg *)0x40002818UL) /**< \brief (PORT) Data Output Value Set 0 */ 85 #define REG_PORT_OUTTGL0 (*(RwReg *)0x4000281CUL) /**< \brief (PORT) Data Output Value Toggle 0 */ 86 #define REG_PORT_IN0 (*(RoReg *)0x40002820UL) /**< \brief (PORT) Data Input Value 0 */ 87 #define REG_PORT_CTRL0 (*(RwReg *)0x40002824UL) /**< \brief (PORT) Control 0 */ 88 #define REG_PORT_WRCONFIG0 (*(WoReg *)0x40002828UL) /**< \brief (PORT) Write Configuration 0 */ 89 #define REG_PORT_EVCTRL0 (*(RwReg *)0x4000282CUL) /**< \brief (PORT) Event Input Control 0 */ 90 #define REG_PORT_PMUX0 (*(RwReg8 *)0x40002830UL) /**< \brief (PORT) Peripheral Multiplexing 0 */ 91 #define REG_PORT_PINCFG0 (*(RwReg8 *)0x40002840UL) /**< \brief (PORT) Pin Configuration 0 */ 92 #define REG_PORT_DIR1 (*(RwReg *)0x40002880UL) /**< \brief (PORT) Data Direction 1 */ 93 #define REG_PORT_DIRCLR1 (*(RwReg *)0x40002884UL) /**< \brief (PORT) Data Direction Clear 1 */ 94 #define REG_PORT_DIRSET1 (*(RwReg *)0x40002888UL) /**< \brief (PORT) Data Direction Set 1 */ 95 #define REG_PORT_DIRTGL1 (*(RwReg *)0x4000288CUL) /**< \brief (PORT) Data Direction Toggle 1 */ 96 #define REG_PORT_OUT1 (*(RwReg *)0x40002890UL) /**< \brief (PORT) Data Output Value 1 */ 97 #define REG_PORT_OUTCLR1 (*(RwReg *)0x40002894UL) /**< \brief (PORT) Data Output Value Clear 1 */ 98 #define REG_PORT_OUTSET1 (*(RwReg *)0x40002898UL) /**< \brief (PORT) Data Output Value Set 1 */ 99 #define REG_PORT_OUTTGL1 (*(RwReg *)0x4000289CUL) /**< \brief (PORT) Data Output Value Toggle 1 */ 100 #define REG_PORT_IN1 (*(RoReg *)0x400028A0UL) /**< \brief (PORT) Data Input Value 1 */ 101 #define REG_PORT_CTRL1 (*(RwReg *)0x400028A4UL) /**< \brief (PORT) Control 1 */ 102 #define REG_PORT_WRCONFIG1 (*(WoReg *)0x400028A8UL) /**< \brief (PORT) Write Configuration 1 */ 103 #define REG_PORT_EVCTRL1 (*(RwReg *)0x400028ACUL) /**< \brief (PORT) Event Input Control 1 */ 104 #define REG_PORT_PMUX1 (*(RwReg8 *)0x400028B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */ 105 #define REG_PORT_PINCFG1 (*(RwReg8 *)0x400028C0UL) /**< \brief (PORT) Pin Configuration 1 */ 106 #define REG_PORT_DIR2 (*(RwReg *)0x40002900UL) /**< \brief (PORT) Data Direction 2 */ 107 #define REG_PORT_DIRCLR2 (*(RwReg *)0x40002904UL) /**< \brief (PORT) Data Direction Clear 2 */ 108 #define REG_PORT_DIRSET2 (*(RwReg *)0x40002908UL) /**< \brief (PORT) Data Direction Set 2 */ 109 #define REG_PORT_DIRTGL2 (*(RwReg *)0x4000290CUL) /**< \brief (PORT) Data Direction Toggle 2 */ 110 #define REG_PORT_OUT2 (*(RwReg *)0x40002910UL) /**< \brief (PORT) Data Output Value 2 */ 111 #define REG_PORT_OUTCLR2 (*(RwReg *)0x40002914UL) /**< \brief (PORT) Data Output Value Clear 2 */ 112 #define REG_PORT_OUTSET2 (*(RwReg *)0x40002918UL) /**< \brief (PORT) Data Output Value Set 2 */ 113 #define REG_PORT_OUTTGL2 (*(RwReg *)0x4000291CUL) /**< \brief (PORT) Data Output Value Toggle 2 */ 114 #define REG_PORT_IN2 (*(RoReg *)0x40002920UL) /**< \brief (PORT) Data Input Value 2 */ 115 #define REG_PORT_CTRL2 (*(RwReg *)0x40002924UL) /**< \brief (PORT) Control 2 */ 116 #define REG_PORT_WRCONFIG2 (*(WoReg *)0x40002928UL) /**< \brief (PORT) Write Configuration 2 */ 117 #define REG_PORT_EVCTRL2 (*(RwReg *)0x4000292CUL) /**< \brief (PORT) Event Input Control 2 */ 118 #define REG_PORT_PMUX2 (*(RwReg8 *)0x40002930UL) /**< \brief (PORT) Peripheral Multiplexing 2 */ 119 #define REG_PORT_PINCFG2 (*(RwReg8 *)0x40002940UL) /**< \brief (PORT) Pin Configuration 2 */ 120 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 121 122 /* ========== Instance parameters for PORT peripheral ========== */ 123 #define PORT_BITS 84 124 #define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } 125 #define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } 126 #define PORT_DRVSTR 1 // DRVSTR supported? 127 #define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } 128 #define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000D0000 } 129 #define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC0C3FFFF, 0x00000000 } 130 #define PORT_EV_NUM 4 131 #define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } 132 #define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } 133 #define PORT_ODRAIN 0 // ODRAIN supported? 134 #define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } 135 #define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } 136 #define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } 137 #define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } 138 #define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } 139 #define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x000D0000 } 140 #define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x00000000 } 141 #define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } 142 #define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } 143 #define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x000D0000 } 144 #define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } 145 #define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } 146 #define PORT_PMUXBIT3_IMPLEMENTED { 0xC3CF0FF0, 0x00C3CFC7, 0x00000000 } 147 #define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } 148 #define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } 149 #define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } 150 #define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } 151 #define PORT_SLEWLIM 0 // SLEWLIM supported? 152 #define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } 153 #define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } 154 155 #endif /* _SAMR34_PORT_INSTANCE_ */ 156
