1 /** 2 * \file 3 * 4 * \brief Component description for RSTC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR34_RSTC_COMPONENT_ 31 #define _SAMR34_RSTC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR RSTC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMR34_RSTC Reset Controller */ 37 /*@{*/ 38 39 #define RSTC_U2239 40 #define REV_RSTC 0x110 41 42 /* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/ 8) Reset Cause -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t POR:1; /*!< bit: 0 Power On Reset */ 47 uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */ 48 uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */ 49 uint8_t :1; /*!< bit: 3 Reserved */ 50 uint8_t EXT:1; /*!< bit: 4 External Reset */ 51 uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ 52 uint8_t SYST:1; /*!< bit: 6 System Reset Request */ 53 uint8_t BACKUP:1; /*!< bit: 7 Backup Reset */ 54 } bit; /*!< Structure used for bit access */ 55 uint8_t reg; /*!< Type used for register access */ 56 } RSTC_RCAUSE_Type; 57 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 58 59 #define RSTC_RCAUSE_OFFSET 0x00 /**< \brief (RSTC_RCAUSE offset) Reset Cause */ 60 61 #define RSTC_RCAUSE_POR_Pos 0 /**< \brief (RSTC_RCAUSE) Power On Reset */ 62 #define RSTC_RCAUSE_POR (_U_(0x1) << RSTC_RCAUSE_POR_Pos) 63 #define RSTC_RCAUSE_BOD12_Pos 1 /**< \brief (RSTC_RCAUSE) Brown Out 12 Detector Reset */ 64 #define RSTC_RCAUSE_BOD12 (_U_(0x1) << RSTC_RCAUSE_BOD12_Pos) 65 #define RSTC_RCAUSE_BOD33_Pos 2 /**< \brief (RSTC_RCAUSE) Brown Out 33 Detector Reset */ 66 #define RSTC_RCAUSE_BOD33 (_U_(0x1) << RSTC_RCAUSE_BOD33_Pos) 67 #define RSTC_RCAUSE_EXT_Pos 4 /**< \brief (RSTC_RCAUSE) External Reset */ 68 #define RSTC_RCAUSE_EXT (_U_(0x1) << RSTC_RCAUSE_EXT_Pos) 69 #define RSTC_RCAUSE_WDT_Pos 5 /**< \brief (RSTC_RCAUSE) Watchdog Reset */ 70 #define RSTC_RCAUSE_WDT (_U_(0x1) << RSTC_RCAUSE_WDT_Pos) 71 #define RSTC_RCAUSE_SYST_Pos 6 /**< \brief (RSTC_RCAUSE) System Reset Request */ 72 #define RSTC_RCAUSE_SYST (_U_(0x1) << RSTC_RCAUSE_SYST_Pos) 73 #define RSTC_RCAUSE_BACKUP_Pos 7 /**< \brief (RSTC_RCAUSE) Backup Reset */ 74 #define RSTC_RCAUSE_BACKUP (_U_(0x1) << RSTC_RCAUSE_BACKUP_Pos) 75 #define RSTC_RCAUSE_MASK _U_(0xF7) /**< \brief (RSTC_RCAUSE) MASK Register */ 76 77 /* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) (R/ 8) Backup Exit Source -------- */ 78 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 79 typedef union { 80 struct { 81 uint8_t EXTWAKE:1; /*!< bit: 0 External Wakeup */ 82 uint8_t RTC:1; /*!< bit: 1 Real Timer Counter Interrupt */ 83 uint8_t BBPS:1; /*!< bit: 2 Battery Backup Power Switch */ 84 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 85 } bit; /*!< Structure used for bit access */ 86 uint8_t reg; /*!< Type used for register access */ 87 } RSTC_BKUPEXIT_Type; 88 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 89 90 #define RSTC_BKUPEXIT_OFFSET 0x02 /**< \brief (RSTC_BKUPEXIT offset) Backup Exit Source */ 91 92 #define RSTC_BKUPEXIT_EXTWAKE_Pos 0 /**< \brief (RSTC_BKUPEXIT) External Wakeup */ 93 #define RSTC_BKUPEXIT_EXTWAKE (_U_(0x1) << RSTC_BKUPEXIT_EXTWAKE_Pos) 94 #define RSTC_BKUPEXIT_RTC_Pos 1 /**< \brief (RSTC_BKUPEXIT) Real Timer Counter Interrupt */ 95 #define RSTC_BKUPEXIT_RTC (_U_(0x1) << RSTC_BKUPEXIT_RTC_Pos) 96 #define RSTC_BKUPEXIT_BBPS_Pos 2 /**< \brief (RSTC_BKUPEXIT) Battery Backup Power Switch */ 97 #define RSTC_BKUPEXIT_BBPS (_U_(0x1) << RSTC_BKUPEXIT_BBPS_Pos) 98 #define RSTC_BKUPEXIT_MASK _U_(0x07) /**< \brief (RSTC_BKUPEXIT) MASK Register */ 99 100 /* -------- RSTC_WKDBCONF : (RSTC Offset: 0x04) (R/W 8) Wakeup Debounce Configuration -------- */ 101 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 102 typedef union { 103 struct { 104 uint8_t WKDBCNT:5; /*!< bit: 0.. 4 Wakeup Debounce Counter */ 105 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 106 } bit; /*!< Structure used for bit access */ 107 uint8_t reg; /*!< Type used for register access */ 108 } RSTC_WKDBCONF_Type; 109 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 110 111 #define RSTC_WKDBCONF_OFFSET 0x04 /**< \brief (RSTC_WKDBCONF offset) Wakeup Debounce Configuration */ 112 #define RSTC_WKDBCONF_RESETVALUE _U_(0x00) /**< \brief (RSTC_WKDBCONF reset_value) Wakeup Debounce Configuration */ 113 114 #define RSTC_WKDBCONF_WKDBCNT_Pos 0 /**< \brief (RSTC_WKDBCONF) Wakeup Debounce Counter */ 115 #define RSTC_WKDBCONF_WKDBCNT_Msk (_U_(0x1F) << RSTC_WKDBCONF_WKDBCNT_Pos) 116 #define RSTC_WKDBCONF_WKDBCNT(value) (RSTC_WKDBCONF_WKDBCNT_Msk & ((value) << RSTC_WKDBCONF_WKDBCNT_Pos)) 117 #define RSTC_WKDBCONF_WKDBCNT_OFF_Val _U_(0x0) /**< \brief (RSTC_WKDBCONF) No debouncing.Input pin is low or high level sensitive depending on its WKPOLx bit. */ 118 #define RSTC_WKDBCONF_WKDBCNT_2CK32_Val _U_(0x1) /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least two 32kHz clock period. */ 119 #define RSTC_WKDBCONF_WKDBCNT_3CK32_Val _U_(0x2) /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least three 32kHz clock period. */ 120 #define RSTC_WKDBCONF_WKDBCNT_32CK32_Val _U_(0x3) /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 32 32kHz clock period. */ 121 #define RSTC_WKDBCONF_WKDBCNT_512CK32_Val _U_(0x4) /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 512 32kHz clock period. */ 122 #define RSTC_WKDBCONF_WKDBCNT_4096CK32_Val _U_(0x5) /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 4096 32kHz clock period. */ 123 #define RSTC_WKDBCONF_WKDBCNT_32768CK32_Val _U_(0x6) /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 32768 32kHz clock period. */ 124 #define RSTC_WKDBCONF_WKDBCNT_OFF (RSTC_WKDBCONF_WKDBCNT_OFF_Val << RSTC_WKDBCONF_WKDBCNT_Pos) 125 #define RSTC_WKDBCONF_WKDBCNT_2CK32 (RSTC_WKDBCONF_WKDBCNT_2CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) 126 #define RSTC_WKDBCONF_WKDBCNT_3CK32 (RSTC_WKDBCONF_WKDBCNT_3CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) 127 #define RSTC_WKDBCONF_WKDBCNT_32CK32 (RSTC_WKDBCONF_WKDBCNT_32CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) 128 #define RSTC_WKDBCONF_WKDBCNT_512CK32 (RSTC_WKDBCONF_WKDBCNT_512CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) 129 #define RSTC_WKDBCONF_WKDBCNT_4096CK32 (RSTC_WKDBCONF_WKDBCNT_4096CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) 130 #define RSTC_WKDBCONF_WKDBCNT_32768CK32 (RSTC_WKDBCONF_WKDBCNT_32768CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) 131 #define RSTC_WKDBCONF_MASK _U_(0x1F) /**< \brief (RSTC_WKDBCONF) MASK Register */ 132 133 /* -------- RSTC_WKPOL : (RSTC Offset: 0x08) (R/W 16) Wakeup Polarity -------- */ 134 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 135 typedef union { 136 struct { 137 uint16_t WKPOL:8; /*!< bit: 0.. 7 Wakeup Polarity */ 138 uint16_t :8; /*!< bit: 8..15 Reserved */ 139 } bit; /*!< Structure used for bit access */ 140 uint16_t reg; /*!< Type used for register access */ 141 } RSTC_WKPOL_Type; 142 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 143 144 #define RSTC_WKPOL_OFFSET 0x08 /**< \brief (RSTC_WKPOL offset) Wakeup Polarity */ 145 #define RSTC_WKPOL_RESETVALUE _U_(0x0000) /**< \brief (RSTC_WKPOL reset_value) Wakeup Polarity */ 146 147 #define RSTC_WKPOL_WKPOL_Pos 0 /**< \brief (RSTC_WKPOL) Wakeup Polarity */ 148 #define RSTC_WKPOL_WKPOL_Msk (_U_(0xFF) << RSTC_WKPOL_WKPOL_Pos) 149 #define RSTC_WKPOL_WKPOL(value) (RSTC_WKPOL_WKPOL_Msk & ((value) << RSTC_WKPOL_WKPOL_Pos)) 150 #define RSTC_WKPOL_MASK _U_(0x00FF) /**< \brief (RSTC_WKPOL) MASK Register */ 151 152 /* -------- RSTC_WKEN : (RSTC Offset: 0x0C) (R/W 16) Wakeup Enable -------- */ 153 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 154 typedef union { 155 struct { 156 uint16_t WKEN:8; /*!< bit: 0.. 7 Wakeup Enable */ 157 uint16_t :8; /*!< bit: 8..15 Reserved */ 158 } bit; /*!< Structure used for bit access */ 159 uint16_t reg; /*!< Type used for register access */ 160 } RSTC_WKEN_Type; 161 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 162 163 #define RSTC_WKEN_OFFSET 0x0C /**< \brief (RSTC_WKEN offset) Wakeup Enable */ 164 #define RSTC_WKEN_RESETVALUE _U_(0x0000) /**< \brief (RSTC_WKEN reset_value) Wakeup Enable */ 165 166 #define RSTC_WKEN_WKEN_Pos 0 /**< \brief (RSTC_WKEN) Wakeup Enable */ 167 #define RSTC_WKEN_WKEN_Msk (_U_(0xFF) << RSTC_WKEN_WKEN_Pos) 168 #define RSTC_WKEN_WKEN(value) (RSTC_WKEN_WKEN_Msk & ((value) << RSTC_WKEN_WKEN_Pos)) 169 #define RSTC_WKEN_MASK _U_(0x00FF) /**< \brief (RSTC_WKEN) MASK Register */ 170 171 /* -------- RSTC_WKCAUSE : (RSTC Offset: 0x10) (R/W 16) Wakeup Cause -------- */ 172 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 173 typedef union { 174 struct { 175 uint16_t WKCAUSE:16; /*!< bit: 0..15 Wakeup Cause */ 176 } bit; /*!< Structure used for bit access */ 177 uint16_t reg; /*!< Type used for register access */ 178 } RSTC_WKCAUSE_Type; 179 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 180 181 #define RSTC_WKCAUSE_OFFSET 0x10 /**< \brief (RSTC_WKCAUSE offset) Wakeup Cause */ 182 #define RSTC_WKCAUSE_RESETVALUE _U_(0x0000) /**< \brief (RSTC_WKCAUSE reset_value) Wakeup Cause */ 183 184 #define RSTC_WKCAUSE_WKCAUSE_Pos 0 /**< \brief (RSTC_WKCAUSE) Wakeup Cause */ 185 #define RSTC_WKCAUSE_WKCAUSE_Msk (_U_(0xFFFF) << RSTC_WKCAUSE_WKCAUSE_Pos) 186 #define RSTC_WKCAUSE_WKCAUSE(value) (RSTC_WKCAUSE_WKCAUSE_Msk & ((value) << RSTC_WKCAUSE_WKCAUSE_Pos)) 187 #define RSTC_WKCAUSE_MASK _U_(0xFFFF) /**< \brief (RSTC_WKCAUSE) MASK Register */ 188 189 /** \brief RSTC hardware registers */ 190 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 191 typedef struct { 192 __I RSTC_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x00 (R/ 8) Reset Cause */ 193 RoReg8 Reserved1[0x1]; 194 __I RSTC_BKUPEXIT_Type BKUPEXIT; /**< \brief Offset: 0x02 (R/ 8) Backup Exit Source */ 195 RoReg8 Reserved2[0x1]; 196 __IO RSTC_WKDBCONF_Type WKDBCONF; /**< \brief Offset: 0x04 (R/W 8) Wakeup Debounce Configuration */ 197 RoReg8 Reserved3[0x3]; 198 __IO RSTC_WKPOL_Type WKPOL; /**< \brief Offset: 0x08 (R/W 16) Wakeup Polarity */ 199 RoReg8 Reserved4[0x2]; 200 __IO RSTC_WKEN_Type WKEN; /**< \brief Offset: 0x0C (R/W 16) Wakeup Enable */ 201 RoReg8 Reserved5[0x2]; 202 __IO RSTC_WKCAUSE_Type WKCAUSE; /**< \brief Offset: 0x10 (R/W 16) Wakeup Cause */ 203 } Rstc; 204 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 205 206 /*@}*/ 207 208 #endif /* _SAMR34_RSTC_COMPONENT_ */ 209
