1 /** 2 * \file 3 * 4 * \brief Component description for PAC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR34_PAC_COMPONENT_ 31 #define _SAMR34_PAC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR PAC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMR34_PAC Peripheral Access Controller */ 37 /*@{*/ 38 39 #define PAC_U2120 40 #define REV_PAC 0x110 41 42 /* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t PERID:16; /*!< bit: 0..15 Peripheral identifier */ 47 uint32_t KEY:8; /*!< bit: 16..23 Peripheral access control key */ 48 uint32_t :8; /*!< bit: 24..31 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 uint32_t reg; /*!< Type used for register access */ 51 } PAC_WRCTRL_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 #define PAC_WRCTRL_OFFSET 0x00 /**< \brief (PAC_WRCTRL offset) Write control */ 55 #define PAC_WRCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WRCTRL reset_value) Write control */ 56 57 #define PAC_WRCTRL_PERID_Pos 0 /**< \brief (PAC_WRCTRL) Peripheral identifier */ 58 #define PAC_WRCTRL_PERID_Msk (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos) 59 #define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos)) 60 #define PAC_WRCTRL_KEY_Pos 16 /**< \brief (PAC_WRCTRL) Peripheral access control key */ 61 #define PAC_WRCTRL_KEY_Msk (_U_(0xFF) << PAC_WRCTRL_KEY_Pos) 62 #define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos)) 63 #define PAC_WRCTRL_KEY_OFF_Val _U_(0x0) /**< \brief (PAC_WRCTRL) No action */ 64 #define PAC_WRCTRL_KEY_CLR_Val _U_(0x1) /**< \brief (PAC_WRCTRL) Clear protection */ 65 #define PAC_WRCTRL_KEY_SET_Val _U_(0x2) /**< \brief (PAC_WRCTRL) Set protection */ 66 #define PAC_WRCTRL_KEY_SETLCK_Val _U_(0x3) /**< \brief (PAC_WRCTRL) Set and lock protection */ 67 #define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos) 68 #define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos) 69 #define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos) 70 #define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos) 71 #define PAC_WRCTRL_MASK _U_(0x00FFFFFF) /**< \brief (PAC_WRCTRL) MASK Register */ 72 73 /* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */ 74 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 75 typedef union { 76 struct { 77 uint8_t ERREO:1; /*!< bit: 0 Peripheral acess error event output */ 78 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 79 } bit; /*!< Structure used for bit access */ 80 uint8_t reg; /*!< Type used for register access */ 81 } PAC_EVCTRL_Type; 82 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 83 84 #define PAC_EVCTRL_OFFSET 0x04 /**< \brief (PAC_EVCTRL offset) Event control */ 85 #define PAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (PAC_EVCTRL reset_value) Event control */ 86 87 #define PAC_EVCTRL_ERREO_Pos 0 /**< \brief (PAC_EVCTRL) Peripheral acess error event output */ 88 #define PAC_EVCTRL_ERREO (_U_(0x1) << PAC_EVCTRL_ERREO_Pos) 89 #define PAC_EVCTRL_MASK _U_(0x01) /**< \brief (PAC_EVCTRL) MASK Register */ 90 91 /* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */ 92 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 93 typedef union { 94 struct { 95 uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt disable */ 96 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 97 } bit; /*!< Structure used for bit access */ 98 uint8_t reg; /*!< Type used for register access */ 99 } PAC_INTENCLR_Type; 100 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 101 102 #define PAC_INTENCLR_OFFSET 0x08 /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */ 103 #define PAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */ 104 105 #define PAC_INTENCLR_ERR_Pos 0 /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */ 106 #define PAC_INTENCLR_ERR (_U_(0x1) << PAC_INTENCLR_ERR_Pos) 107 #define PAC_INTENCLR_MASK _U_(0x01) /**< \brief (PAC_INTENCLR) MASK Register */ 108 109 /* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */ 110 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 111 typedef union { 112 struct { 113 uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt enable */ 114 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 115 } bit; /*!< Structure used for bit access */ 116 uint8_t reg; /*!< Type used for register access */ 117 } PAC_INTENSET_Type; 118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 119 120 #define PAC_INTENSET_OFFSET 0x09 /**< \brief (PAC_INTENSET offset) Interrupt enable set */ 121 #define PAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */ 122 123 #define PAC_INTENSET_ERR_Pos 0 /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */ 124 #define PAC_INTENSET_ERR (_U_(0x1) << PAC_INTENSET_ERR_Pos) 125 #define PAC_INTENSET_MASK _U_(0x01) /**< \brief (PAC_INTENSET) MASK Register */ 126 127 /* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */ 128 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 129 typedef union { // __I to avoid read-modify-write on write-to-clear register 130 struct { 131 __I uint32_t FLASH_:1; /*!< bit: 0 FLASH */ 132 __I uint32_t HSRAMCM0P_:1; /*!< bit: 1 HSRAMCM0P */ 133 __I uint32_t HSRAMDSU_:1; /*!< bit: 2 HSRAMDSU */ 134 __I uint32_t HPB1_:1; /*!< bit: 3 HPB1 */ 135 __I uint32_t H2LBRIDGES_:1; /*!< bit: 4 H2LBRIDGES */ 136 __I uint32_t :11; /*!< bit: 5..15 Reserved */ 137 __I uint32_t HPB0_:1; /*!< bit: 16 HPB0 */ 138 __I uint32_t HPB2_:1; /*!< bit: 17 HPB2 */ 139 __I uint32_t HPB3_:1; /*!< bit: 18 HPB3 */ 140 __I uint32_t HPB4_:1; /*!< bit: 19 HPB4 */ 141 __I uint32_t :1; /*!< bit: 20 Reserved */ 142 __I uint32_t LPRAMHS_:1; /*!< bit: 21 LPRAMHS */ 143 __I uint32_t LPRAMPICOP_:1; /*!< bit: 22 LPRAMPICOP */ 144 __I uint32_t LPRAMDMAC_:1; /*!< bit: 23 LPRAMDMAC */ 145 __I uint32_t L2HBRIDGES_:1; /*!< bit: 24 L2HBRIDGES */ 146 __I uint32_t HSRAMLP_:1; /*!< bit: 25 HSRAMLP */ 147 __I uint32_t :6; /*!< bit: 26..31 Reserved */ 148 } bit; /*!< Structure used for bit access */ 149 uint32_t reg; /*!< Type used for register access */ 150 } PAC_INTFLAGAHB_Type; 151 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 152 153 #define PAC_INTFLAGAHB_OFFSET 0x10 /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */ 154 #define PAC_INTFLAGAHB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */ 155 156 #define PAC_INTFLAGAHB_FLASH_Pos 0 /**< \brief (PAC_INTFLAGAHB) FLASH */ 157 #define PAC_INTFLAGAHB_FLASH (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos) 158 #define PAC_INTFLAGAHB_HSRAMCM0P_Pos 1 /**< \brief (PAC_INTFLAGAHB) HSRAMCM0P */ 159 #define PAC_INTFLAGAHB_HSRAMCM0P (_U_(0x1) << PAC_INTFLAGAHB_HSRAMCM0P_Pos) 160 #define PAC_INTFLAGAHB_HSRAMDSU_Pos 2 /**< \brief (PAC_INTFLAGAHB) HSRAMDSU */ 161 #define PAC_INTFLAGAHB_HSRAMDSU (_U_(0x1) << PAC_INTFLAGAHB_HSRAMDSU_Pos) 162 #define PAC_INTFLAGAHB_HPB1_Pos 3 /**< \brief (PAC_INTFLAGAHB) HPB1 */ 163 #define PAC_INTFLAGAHB_HPB1 (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos) 164 #define PAC_INTFLAGAHB_H2LBRIDGES_Pos 4 /**< \brief (PAC_INTFLAGAHB) H2LBRIDGES */ 165 #define PAC_INTFLAGAHB_H2LBRIDGES (_U_(0x1) << PAC_INTFLAGAHB_H2LBRIDGES_Pos) 166 #define PAC_INTFLAGAHB_HPB0_Pos 16 /**< \brief (PAC_INTFLAGAHB) HPB0 */ 167 #define PAC_INTFLAGAHB_HPB0 (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos) 168 #define PAC_INTFLAGAHB_HPB2_Pos 17 /**< \brief (PAC_INTFLAGAHB) HPB2 */ 169 #define PAC_INTFLAGAHB_HPB2 (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos) 170 #define PAC_INTFLAGAHB_HPB3_Pos 18 /**< \brief (PAC_INTFLAGAHB) HPB3 */ 171 #define PAC_INTFLAGAHB_HPB3 (_U_(0x1) << PAC_INTFLAGAHB_HPB3_Pos) 172 #define PAC_INTFLAGAHB_HPB4_Pos 19 /**< \brief (PAC_INTFLAGAHB) HPB4 */ 173 #define PAC_INTFLAGAHB_HPB4 (_U_(0x1) << PAC_INTFLAGAHB_HPB4_Pos) 174 #define PAC_INTFLAGAHB_LPRAMHS_Pos 21 /**< \brief (PAC_INTFLAGAHB) LPRAMHS */ 175 #define PAC_INTFLAGAHB_LPRAMHS (_U_(0x1) << PAC_INTFLAGAHB_LPRAMHS_Pos) 176 #define PAC_INTFLAGAHB_LPRAMPICOP_Pos 22 /**< \brief (PAC_INTFLAGAHB) LPRAMPICOP */ 177 #define PAC_INTFLAGAHB_LPRAMPICOP (_U_(0x1) << PAC_INTFLAGAHB_LPRAMPICOP_Pos) 178 #define PAC_INTFLAGAHB_LPRAMDMAC_Pos 23 /**< \brief (PAC_INTFLAGAHB) LPRAMDMAC */ 179 #define PAC_INTFLAGAHB_LPRAMDMAC (_U_(0x1) << PAC_INTFLAGAHB_LPRAMDMAC_Pos) 180 #define PAC_INTFLAGAHB_L2HBRIDGES_Pos 24 /**< \brief (PAC_INTFLAGAHB) L2HBRIDGES */ 181 #define PAC_INTFLAGAHB_L2HBRIDGES (_U_(0x1) << PAC_INTFLAGAHB_L2HBRIDGES_Pos) 182 #define PAC_INTFLAGAHB_HSRAMLP_Pos 25 /**< \brief (PAC_INTFLAGAHB) HSRAMLP */ 183 #define PAC_INTFLAGAHB_HSRAMLP (_U_(0x1) << PAC_INTFLAGAHB_HSRAMLP_Pos) 184 #define PAC_INTFLAGAHB_MASK _U_(0x03EF001F) /**< \brief (PAC_INTFLAGAHB) MASK Register */ 185 186 /* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */ 187 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 188 typedef union { // __I to avoid read-modify-write on write-to-clear register 189 struct { 190 __I uint32_t PM_:1; /*!< bit: 0 PM */ 191 __I uint32_t MCLK_:1; /*!< bit: 1 MCLK */ 192 __I uint32_t RSTC_:1; /*!< bit: 2 RSTC */ 193 __I uint32_t OSCCTRL_:1; /*!< bit: 3 OSCCTRL */ 194 __I uint32_t OSC32KCTRL_:1; /*!< bit: 4 OSC32KCTRL */ 195 __I uint32_t SUPC_:1; /*!< bit: 5 SUPC */ 196 __I uint32_t GCLK_:1; /*!< bit: 6 GCLK */ 197 __I uint32_t WDT_:1; /*!< bit: 7 WDT */ 198 __I uint32_t RTC_:1; /*!< bit: 8 RTC */ 199 __I uint32_t EIC_:1; /*!< bit: 9 EIC */ 200 __I uint32_t PORT_:1; /*!< bit: 10 PORT */ 201 __I uint32_t :21; /*!< bit: 11..31 Reserved */ 202 } bit; /*!< Structure used for bit access */ 203 uint32_t reg; /*!< Type used for register access */ 204 } PAC_INTFLAGA_Type; 205 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 206 207 #define PAC_INTFLAGA_OFFSET 0x14 /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */ 208 #define PAC_INTFLAGA_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */ 209 210 #define PAC_INTFLAGA_PM_Pos 0 /**< \brief (PAC_INTFLAGA) PM */ 211 #define PAC_INTFLAGA_PM (_U_(0x1) << PAC_INTFLAGA_PM_Pos) 212 #define PAC_INTFLAGA_MCLK_Pos 1 /**< \brief (PAC_INTFLAGA) MCLK */ 213 #define PAC_INTFLAGA_MCLK (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos) 214 #define PAC_INTFLAGA_RSTC_Pos 2 /**< \brief (PAC_INTFLAGA) RSTC */ 215 #define PAC_INTFLAGA_RSTC (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos) 216 #define PAC_INTFLAGA_OSCCTRL_Pos 3 /**< \brief (PAC_INTFLAGA) OSCCTRL */ 217 #define PAC_INTFLAGA_OSCCTRL (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos) 218 #define PAC_INTFLAGA_OSC32KCTRL_Pos 4 /**< \brief (PAC_INTFLAGA) OSC32KCTRL */ 219 #define PAC_INTFLAGA_OSC32KCTRL (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos) 220 #define PAC_INTFLAGA_SUPC_Pos 5 /**< \brief (PAC_INTFLAGA) SUPC */ 221 #define PAC_INTFLAGA_SUPC (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos) 222 #define PAC_INTFLAGA_GCLK_Pos 6 /**< \brief (PAC_INTFLAGA) GCLK */ 223 #define PAC_INTFLAGA_GCLK (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos) 224 #define PAC_INTFLAGA_WDT_Pos 7 /**< \brief (PAC_INTFLAGA) WDT */ 225 #define PAC_INTFLAGA_WDT (_U_(0x1) << PAC_INTFLAGA_WDT_Pos) 226 #define PAC_INTFLAGA_RTC_Pos 8 /**< \brief (PAC_INTFLAGA) RTC */ 227 #define PAC_INTFLAGA_RTC (_U_(0x1) << PAC_INTFLAGA_RTC_Pos) 228 #define PAC_INTFLAGA_EIC_Pos 9 /**< \brief (PAC_INTFLAGA) EIC */ 229 #define PAC_INTFLAGA_EIC (_U_(0x1) << PAC_INTFLAGA_EIC_Pos) 230 #define PAC_INTFLAGA_PORT_Pos 10 /**< \brief (PAC_INTFLAGA) PORT */ 231 #define PAC_INTFLAGA_PORT (_U_(0x1) << PAC_INTFLAGA_PORT_Pos) 232 #define PAC_INTFLAGA_MASK _U_(0x000007FF) /**< \brief (PAC_INTFLAGA) MASK Register */ 233 234 /* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */ 235 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 236 typedef union { // __I to avoid read-modify-write on write-to-clear register 237 struct { 238 __I uint32_t USB_:1; /*!< bit: 0 USB */ 239 __I uint32_t DSU_:1; /*!< bit: 1 DSU */ 240 __I uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL */ 241 __I uint32_t MTB_:1; /*!< bit: 3 MTB */ 242 __I uint32_t :28; /*!< bit: 4..31 Reserved */ 243 } bit; /*!< Structure used for bit access */ 244 uint32_t reg; /*!< Type used for register access */ 245 } PAC_INTFLAGB_Type; 246 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 247 248 #define PAC_INTFLAGB_OFFSET 0x18 /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */ 249 #define PAC_INTFLAGB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */ 250 251 #define PAC_INTFLAGB_USB_Pos 0 /**< \brief (PAC_INTFLAGB) USB */ 252 #define PAC_INTFLAGB_USB (_U_(0x1) << PAC_INTFLAGB_USB_Pos) 253 #define PAC_INTFLAGB_DSU_Pos 1 /**< \brief (PAC_INTFLAGB) DSU */ 254 #define PAC_INTFLAGB_DSU (_U_(0x1) << PAC_INTFLAGB_DSU_Pos) 255 #define PAC_INTFLAGB_NVMCTRL_Pos 2 /**< \brief (PAC_INTFLAGB) NVMCTRL */ 256 #define PAC_INTFLAGB_NVMCTRL (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos) 257 #define PAC_INTFLAGB_MTB_Pos 3 /**< \brief (PAC_INTFLAGB) MTB */ 258 #define PAC_INTFLAGB_MTB (_U_(0x1) << PAC_INTFLAGB_MTB_Pos) 259 #define PAC_INTFLAGB_MASK _U_(0x0000000F) /**< \brief (PAC_INTFLAGB) MASK Register */ 260 261 /* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */ 262 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 263 typedef union { // __I to avoid read-modify-write on write-to-clear register 264 struct { 265 __I uint32_t SERCOM0_:1; /*!< bit: 0 SERCOM0 */ 266 __I uint32_t SERCOM1_:1; /*!< bit: 1 SERCOM1 */ 267 __I uint32_t SERCOM2_:1; /*!< bit: 2 SERCOM2 */ 268 __I uint32_t SERCOM3_:1; /*!< bit: 3 SERCOM3 */ 269 __I uint32_t SERCOM4_:1; /*!< bit: 4 SERCOM4 */ 270 __I uint32_t TCC0_:1; /*!< bit: 5 TCC0 */ 271 __I uint32_t TCC1_:1; /*!< bit: 6 TCC1 */ 272 __I uint32_t TCC2_:1; /*!< bit: 7 TCC2 */ 273 __I uint32_t TC0_:1; /*!< bit: 8 TC0 */ 274 __I uint32_t TC1_:1; /*!< bit: 9 TC1 */ 275 __I uint32_t TC2_:1; /*!< bit: 10 TC2 */ 276 __I uint32_t TC3_:1; /*!< bit: 11 TC3 */ 277 __I uint32_t DAC_:1; /*!< bit: 12 DAC */ 278 __I uint32_t AES_:1; /*!< bit: 13 AES */ 279 __I uint32_t TRNG_:1; /*!< bit: 14 TRNG */ 280 __I uint32_t :17; /*!< bit: 15..31 Reserved */ 281 } bit; /*!< Structure used for bit access */ 282 uint32_t reg; /*!< Type used for register access */ 283 } PAC_INTFLAGC_Type; 284 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 285 286 #define PAC_INTFLAGC_OFFSET 0x1C /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */ 287 #define PAC_INTFLAGC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */ 288 289 #define PAC_INTFLAGC_SERCOM0_Pos 0 /**< \brief (PAC_INTFLAGC) SERCOM0 */ 290 #define PAC_INTFLAGC_SERCOM0 (_U_(0x1) << PAC_INTFLAGC_SERCOM0_Pos) 291 #define PAC_INTFLAGC_SERCOM1_Pos 1 /**< \brief (PAC_INTFLAGC) SERCOM1 */ 292 #define PAC_INTFLAGC_SERCOM1 (_U_(0x1) << PAC_INTFLAGC_SERCOM1_Pos) 293 #define PAC_INTFLAGC_SERCOM2_Pos 2 /**< \brief (PAC_INTFLAGC) SERCOM2 */ 294 #define PAC_INTFLAGC_SERCOM2 (_U_(0x1) << PAC_INTFLAGC_SERCOM2_Pos) 295 #define PAC_INTFLAGC_SERCOM3_Pos 3 /**< \brief (PAC_INTFLAGC) SERCOM3 */ 296 #define PAC_INTFLAGC_SERCOM3 (_U_(0x1) << PAC_INTFLAGC_SERCOM3_Pos) 297 #define PAC_INTFLAGC_SERCOM4_Pos 4 /**< \brief (PAC_INTFLAGC) SERCOM4 */ 298 #define PAC_INTFLAGC_SERCOM4 (_U_(0x1) << PAC_INTFLAGC_SERCOM4_Pos) 299 #define PAC_INTFLAGC_TCC0_Pos 5 /**< \brief (PAC_INTFLAGC) TCC0 */ 300 #define PAC_INTFLAGC_TCC0 (_U_(0x1) << PAC_INTFLAGC_TCC0_Pos) 301 #define PAC_INTFLAGC_TCC1_Pos 6 /**< \brief (PAC_INTFLAGC) TCC1 */ 302 #define PAC_INTFLAGC_TCC1 (_U_(0x1) << PAC_INTFLAGC_TCC1_Pos) 303 #define PAC_INTFLAGC_TCC2_Pos 7 /**< \brief (PAC_INTFLAGC) TCC2 */ 304 #define PAC_INTFLAGC_TCC2 (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos) 305 #define PAC_INTFLAGC_TC0_Pos 8 /**< \brief (PAC_INTFLAGC) TC0 */ 306 #define PAC_INTFLAGC_TC0 (_U_(0x1) << PAC_INTFLAGC_TC0_Pos) 307 #define PAC_INTFLAGC_TC1_Pos 9 /**< \brief (PAC_INTFLAGC) TC1 */ 308 #define PAC_INTFLAGC_TC1 (_U_(0x1) << PAC_INTFLAGC_TC1_Pos) 309 #define PAC_INTFLAGC_TC2_Pos 10 /**< \brief (PAC_INTFLAGC) TC2 */ 310 #define PAC_INTFLAGC_TC2 (_U_(0x1) << PAC_INTFLAGC_TC2_Pos) 311 #define PAC_INTFLAGC_TC3_Pos 11 /**< \brief (PAC_INTFLAGC) TC3 */ 312 #define PAC_INTFLAGC_TC3 (_U_(0x1) << PAC_INTFLAGC_TC3_Pos) 313 #define PAC_INTFLAGC_DAC_Pos 12 /**< \brief (PAC_INTFLAGC) DAC */ 314 #define PAC_INTFLAGC_DAC (_U_(0x1) << PAC_INTFLAGC_DAC_Pos) 315 #define PAC_INTFLAGC_AES_Pos 13 /**< \brief (PAC_INTFLAGC) AES */ 316 #define PAC_INTFLAGC_AES (_U_(0x1) << PAC_INTFLAGC_AES_Pos) 317 #define PAC_INTFLAGC_TRNG_Pos 14 /**< \brief (PAC_INTFLAGC) TRNG */ 318 #define PAC_INTFLAGC_TRNG (_U_(0x1) << PAC_INTFLAGC_TRNG_Pos) 319 #define PAC_INTFLAGC_MASK _U_(0x00007FFF) /**< \brief (PAC_INTFLAGC) MASK Register */ 320 321 /* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */ 322 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 323 typedef union { // __I to avoid read-modify-write on write-to-clear register 324 struct { 325 __I uint32_t EVSYS_:1; /*!< bit: 0 EVSYS */ 326 __I uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 */ 327 __I uint32_t TC4_:1; /*!< bit: 2 TC4 */ 328 __I uint32_t ADC_:1; /*!< bit: 3 ADC */ 329 __I uint32_t AC_:1; /*!< bit: 4 AC */ 330 __I uint32_t PTC_:1; /*!< bit: 5 PTC */ 331 __I uint32_t :1; /*!< bit: 6 Reserved */ 332 __I uint32_t CCL_:1; /*!< bit: 7 CCL */ 333 __I uint32_t :24; /*!< bit: 8..31 Reserved */ 334 } bit; /*!< Structure used for bit access */ 335 uint32_t reg; /*!< Type used for register access */ 336 } PAC_INTFLAGD_Type; 337 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 338 339 #define PAC_INTFLAGD_OFFSET 0x20 /**< \brief (PAC_INTFLAGD offset) Peripheral interrupt flag status - Bridge D */ 340 #define PAC_INTFLAGD_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGD reset_value) Peripheral interrupt flag status - Bridge D */ 341 342 #define PAC_INTFLAGD_EVSYS_Pos 0 /**< \brief (PAC_INTFLAGD) EVSYS */ 343 #define PAC_INTFLAGD_EVSYS (_U_(0x1) << PAC_INTFLAGD_EVSYS_Pos) 344 #define PAC_INTFLAGD_SERCOM5_Pos 1 /**< \brief (PAC_INTFLAGD) SERCOM5 */ 345 #define PAC_INTFLAGD_SERCOM5 (_U_(0x1) << PAC_INTFLAGD_SERCOM5_Pos) 346 #define PAC_INTFLAGD_TC4_Pos 2 /**< \brief (PAC_INTFLAGD) TC4 */ 347 #define PAC_INTFLAGD_TC4 (_U_(0x1) << PAC_INTFLAGD_TC4_Pos) 348 #define PAC_INTFLAGD_ADC_Pos 3 /**< \brief (PAC_INTFLAGD) ADC */ 349 #define PAC_INTFLAGD_ADC (_U_(0x1) << PAC_INTFLAGD_ADC_Pos) 350 #define PAC_INTFLAGD_AC_Pos 4 /**< \brief (PAC_INTFLAGD) AC */ 351 #define PAC_INTFLAGD_AC (_U_(0x1) << PAC_INTFLAGD_AC_Pos) 352 #define PAC_INTFLAGD_PTC_Pos 5 /**< \brief (PAC_INTFLAGD) PTC */ 353 #define PAC_INTFLAGD_PTC (_U_(0x1) << PAC_INTFLAGD_PTC_Pos) 354 #define PAC_INTFLAGD_CCL_Pos 7 /**< \brief (PAC_INTFLAGD) CCL */ 355 #define PAC_INTFLAGD_CCL (_U_(0x1) << PAC_INTFLAGD_CCL_Pos) 356 #define PAC_INTFLAGD_MASK _U_(0x000000BF) /**< \brief (PAC_INTFLAGD) MASK Register */ 357 358 /* -------- PAC_INTFLAGE : (PAC Offset: 0x24) (R/W 32) Peripheral interrupt flag status - Bridge E -------- */ 359 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 360 typedef union { // __I to avoid read-modify-write on write-to-clear register 361 struct { 362 __I uint32_t PAC_:1; /*!< bit: 0 PAC */ 363 __I uint32_t DMAC_:1; /*!< bit: 1 DMAC */ 364 __I uint32_t :30; /*!< bit: 2..31 Reserved */ 365 } bit; /*!< Structure used for bit access */ 366 uint32_t reg; /*!< Type used for register access */ 367 } PAC_INTFLAGE_Type; 368 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 369 370 #define PAC_INTFLAGE_OFFSET 0x24 /**< \brief (PAC_INTFLAGE offset) Peripheral interrupt flag status - Bridge E */ 371 #define PAC_INTFLAGE_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGE reset_value) Peripheral interrupt flag status - Bridge E */ 372 373 #define PAC_INTFLAGE_PAC_Pos 0 /**< \brief (PAC_INTFLAGE) PAC */ 374 #define PAC_INTFLAGE_PAC (_U_(0x1) << PAC_INTFLAGE_PAC_Pos) 375 #define PAC_INTFLAGE_DMAC_Pos 1 /**< \brief (PAC_INTFLAGE) DMAC */ 376 #define PAC_INTFLAGE_DMAC (_U_(0x1) << PAC_INTFLAGE_DMAC_Pos) 377 #define PAC_INTFLAGE_MASK _U_(0x00000003) /**< \brief (PAC_INTFLAGE) MASK Register */ 378 379 /* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/ 32) Peripheral write protection status - Bridge A -------- */ 380 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 381 typedef union { 382 struct { 383 uint32_t PM_:1; /*!< bit: 0 PM APB Protect Enable */ 384 uint32_t MCLK_:1; /*!< bit: 1 MCLK APB Protect Enable */ 385 uint32_t RSTC_:1; /*!< bit: 2 RSTC APB Protect Enable */ 386 uint32_t OSCCTRL_:1; /*!< bit: 3 OSCCTRL APB Protect Enable */ 387 uint32_t OSC32KCTRL_:1; /*!< bit: 4 OSC32KCTRL APB Protect Enable */ 388 uint32_t SUPC_:1; /*!< bit: 5 SUPC APB Protect Enable */ 389 uint32_t GCLK_:1; /*!< bit: 6 GCLK APB Protect Enable */ 390 uint32_t WDT_:1; /*!< bit: 7 WDT APB Protect Enable */ 391 uint32_t RTC_:1; /*!< bit: 8 RTC APB Protect Enable */ 392 uint32_t EIC_:1; /*!< bit: 9 EIC APB Protect Enable */ 393 uint32_t PORT_:1; /*!< bit: 10 PORT APB Protect Enable */ 394 uint32_t :21; /*!< bit: 11..31 Reserved */ 395 } bit; /*!< Structure used for bit access */ 396 uint32_t reg; /*!< Type used for register access */ 397 } PAC_STATUSA_Type; 398 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 399 400 #define PAC_STATUSA_OFFSET 0x34 /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */ 401 #define PAC_STATUSA_RESETVALUE _U_(0x00003000) /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */ 402 403 #define PAC_STATUSA_PM_Pos 0 /**< \brief (PAC_STATUSA) PM APB Protect Enable */ 404 #define PAC_STATUSA_PM (_U_(0x1) << PAC_STATUSA_PM_Pos) 405 #define PAC_STATUSA_MCLK_Pos 1 /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */ 406 #define PAC_STATUSA_MCLK (_U_(0x1) << PAC_STATUSA_MCLK_Pos) 407 #define PAC_STATUSA_RSTC_Pos 2 /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */ 408 #define PAC_STATUSA_RSTC (_U_(0x1) << PAC_STATUSA_RSTC_Pos) 409 #define PAC_STATUSA_OSCCTRL_Pos 3 /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */ 410 #define PAC_STATUSA_OSCCTRL (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos) 411 #define PAC_STATUSA_OSC32KCTRL_Pos 4 /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */ 412 #define PAC_STATUSA_OSC32KCTRL (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos) 413 #define PAC_STATUSA_SUPC_Pos 5 /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */ 414 #define PAC_STATUSA_SUPC (_U_(0x1) << PAC_STATUSA_SUPC_Pos) 415 #define PAC_STATUSA_GCLK_Pos 6 /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */ 416 #define PAC_STATUSA_GCLK (_U_(0x1) << PAC_STATUSA_GCLK_Pos) 417 #define PAC_STATUSA_WDT_Pos 7 /**< \brief (PAC_STATUSA) WDT APB Protect Enable */ 418 #define PAC_STATUSA_WDT (_U_(0x1) << PAC_STATUSA_WDT_Pos) 419 #define PAC_STATUSA_RTC_Pos 8 /**< \brief (PAC_STATUSA) RTC APB Protect Enable */ 420 #define PAC_STATUSA_RTC (_U_(0x1) << PAC_STATUSA_RTC_Pos) 421 #define PAC_STATUSA_EIC_Pos 9 /**< \brief (PAC_STATUSA) EIC APB Protect Enable */ 422 #define PAC_STATUSA_EIC (_U_(0x1) << PAC_STATUSA_EIC_Pos) 423 #define PAC_STATUSA_PORT_Pos 10 /**< \brief (PAC_STATUSA) PORT APB Protect Enable */ 424 #define PAC_STATUSA_PORT (_U_(0x1) << PAC_STATUSA_PORT_Pos) 425 #define PAC_STATUSA_MASK _U_(0x000007FF) /**< \brief (PAC_STATUSA) MASK Register */ 426 427 /* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/ 32) Peripheral write protection status - Bridge B -------- */ 428 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 429 typedef union { 430 struct { 431 uint32_t USB_:1; /*!< bit: 0 USB APB Protect Enable */ 432 uint32_t DSU_:1; /*!< bit: 1 DSU APB Protect Enable */ 433 uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Protect Enable */ 434 uint32_t MTB_:1; /*!< bit: 3 MTB APB Protect Enable */ 435 uint32_t :28; /*!< bit: 4..31 Reserved */ 436 } bit; /*!< Structure used for bit access */ 437 uint32_t reg; /*!< Type used for register access */ 438 } PAC_STATUSB_Type; 439 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 440 441 #define PAC_STATUSB_OFFSET 0x38 /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */ 442 #define PAC_STATUSB_RESETVALUE _U_(0x00000002) /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */ 443 444 #define PAC_STATUSB_USB_Pos 0 /**< \brief (PAC_STATUSB) USB APB Protect Enable */ 445 #define PAC_STATUSB_USB (_U_(0x1) << PAC_STATUSB_USB_Pos) 446 #define PAC_STATUSB_DSU_Pos 1 /**< \brief (PAC_STATUSB) DSU APB Protect Enable */ 447 #define PAC_STATUSB_DSU (_U_(0x1) << PAC_STATUSB_DSU_Pos) 448 #define PAC_STATUSB_NVMCTRL_Pos 2 /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */ 449 #define PAC_STATUSB_NVMCTRL (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos) 450 #define PAC_STATUSB_MTB_Pos 3 /**< \brief (PAC_STATUSB) MTB APB Protect Enable */ 451 #define PAC_STATUSB_MTB (_U_(0x1) << PAC_STATUSB_MTB_Pos) 452 #define PAC_STATUSB_MASK _U_(0x0000000F) /**< \brief (PAC_STATUSB) MASK Register */ 453 454 /* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/ 32) Peripheral write protection status - Bridge C -------- */ 455 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 456 typedef union { 457 struct { 458 uint32_t SERCOM0_:1; /*!< bit: 0 SERCOM0 APB Protect Enable */ 459 uint32_t SERCOM1_:1; /*!< bit: 1 SERCOM1 APB Protect Enable */ 460 uint32_t SERCOM2_:1; /*!< bit: 2 SERCOM2 APB Protect Enable */ 461 uint32_t SERCOM3_:1; /*!< bit: 3 SERCOM3 APB Protect Enable */ 462 uint32_t SERCOM4_:1; /*!< bit: 4 SERCOM4 APB Protect Enable */ 463 uint32_t TCC0_:1; /*!< bit: 5 TCC0 APB Protect Enable */ 464 uint32_t TCC1_:1; /*!< bit: 6 TCC1 APB Protect Enable */ 465 uint32_t TCC2_:1; /*!< bit: 7 TCC2 APB Protect Enable */ 466 uint32_t TC0_:1; /*!< bit: 8 TC0 APB Protect Enable */ 467 uint32_t TC1_:1; /*!< bit: 9 TC1 APB Protect Enable */ 468 uint32_t TC2_:1; /*!< bit: 10 TC2 APB Protect Enable */ 469 uint32_t TC3_:1; /*!< bit: 11 TC3 APB Protect Enable */ 470 uint32_t DAC_:1; /*!< bit: 12 DAC APB Protect Enable */ 471 uint32_t AES_:1; /*!< bit: 13 AES APB Protect Enable */ 472 uint32_t TRNG_:1; /*!< bit: 14 TRNG APB Protect Enable */ 473 uint32_t :17; /*!< bit: 15..31 Reserved */ 474 } bit; /*!< Structure used for bit access */ 475 uint32_t reg; /*!< Type used for register access */ 476 } PAC_STATUSC_Type; 477 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 478 479 #define PAC_STATUSC_OFFSET 0x3C /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */ 480 #define PAC_STATUSC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */ 481 482 #define PAC_STATUSC_SERCOM0_Pos 0 /**< \brief (PAC_STATUSC) SERCOM0 APB Protect Enable */ 483 #define PAC_STATUSC_SERCOM0 (_U_(0x1) << PAC_STATUSC_SERCOM0_Pos) 484 #define PAC_STATUSC_SERCOM1_Pos 1 /**< \brief (PAC_STATUSC) SERCOM1 APB Protect Enable */ 485 #define PAC_STATUSC_SERCOM1 (_U_(0x1) << PAC_STATUSC_SERCOM1_Pos) 486 #define PAC_STATUSC_SERCOM2_Pos 2 /**< \brief (PAC_STATUSC) SERCOM2 APB Protect Enable */ 487 #define PAC_STATUSC_SERCOM2 (_U_(0x1) << PAC_STATUSC_SERCOM2_Pos) 488 #define PAC_STATUSC_SERCOM3_Pos 3 /**< \brief (PAC_STATUSC) SERCOM3 APB Protect Enable */ 489 #define PAC_STATUSC_SERCOM3 (_U_(0x1) << PAC_STATUSC_SERCOM3_Pos) 490 #define PAC_STATUSC_SERCOM4_Pos 4 /**< \brief (PAC_STATUSC) SERCOM4 APB Protect Enable */ 491 #define PAC_STATUSC_SERCOM4 (_U_(0x1) << PAC_STATUSC_SERCOM4_Pos) 492 #define PAC_STATUSC_TCC0_Pos 5 /**< \brief (PAC_STATUSC) TCC0 APB Protect Enable */ 493 #define PAC_STATUSC_TCC0 (_U_(0x1) << PAC_STATUSC_TCC0_Pos) 494 #define PAC_STATUSC_TCC1_Pos 6 /**< \brief (PAC_STATUSC) TCC1 APB Protect Enable */ 495 #define PAC_STATUSC_TCC1 (_U_(0x1) << PAC_STATUSC_TCC1_Pos) 496 #define PAC_STATUSC_TCC2_Pos 7 /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */ 497 #define PAC_STATUSC_TCC2 (_U_(0x1) << PAC_STATUSC_TCC2_Pos) 498 #define PAC_STATUSC_TC0_Pos 8 /**< \brief (PAC_STATUSC) TC0 APB Protect Enable */ 499 #define PAC_STATUSC_TC0 (_U_(0x1) << PAC_STATUSC_TC0_Pos) 500 #define PAC_STATUSC_TC1_Pos 9 /**< \brief (PAC_STATUSC) TC1 APB Protect Enable */ 501 #define PAC_STATUSC_TC1 (_U_(0x1) << PAC_STATUSC_TC1_Pos) 502 #define PAC_STATUSC_TC2_Pos 10 /**< \brief (PAC_STATUSC) TC2 APB Protect Enable */ 503 #define PAC_STATUSC_TC2 (_U_(0x1) << PAC_STATUSC_TC2_Pos) 504 #define PAC_STATUSC_TC3_Pos 11 /**< \brief (PAC_STATUSC) TC3 APB Protect Enable */ 505 #define PAC_STATUSC_TC3 (_U_(0x1) << PAC_STATUSC_TC3_Pos) 506 #define PAC_STATUSC_DAC_Pos 12 /**< \brief (PAC_STATUSC) DAC APB Protect Enable */ 507 #define PAC_STATUSC_DAC (_U_(0x1) << PAC_STATUSC_DAC_Pos) 508 #define PAC_STATUSC_AES_Pos 13 /**< \brief (PAC_STATUSC) AES APB Protect Enable */ 509 #define PAC_STATUSC_AES (_U_(0x1) << PAC_STATUSC_AES_Pos) 510 #define PAC_STATUSC_TRNG_Pos 14 /**< \brief (PAC_STATUSC) TRNG APB Protect Enable */ 511 #define PAC_STATUSC_TRNG (_U_(0x1) << PAC_STATUSC_TRNG_Pos) 512 #define PAC_STATUSC_MASK _U_(0x00007FFF) /**< \brief (PAC_STATUSC) MASK Register */ 513 514 /* -------- PAC_STATUSD : (PAC Offset: 0x40) (R/ 32) Peripheral write protection status - Bridge D -------- */ 515 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 516 typedef union { 517 struct { 518 uint32_t EVSYS_:1; /*!< bit: 0 EVSYS APB Protect Enable */ 519 uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Protect Enable */ 520 uint32_t TC4_:1; /*!< bit: 2 TC4 APB Protect Enable */ 521 uint32_t ADC_:1; /*!< bit: 3 ADC APB Protect Enable */ 522 uint32_t AC_:1; /*!< bit: 4 AC APB Protect Enable */ 523 uint32_t PTC_:1; /*!< bit: 5 PTC APB Protect Enable */ 524 uint32_t :1; /*!< bit: 6 Reserved */ 525 uint32_t CCL_:1; /*!< bit: 7 CCL APB Protect Enable */ 526 uint32_t :24; /*!< bit: 8..31 Reserved */ 527 } bit; /*!< Structure used for bit access */ 528 uint32_t reg; /*!< Type used for register access */ 529 } PAC_STATUSD_Type; 530 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 531 532 #define PAC_STATUSD_OFFSET 0x40 /**< \brief (PAC_STATUSD offset) Peripheral write protection status - Bridge D */ 533 #define PAC_STATUSD_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSD reset_value) Peripheral write protection status - Bridge D */ 534 535 #define PAC_STATUSD_EVSYS_Pos 0 /**< \brief (PAC_STATUSD) EVSYS APB Protect Enable */ 536 #define PAC_STATUSD_EVSYS (_U_(0x1) << PAC_STATUSD_EVSYS_Pos) 537 #define PAC_STATUSD_SERCOM5_Pos 1 /**< \brief (PAC_STATUSD) SERCOM5 APB Protect Enable */ 538 #define PAC_STATUSD_SERCOM5 (_U_(0x1) << PAC_STATUSD_SERCOM5_Pos) 539 #define PAC_STATUSD_TC4_Pos 2 /**< \brief (PAC_STATUSD) TC4 APB Protect Enable */ 540 #define PAC_STATUSD_TC4 (_U_(0x1) << PAC_STATUSD_TC4_Pos) 541 #define PAC_STATUSD_ADC_Pos 3 /**< \brief (PAC_STATUSD) ADC APB Protect Enable */ 542 #define PAC_STATUSD_ADC (_U_(0x1) << PAC_STATUSD_ADC_Pos) 543 #define PAC_STATUSD_AC_Pos 4 /**< \brief (PAC_STATUSD) AC APB Protect Enable */ 544 #define PAC_STATUSD_AC (_U_(0x1) << PAC_STATUSD_AC_Pos) 545 #define PAC_STATUSD_PTC_Pos 5 /**< \brief (PAC_STATUSD) PTC APB Protect Enable */ 546 #define PAC_STATUSD_PTC (_U_(0x1) << PAC_STATUSD_PTC_Pos) 547 #define PAC_STATUSD_CCL_Pos 7 /**< \brief (PAC_STATUSD) CCL APB Protect Enable */ 548 #define PAC_STATUSD_CCL (_U_(0x1) << PAC_STATUSD_CCL_Pos) 549 #define PAC_STATUSD_MASK _U_(0x000000BF) /**< \brief (PAC_STATUSD) MASK Register */ 550 551 /* -------- PAC_STATUSE : (PAC Offset: 0x44) (R/ 32) Peripheral write protection status - Bridge E -------- */ 552 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 553 typedef union { 554 struct { 555 uint32_t PAC_:1; /*!< bit: 0 PAC APB Protect Enable */ 556 uint32_t DMAC_:1; /*!< bit: 1 DMAC APB Protect Enable */ 557 uint32_t :30; /*!< bit: 2..31 Reserved */ 558 } bit; /*!< Structure used for bit access */ 559 uint32_t reg; /*!< Type used for register access */ 560 } PAC_STATUSE_Type; 561 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 562 563 #define PAC_STATUSE_OFFSET 0x44 /**< \brief (PAC_STATUSE offset) Peripheral write protection status - Bridge E */ 564 #define PAC_STATUSE_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSE reset_value) Peripheral write protection status - Bridge E */ 565 566 #define PAC_STATUSE_PAC_Pos 0 /**< \brief (PAC_STATUSE) PAC APB Protect Enable */ 567 #define PAC_STATUSE_PAC (_U_(0x1) << PAC_STATUSE_PAC_Pos) 568 #define PAC_STATUSE_DMAC_Pos 1 /**< \brief (PAC_STATUSE) DMAC APB Protect Enable */ 569 #define PAC_STATUSE_DMAC (_U_(0x1) << PAC_STATUSE_DMAC_Pos) 570 #define PAC_STATUSE_MASK _U_(0x00000003) /**< \brief (PAC_STATUSE) MASK Register */ 571 572 /** \brief PAC hardware registers */ 573 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 574 typedef struct { 575 __IO PAC_WRCTRL_Type WRCTRL; /**< \brief Offset: 0x00 (R/W 32) Write control */ 576 __IO PAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event control */ 577 RoReg8 Reserved1[0x3]; 578 __IO PAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt enable clear */ 579 __IO PAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt enable set */ 580 RoReg8 Reserved2[0x6]; 581 __IO PAC_INTFLAGAHB_Type INTFLAGAHB; /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */ 582 __IO PAC_INTFLAGA_Type INTFLAGA; /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */ 583 __IO PAC_INTFLAGB_Type INTFLAGB; /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */ 584 __IO PAC_INTFLAGC_Type INTFLAGC; /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */ 585 __IO PAC_INTFLAGD_Type INTFLAGD; /**< \brief Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */ 586 __IO PAC_INTFLAGE_Type INTFLAGE; /**< \brief Offset: 0x24 (R/W 32) Peripheral interrupt flag status - Bridge E */ 587 RoReg8 Reserved3[0xC]; 588 __I PAC_STATUSA_Type STATUSA; /**< \brief Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */ 589 __I PAC_STATUSB_Type STATUSB; /**< \brief Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */ 590 __I PAC_STATUSC_Type STATUSC; /**< \brief Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */ 591 __I PAC_STATUSD_Type STATUSD; /**< \brief Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D */ 592 __I PAC_STATUSE_Type STATUSE; /**< \brief Offset: 0x44 (R/ 32) Peripheral write protection status - Bridge E */ 593 } Pac; 594 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 595 596 /*@}*/ 597 598 #endif /* _SAMR34_PAC_COMPONENT_ */ 599
